71 lines
2.3 KiB
Plaintext
71 lines
2.3 KiB
Plaintext
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* Rockchip PX30 Clock and Reset Unit
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The PX30 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
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- compatible: CRU should be "rockchip,px30-cru"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- clocks: A list of phandle + clock-specifier pairs for the clocks listed
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in clock-names
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- clock-names: Should contain the following:
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- "xin24m" for both PMUCRU and CRU
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- "gpll" for CRU (sourced from PMUCRU)
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Optional Properties:
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- rockchip,grf: phandle to the syscon managing the "general register files"
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If missing, pll rates are not changeable, due to the missing pll lock status.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
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used in device tree sources. Similar macros exist for the reset sources in
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these files.
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External clocks:
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required,
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- "xin32k" - rtc clock - optional,
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- "i2sx_clkin" - external I2S clock - optional,
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- "gmac_clkin" - external GMAC clock - optional
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Example: Clock controller node:
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pmucru: clock-controller@ff2bc000 {
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compatible = "rockchip,px30-pmucru";
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reg = <0x0 0xff2bc000 0x0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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cru: clock-controller@ff2b0000 {
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compatible = "rockchip,px30-cru";
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reg = <0x0 0xff2b0000 0x0 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart0: serial@ff030000 {
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compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff030000 0x0 0x100>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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