102 lines
2.8 KiB
YAML
102 lines
2.8 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SDM845
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maintainers:
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SDM845.
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See also dt-bindings/clock/qcom,dispcc-sdm845.h.
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properties:
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compatible:
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const: qcom,sdm845-dispcc
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# NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
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# The code had to use hardcoded mechanisms to find the input clocks.
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# New dts files should have these clocks.
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: GPLL0 div source from GCC
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Byte clock from DSI PHY1
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- description: Pixel clock from DSI PHY1
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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clock-names:
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items:
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- const: bi_tcxo
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- const: gcc_disp_gpll0_clk_src
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- const: gcc_disp_gpll0_div_clk_src
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dsi1_phy_pll_out_byteclk
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- const: dsi1_phy_pll_out_dsiclk
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- const: dp_link_clk_divsel_ten
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- const: dp_vco_divided_clk_src_mux
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@af00000 {
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compatible = "qcom,sdm845-dispcc";
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reg = <0x0af00000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_CLK_SRC>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi1_phy 0>,
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<&dsi1_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>;
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clock-names = "bi_tcxo",
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"gcc_disp_gpll0_clk_src",
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"gcc_disp_gpll0_div_clk_src",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_byteclk",
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"dsi1_phy_pll_out_dsiclk",
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"dp_link_clk_divsel_ten",
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"dp_vco_divided_clk_src_mux";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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