70 lines
1.7 KiB
YAML
70 lines
1.7 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra Clock and Reset Controller
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maintainers:
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- Jon Hunter <jonathanh@nvidia.com>
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- Thierry Reding <thierry.reding@gmail.com>
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description: |
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The Clock and Reset (CAR) is the HW module responsible for muxing and gating
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Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
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CLKGEN provides the registers to program the PLLs. It controls most of
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the clock source programming and most of the clock dividers.
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CLKGEN input signals include the external clock for the reference frequency
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(12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
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Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
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RSTGEN provides the registers needed to control resetting of each block in
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the Tegra system.
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properties:
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compatible:
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enum:
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- nvidia,tegra20-car
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- nvidia,tegra30-car
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- nvidia,tegra114-car
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- nvidia,tegra210-car
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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"#reset-cells":
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra20-car.h>
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car: clock-controller@60006000 {
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compatible = "nvidia,tegra20-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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usb-controller@c5004000 {
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compatible = "nvidia,tegra20-ehci";
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reg = <0xc5004000 0x4000>;
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clocks = <&car TEGRA20_CLK_USB2>;
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resets = <&car TEGRA20_CLK_USB2>;
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};
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