54 lines
1.6 KiB
Plaintext
54 lines
1.6 KiB
Plaintext
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* Amlogic GXBB Clock and Reset Unit
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The Amlogic GXBB clock controller generates and supplies clock to various
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controllers within the SoC.
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Required Properties:
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- compatible: should be:
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"amlogic,gxbb-clkc" for GXBB SoC,
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"amlogic,gxl-clkc" for GXL and GXM SoC,
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"amlogic,axg-clkc" for AXG SoC.
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"amlogic,g12a-clkc" for G12A SoC.
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"amlogic,g12b-clkc" for G12B SoC.
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"amlogic,sm1-clkc" for SM1 SoC.
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- clocks : list of clock phandle, one for each entry clock-names.
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- clock-names : should contain the following:
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* "xtal": the platform xtal
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
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used in device tree sources.
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Parent node should have the following properties :
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- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
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"amlogic,meson-axg-hhi-sysctrl"
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- reg: base address and size of the HHI system control register space.
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Example: Clock controller node:
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sysctrl: system-controller@0 {
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compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
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reg = <0 0 0 0x400>;
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clkc: clock-controller {
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#clock-cells = <1>;
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compatible = "amlogic,gxbb-clkc";
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clocks = <&xtal>;
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clock-names = "xtal";
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};
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart_AO: serial@c81004c0 {
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compatible = "amlogic,meson-uart";
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reg = <0xc81004c0 0x14>;
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interrupts = <0 90 1>;
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clocks = <&clkc CLKID_CLK81>;
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};
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