65 lines
2.4 KiB
Plaintext
65 lines
2.4 KiB
Plaintext
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* Amlogic GXBB AO Clock and Reset Unit
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The Amlogic GXBB AO clock controller generates and supplies clock to various
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controllers within the Always-On part of the SoC.
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Required Properties:
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- compatible: value should be different for each SoC family as :
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- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
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- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
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- GXM (S912) : "amlogic,meson-gxm-aoclkc"
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- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
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- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
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followed by the common "amlogic,meson-gx-aoclkc"
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- clocks: list of clock phandle, one for each entry clock-names.
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- clock-names: should contain the following:
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* "xtal" : the platform xtal
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* "mpeg-clk" : the main clock controller mother clock (aka clk81)
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* "ext-32k-0" : external 32kHz reference #0 if any (optional)
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* "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
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* "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
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used in device tree sources.
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- #reset-cells: should be 1.
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Each reset is assigned an identifier and client nodes can use this identifier
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to specify the reset which they consume. All available resets are defined as
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preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
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used in device tree sources.
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Parent node should have the following properties :
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- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
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- reg: base address and size of the AO system control register space.
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Example: AO Clock controller node:
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ao_sysctrl: sys-ctrl@0 {
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compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
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reg = <0x0 0x0 0x0 0x100>;
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clkc_AO: clock-controller {
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compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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clocks = <&xtal>, <&clkc CLKID_CLK81>;
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clock-names = "xtal", "mpeg-clk";
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};
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Example: UART controller node that consumes the clock and reset generated
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by the clock controller:
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uart_AO: serial@4c0 {
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compatible = "amlogic,meson-uart";
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reg = <0x4c0 0x14>;
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interrupts = <0 90 1>;
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clocks = <&clkc_AO CLKID_AO_UART1>;
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resets = <&clkc_AO RESET_AO_UART1>;
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};
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