25 lines
670 B
C
25 lines
670 B
C
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (C) 2019 SiFive, Inc.
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* Wesley Terpstra
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* Paul Walmsley
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* Zong Li
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*/
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#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
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#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
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/* Clock indexes for use by Device Tree data and the PRCI driver */
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#define PRCI_CLK_COREPLL 0
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#define PRCI_CLK_DDRPLL 1
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#define PRCI_CLK_GEMGXLPLL 2
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#define PRCI_CLK_DVFSCOREPLL 3
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#define PRCI_CLK_HFPCLKPLL 4
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#define PRCI_CLK_CLTXPLL 5
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#define PRCI_CLK_TLCLK 6
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#define PRCI_CLK_PCLK 7
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#define PRCI_CLK_PCIE_AUX 8
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#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */
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