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150 lines
6.2 KiB
C
150 lines
6.2 KiB
C
// Copyright (c) 2022 Cesanta Software Limited
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// All rights reserved
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#include "mip.h"
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#if MG_ENABLE_MIP
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struct stm32_eth {
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uint32_t MACCR, MACFFR, MACHTHR, MACHTLR, MACMIIAR, MACMIIDR, MACFCR,
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MACVLANTR, RESERVED0[2], MACRWUFFR, MACPMTCSR, RESERVED1, MACDBGR, MACSR,
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MACIMR, MACA0HR, MACA0LR, MACA1HR, MACA1LR, MACA2HR, MACA2LR, MACA3HR,
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MACA3LR, RESERVED2[40], MMCCR, MMCRIR, MMCTIR, MMCRIMR, MMCTIMR,
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RESERVED3[14], MMCTGFSCCR, MMCTGFMSCCR, RESERVED4[5], MMCTGFCR,
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RESERVED5[10], MMCRFCECR, MMCRFAECR, RESERVED6[10], MMCRGUFCR,
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RESERVED7[334], PTPTSCR, PTPSSIR, PTPTSHR, PTPTSLR, PTPTSHUR, PTPTSLUR,
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PTPTSAR, PTPTTHR, PTPTTLR, RESERVED8, PTPTSSR, PTPPPSCR, RESERVED9[564],
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DMABMR, DMATPDR, DMARPDR, DMARDLAR, DMATDLAR, DMASR, DMAOMR, DMAIER,
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DMAMFBOCR, DMARSWTR, RESERVED10[8], DMACHTDR, DMACHRDR, DMACHTBAR,
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DMACHRBAR;
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};
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#define ETH ((struct stm32_eth *) (uintptr_t) 0x40028000)
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#define BIT(x) ((uint32_t) 1 << (x))
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#define ETH_PKT_SIZE 1540 // Max frame size
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_DS 4 // Descriptor size (words)
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static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
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static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
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static void (*s_rx)(void *, size_t, void *); // Recv callback
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static void *s_rxdata; // Recv callback data
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static void *s_userdata; // Driver data
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enum { PHY_ADDR = 0, PHY_BCR = 0, PHY_BSR = 1 }; // PHY constants
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static inline void spin(volatile uint32_t count) {
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while (count--) asm("nop");
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}
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static uint32_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ETH->MACMIIAR &= (7 << 2);
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ETH->MACMIIAR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6);
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ETH->MACMIIAR |= BIT(0);
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while (ETH->MACMIIAR & BIT(0)) spin(1);
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return ETH->MACMIIDR;
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}
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static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
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ETH->MACMIIDR = val;
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ETH->MACMIIAR &= (7 << 2);
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ETH->MACMIIAR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6) | BIT(1);
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ETH->MACMIIAR |= BIT(0);
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while (ETH->MACMIIAR & BIT(0)) spin(1);
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}
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static void mip_driver_stm32_init(void *userdata) {
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s_userdata = userdata;
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// Init RX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_rxdesc[i][0] = BIT(31); // Own
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s_rxdesc[i][1] = sizeof(s_rxbuf[i]) | BIT(14); // 2nd address chained
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s_rxdesc[i][2] = (uint32_t) (uintptr_t) s_rxbuf[i]; // Point to data buffer
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s_rxdesc[i][3] =
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(uint32_t) (uintptr_t) s_rxdesc[(i + 1) % ETH_DESC_CNT]; // Chain
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}
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// Init TX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_txdesc[i][2] = (uint32_t) (uintptr_t) s_txbuf[i]; // Buf pointer
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s_txdesc[i][3] =
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(uint32_t) (uintptr_t) s_txdesc[(i + 1) % ETH_DESC_CNT]; // Chain
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}
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ETH->DMABMR |= BIT(0); // Software reset
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while ((ETH->DMABMR & BIT(0)) != 0) spin(1); // Wait until done
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// NOTE(cpq): we do not use extended descriptor bit 7, and do not use
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// hardware checksum. Therefore, descriptor size is 4, not 8
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// ETH->DMABMR = BIT(13) | BIT(16) | BIT(22) | BIT(23) | BIT(25);
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ETH->MACIMR = BIT(3) | BIT(9); // Mask timestamp & PMT IT
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ETH->MACMIIAR = 4 << 2; // MDC clock 150-216 MHz, 38.8.1
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ETH->MACFCR = BIT(7); // Disable zero quarta pause
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ETH->MACFFR = BIT(31); // Receive all
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(15)); // Reset PHY
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(12)); // Set autonegotiation
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ETH->DMARDLAR = (uint32_t) (uintptr_t) s_rxdesc; // RX descriptors
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ETH->DMATDLAR = (uint32_t) (uintptr_t) s_txdesc; // RX descriptors
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ETH->DMAIER = BIT(6) | BIT(16); // RIE, NISE
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ETH->MACCR = BIT(2) | BIT(3) | BIT(11) | BIT(14); // RE, TE, Duplex, Fast
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ETH->DMAOMR = BIT(1) | BIT(13) | BIT(21) | BIT(25); // SR, ST, TSF, RSF
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}
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static void mip_driver_stm32_setrx(void (*rx)(void *, size_t, void *),
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void *rxdata) {
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s_rx = rx;
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s_rxdata = rxdata;
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}
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static uint32_t s_txno;
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static size_t mip_driver_stm32_tx(const void *buf, size_t len, void *userdata) {
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if (len > sizeof(s_txbuf[s_txno])) {
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printf("%s: frame too big, %ld\n", __func__, (long) len);
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len = 0; // Frame is too big
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} else if ((s_txdesc[s_txno][0] & BIT(31))) {
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printf("%s: no free descr\n", __func__);
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len = 0; // All descriptors are busy, fail
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} else {
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][1] = (uint32_t) len; // Set data len
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s_txdesc[s_txno][0] = BIT(20) | BIT(28) | BIT(29) | BIT(30); // Chain,FS,LS
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s_txdesc[s_txno][0] |= BIT(31); // Set OWN bit - let DMA take over
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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uint32_t sr = ETH->DMASR;
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if (sr & BIT(2)) ETH->DMASR = BIT(2), ETH->DMATPDR = 0; // Resume
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if (sr & BIT(5)) ETH->DMASR = BIT(5), ETH->DMATPDR = 0; // if busy
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if (len == 0) printf("E: D0 %lx SR %lx\n", (long) s_txdesc[0][0], (long) sr);
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return len;
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(void) userdata;
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}
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static bool mip_driver_stm32_status(void *userdata) {
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uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
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return bsr & BIT(2) ? 1 : 0;
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(void) userdata;
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}
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void ETH_IRQHandler(void);
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void ETH_IRQHandler(void) {
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volatile uint32_t sr = ETH->DMASR;
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if (sr & BIT(6)) { // Frame received, loop
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for (uint32_t i = 0; i < ETH_DESC_CNT; i++) {
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if (s_rxdesc[i][0] & BIT(31)) continue;
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uint32_t len = ((s_rxdesc[i][0] >> 16) & (BIT(14) - 1));
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// printf("%lx %lu %lx %lx\n", i, len, s_rxdesc[i][0], sr);
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if (s_rx != NULL) s_rx(s_rxbuf[i], len > 4 ? len - 4 : len, s_rxdata);
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s_rxdesc[i][0] = BIT(31);
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}
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}
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if (sr & BIT(7)) ETH->DMARPDR = 0; // Resume RX
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ETH->DMASR = sr & ~(BIT(2) | BIT(7)); // Clear status
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}
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struct mip_driver mip_driver_stm32 = {.init = mip_driver_stm32_init,
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.tx = mip_driver_stm32_tx,
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.rxcb = mip_driver_stm32_setrx,
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.status = mip_driver_stm32_status};
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#endif // MG_ENABLE_MIP
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