mirror of
https://github.com/cesanta/mongoose.git
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100 lines
4.8 KiB
C
100 lines
4.8 KiB
C
// Copyright (c) 2022 Cesanta Software Limited
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// All rights reserved
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//
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// This software is dual-licensed: you can redistribute it and/or modify
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// it under the terms of the GNU Affero General Public License version 3 as
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// published by the Free Software Foundation. For the terms of this
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// license, see http://www.fsf.org/licensing/licenses/agpl-3.0.html
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//
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// You are free to use this software under the terms of the GNU General
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// Public License, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// See the GNU General Public License for more details.
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//
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// Alternatively, you can license this software under a commercial
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// license, please contact us at https://cesanta.com/contact.html
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#pragma once
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struct w5500 {
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uint8_t mac[6]; // MAC address
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void *spi; // Opaque SPI bus descriptor
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uint8_t (*txn)(void *, uint8_t); // SPI transaction
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void (*begin)(void *); // SPI begin
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void (*end)(void *); // SPI end
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};
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enum { W5500_CR = 0, W5500_S0 = 1, W5500_TX0 = 2, W5500_RX0 = 3 };
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static inline void w5500_txn(struct w5500 *w, uint8_t block, uint16_t addr,
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bool wr, void *buf, size_t len) {
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uint8_t *p = buf, cmd[] = {(uint8_t) (addr >> 8), (uint8_t) (addr & 255),
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(uint8_t) ((block << 3) | (wr ? 4 : 0))};
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w->begin(w->spi);
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for (size_t i = 0; i < sizeof(cmd); i++) w->txn(w->spi, cmd[i]);
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for (size_t i = 0; i < len; i++) {
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uint8_t r = w->txn(w->spi, p[i]);
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if (!wr) p[i] = r;
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}
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w->end(w->spi);
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}
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// clang-format off
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static inline void w5500_wn(struct w5500 *w, uint8_t block, uint16_t addr, void *buf, size_t len) { w5500_txn(w, block, addr, true, buf, len); }
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static inline void w5500_w1(struct w5500 *w, uint8_t block, uint16_t addr, uint8_t val) { w5500_wn(w, block, addr, &val, 1); }
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static inline void w5500_w2(struct w5500 *w, uint8_t block, uint16_t addr, uint16_t val) { uint8_t buf[2] = {(uint8_t) (val >> 8), (uint8_t) (val & 255)}; w5500_wn(w, block, addr, buf, sizeof(buf)); }
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static inline void w5500_rn(struct w5500 *w, uint8_t block, uint16_t addr, void *buf, size_t len) { w5500_txn(w, block, addr, false, buf, len); }
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static inline uint8_t w5500_r1(struct w5500 *w, uint8_t block, uint16_t addr) { uint8_t r = 0; w5500_rn(w, block, addr, &r, 1); return r; }
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static inline uint16_t w5500_r2(struct w5500 *w, uint8_t block, uint16_t addr) { uint8_t buf[2] = {0, 0}; w5500_rn(w, block, addr, buf, sizeof(buf)); return (uint16_t) ((buf[0] << 8) | buf[1]); }
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// clang-format on
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static inline uint8_t w5500_status(struct w5500 *w) {
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return w5500_r1(w, W5500_CR, 0x2e);
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}
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static inline uint16_t w5500_rx(struct w5500 *w, uint8_t *buf, uint16_t len) {
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uint16_t r = 0, n = 0, n2; // Read recv len
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while ((n2 = w5500_r2(w, W5500_S0, 0x26)) > n) n = n2; // Until it is stable
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// printf("RSR: %d\n", (int) n);
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if (n > 0) {
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uint16_t ptr = w5500_r2(w, W5500_S0, 0x28); // Get read pointer
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n = w5500_r2(w, W5500_RX0, ptr); // Read frame length
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if (n <= len + 2) r = n - 2, w5500_rn(w, W5500_RX0, ptr + 2, buf, r);
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w5500_w2(w, W5500_S0, 0x28, ptr + n); // Advance read pointer
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w5500_w1(w, W5500_S0, 1, 0x40); // Sock0 CR -> RECV
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// printf(" RX_RD: tot=%u n=%u r=%u\n", n2, n, r);
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}
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return r;
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}
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static inline uint16_t w5500_tx(struct w5500 *w, void *buf, uint16_t len) {
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uint16_t n = 0;
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while (n < len) n = w5500_r2(w, W5500_S0, 0x20); // Wait for space
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uint16_t ptr = w5500_r2(w, W5500_S0, 0x24); // Get write pointer
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w5500_wn(w, W5500_TX0, ptr, buf, len); // Write data
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w5500_w2(w, W5500_S0, 0x24, ptr + len); // Advance write pointer
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w5500_w1(w, W5500_S0, 1, 0x20); // Sock0 CR -> SEND
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for (int i = 0; i < 40; i++) {
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uint8_t ir = w5500_r1(w, W5500_S0, 2); // Read S0 IR
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if (ir == 0) continue;
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// printf("IR %d, len=%d, free=%d, ptr %d\n", ir, (int) len, (int) n, ptr);
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w5500_w1(w, W5500_S0, 2, ir); // Write S0 IR: clear it!
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if (ir & 8) len = 0; // Timeout. Report error
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if (ir & (16 | 8)) break; // Stop on SEND_OK or timeout
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}
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return len;
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}
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static inline bool w5500_init(struct w5500 *w) {
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w->end(w->spi);
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w5500_w1(w, W5500_CR, 0, 0x80); // Reset chip: CR -> 0x80
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w5500_w1(w, W5500_CR, 0x2e, 0); // CR PHYCFGR -> reset
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w5500_w1(w, W5500_CR, 0x2e, 0xf8); // CR PHYCFGR -> set
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// w5500_wn(w, W5500_CR, 9, w->mac, 6); // Set source MAC
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w5500_w1(w, W5500_S0, 0x1e, 16); // Sock0 RX buf size
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w5500_w1(w, W5500_S0, 0x1f, 16); // Sock0 TX buf size
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w5500_w1(w, W5500_S0, 0, 4); // Sock0 MR -> MACRAW
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w5500_w1(w, W5500_S0, 1, 1); // Sock0 CR -> OPEN
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return w5500_r1(w, W5500_S0, 3) == 0x42; // Sock0 SR == MACRAW
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}
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