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49 lines
2.0 KiB
C
49 lines
2.0 KiB
C
// Copyright (c) 2024 Cesanta Software Limited
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// All rights reserved
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//
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// This file contains essentials required by the CMSIS:
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// uint32_t SystemCoreClock - holds the system core clock value
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// SystemInit() - initialises the system, e.g. sets up clocks
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#include "hal.h"
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#include "fsl_clock.h"
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#include "fsl_dcdc.h"
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#include "fsl_pmu.h"
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uint32_t SystemCoreClock = SYS_FREQUENCY;
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// - 15.4 clock tree
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// 15.4: M7_CLK_ROOT
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// 15.5.3 Table 15-4; 15.9.1.2; select PLL_ARM_CLK
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// 15.8.2 PLL Enable Sequence
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// - Datasheet 4.1.3, Table 11: "Overdrive" run mode particulars
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void SystemInit(void) { // Called automatically by startup code (ints masked)
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
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asm("DSB");
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asm("ISB");
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// 79.5.2: Disable watchdogS after reset (unlocked)
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RTWDOG3->CS &= ~RTWDOG_CS_EN_MASK;
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RTWDOG3->TOVAL = 0xFFFF;
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while (RTWDOG3->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock
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while ((RTWDOG3->CS & RTWDOG_CS_RCS_MASK) == 0)
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spin(1); // wait for new config
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RTWDOG4->CS &= ~RTWDOG_CS_EN_MASK;
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RTWDOG4->TOVAL = 0xFFFF;
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while (RTWDOG4->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock
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while ((RTWDOG4->CS & RTWDOG_CS_RCS_MASK) == 0)
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spin(1); // wait for new config
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ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1);
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while ((ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK) == 0)
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spin(1); // wait until it is stable
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DCDC_BootIntoDCM(DCDC); // Enable "overdrive" mode as needed
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DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
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PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, (OCOTP->FUSEN[7].FUSE & BIT(4)) == 0);
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const clock_arm_pll_config_t armpll = {.loopDivider = 166, .postDivider = 0};
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CLOCK_InitArmPll(&armpll); // Set clock to 996MHz
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CCM->CLOCK_ROOT[0].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(4); // /1
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// rng_init(); // TRNG is part or CAAM and there is no info on that
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// NXP startup code calls SystemInit BEFORE initializing RAM...
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SysTick_Config(SYS_FREQUENCY / 1000); // Sys tick every 1ms
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}
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