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https://github.com/cesanta/mongoose.git
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245 lines
9.6 KiB
C
245 lines
9.6 KiB
C
// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define LED1 PIN(16, 1)
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#define LED2 PIN(16, 2)
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#define LED3 PIN(16, 3)
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#include "xmc7200d_e272k8384.h"
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#define BIT(x) (1UL << (x))
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define PIN(bank, num) ((bank << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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void hal_init(void);
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size_t hal_ram_free(void);
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size_t hal_ram_used(void);
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static inline void spin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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extern uint32_t SystemCoreClock;
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enum {PLL_FEEDBACK = 50, PLL_REF = 1, PLL_OUT = 4};
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#define CLK_IMO 8000000UL
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#define SYS_FREQUENCY ((CLK_IMO * PLL_FEEDBACK) / (PLL_REF * PLL_OUT))
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#ifndef UART_DEBUG
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#define UART_DEBUG SCB3
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#endif
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_HIGHZ = 0, GPIO_PULLUP = 2, GPIO_PULLDOWN = 3, GPIO_OPENDRAIN_LOW = 4,
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GPIO_OPENDRAIN_HIGH = 5, GPIO_STRONG = 6, GPIO_PULLUP_DOWN = 7};
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enum { GPIO_SPEED_LOW = 3, GPIO_SPEED_MEDIUM = 2, GPIO_SPEED_HIGH = 0};
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#undef GPIO
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#define GPIO_TypeDef GPIO_PRT_Type
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#define GPIO(N) ((GPIO_TypeDef *) (GPIO_BASE + 0x80 * (N)))
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static GPIO_TypeDef *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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(void) pin, (void) mode, (void) type, (void) speed, (void) pull, (void) af;
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t pinno = PINNO(pin);
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uint32_t msk, pos;
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// configure input / output direction
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if (mode == GPIO_MODE_INPUT) {
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gpio->CFG |= 1 << (4 * pinno + 3); // enable input buffer (IN_ENx)
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}
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if (af || (mode == GPIO_MODE_AF && af)) {
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// configure alternate function
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HSIOM_PRT_Type* hsiom = ((HSIOM_PRT_Type*) HSIOM) + PINBANK(pin);
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volatile uint32_t *port_sel = pinno < 4 ? &hsiom->PORT_SEL0 : &hsiom->PORT_SEL1;
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pos = 8 * (pinno % 4), msk = 0x1f << pos;
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*port_sel &= ~msk, *port_sel |= af << pos;
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}
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// configure driver mode
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msk = 7, pos = 4 * pinno;
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CLRSET(gpio->CFG, msk << pos, type << pos);
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// configure speed
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msk = 3, pos = 2 * pinno + 16;
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CLRSET(gpio->CFG_OUT, msk << pos, speed << pos);
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if (mode == GPIO_MODE_OUTPUT /*&& af == 0*/) {
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gpio->OUT_SET = (1 << pinno);
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}
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH,
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0, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_MEDIUM,
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0, 0);
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}
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static inline bool gpio_read(uint16_t pin) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t pinno = PINNO(pin);
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if (gpio->CFG & (1 << (4 * pinno + 3))) {
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// pin mode is input, reading from GPIO_PRT_IN
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return gpio->IN & (1 << pinno);
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} else {
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// pin mode is output, reading from GPIO_PRT_OUT
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return gpio->OUT & (1 << pinno);
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}
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}
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static inline void gpio_write(uint16_t pin, bool value) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t pinno = PINNO(pin);
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if (value) {
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gpio->OUT_SET = 1 << pinno;
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} else {
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gpio->OUT_CLR = 1 << pinno;
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}
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}
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static inline void gpio_toggle(uint16_t pin) {
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gpio_write(pin, !gpio_read(pin));
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}
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static inline void uart_init(volatile CySCB_Type *uart, unsigned long baud) {
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(void) uart, (void) baud;
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uint16_t rx = 0, tx = 0;
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if (uart == SCB3) {
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rx = PIN(13, 0), tx = PIN(13, 1);
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} else {
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return; // unsupported uart
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}
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// set pins
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gpio_init(rx, GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 17);
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gpio_init(tx, GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 17);
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// enable peripheral clock (18.6.2)
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// compute divider first (we choose 24 bit divider 0)
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unsigned long div = 0, frac = 0, ovs = 16;
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div = SYS_FREQUENCY / (baud * ovs);
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if (div == 0) div = 1;
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frac = SYS_FREQUENCY % (baud * ovs);
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frac = (frac * 100) / (baud * ovs);
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PERI_PCLK->GR[1].DIV_CMD = (3 << PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos) |
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PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk |
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PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk;
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PERI_PCLK->GR[1].DIV_CMD |= PERI_PCLK_GR_DIV_CMD_DISABLE_Msk; // disable divider
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PERI_PCLK->GR[1].DIV_24_5_CTL[0] = (((uint8_t) (div - 1)) << PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Pos) |
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(frac << PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Pos);
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PERI_PCLK->GR[1].DIV_CMD = (3 << PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos) |
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PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk |
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PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk;;
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PERI_PCLK->GR[1].DIV_CMD |= PERI_PCLK_GR_DIV_CMD_ENABLE_Msk; // enable divider
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PERI_PCLK->GR[1].CLOCK_CTL[PCLK_SCB3_CLOCK & 0xff] = 3 << PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Pos; // connect SCB3 to div_24_5_ctl[0]
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// configure UART interface
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uart->CTRL = ((ovs - 1) << SCB_CTRL_OVS_Pos) | (2 << SCB_CTRL_MODE_Pos);
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uart->UART_CTRL = 0;
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uart->UART_RX_CTRL = 1 << SCB_UART_RX_CTRL_STOP_BITS_Pos;
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uart->RX_CTRL = 7 << SCB_RX_CTRL_DATA_WIDTH_Pos;
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uart->UART_TX_CTRL = 1 << SCB_UART_TX_CTRL_STOP_BITS_Pos;
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uart->TX_CTRL = 7 << SCB_TX_CTRL_DATA_WIDTH_Pos;
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uart->TX_FIFO_CTRL = 1 << 16;
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uart->TX_FIFO_CTRL = 0;
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uart->CTRL |= 1 << SCB_CTRL_ENABLED_Pos;
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}
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static inline void uart_write_byte(volatile CySCB_Type *uart, uint8_t byte) {
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(void) byte; (void) uart;
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while((uart->INTR_TX & SCB_INTR_TX_EMPTY_Msk) == 0) spin(1);
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uart->TX_FIFO_WR = byte;
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uart->INTR_TX |= ~SCB_INTR_TX_EMPTY_Msk;
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}
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static inline void uart_write_buf(volatile CySCB_Type *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline void rng_init(void) {
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}
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static inline uint32_t rng_read(void) {
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return 0;
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}
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static inline void ethernet_init(void) {
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gpio_init(PIN(26, 0), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_REF_CLK
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gpio_init(PIN(26, 1), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TX_CTL
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gpio_init(PIN(26, 2), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TX_CLK
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gpio_init(PIN(26, 3), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_0
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gpio_init(PIN(26, 4), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_1
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gpio_init(PIN(26, 5), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_2
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gpio_init(PIN(26, 6), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_HIGH, 0, 27); // ETH1_TXD_3
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gpio_init(PIN(26, 7), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_0
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gpio_init(PIN(27, 0), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_1
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gpio_init(PIN(27, 1), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_2
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gpio_init(PIN(27, 2), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RXD_3
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gpio_init(PIN(27, 3), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RX_CTL
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gpio_init(PIN(27, 4), GPIO_MODE_INPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 27); // ETH1_RX_CLK
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gpio_init(PIN(27, 5), GPIO_MODE_INPUT, GPIO_STRONG, GPIO_SPEED_LOW, 0, 27); // ETH1_MDIO
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gpio_init(PIN(27, 6), GPIO_MODE_OUTPUT, GPIO_STRONG, GPIO_SPEED_LOW, 0, 27); // ETH1_MDC
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//gpio_init(PIN(27, 7), GPIO_MODE_OUTPUT, GPIO_HIGHZ, GPIO_SPEED_HIGH, 0, 0); // ETH1_RST
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CPUSS->CM7_0_SYSTEM_INT_CTL[eth_1_interrupt_eth_0_IRQn] = 0x80000003; // assign CPU interrupt #3
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NVIC->ISER[0] = 1 << 3;
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spin(10000000); // artificial delay to wait for PHY init
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}
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static inline void clock_init(void) {
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
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asm("DSB");
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asm("ISB");
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// configure PLL
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CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_BYPASS_SEL_Msk, BIT(29)); // First bypass PLL
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spin(10);
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SRSS->CLK_PLL400M[0].CONFIG &= ~CLK_PLL400M_CONFIG_ENABLE_Msk; // disable the PLL itself
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// IMO source generates a frequency of 8MHz. The final frequency will be
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// calculated as (CLK_IMO * feedback) / (reference * output_div)
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CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_FEEDBACK_DIV_Msk, PLL_FEEDBACK << CLK_PLL400M_CONFIG_FEEDBACK_DIV_Pos);
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CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_REFERENCE_DIV_Msk, PLL_REF << CLK_PLL400M_CONFIG_REFERENCE_DIV_Pos);
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CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_OUTPUT_DIV_Msk, PLL_OUT << CLK_PLL400M_CONFIG_OUTPUT_DIV_Pos);
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CLRSET(SRSS->CLK_PLL400M[0].CONFIG2, CLK_PLL400M_CONFIG2_FRAC_DIV_Msk, 0);
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CLRSET(SRSS->CLK_PLL400M[0].CONFIG2, CLK_PLL400M_CONFIG2_FRAC_DITHER_EN_Msk, 0);
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CLRSET(SRSS->CLK_PLL400M[0].CONFIG2, CLK_PLL400M_CONFIG2_FRAC_EN_Msk, 1 << CLK_PLL400M_CONFIG2_FRAC_EN_Pos);
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CLRSET(SRSS->CLK_PLL400M[0].CONFIG, CLK_PLL400M_CONFIG_BYPASS_SEL_Msk, 0);
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spin(10);
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SRSS->CLK_PLL400M[0].CONFIG |= CLK_PLL400M_CONFIG_ENABLE_Msk; // enable the PLL
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while (SRSS->CLK_PLL400M[0].CONFIG & 1) spin(1);
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// configure PATH1 with source set to IMO
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SRSS->CLK_PATH_SELECT[1] = 0;
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// enable CLK_HFx
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uint8_t clocks[] = {0, 1, 2, 3, 4, 5, 6};
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for (size_t i = 0; i < sizeof(clocks) / sizeof(uint8_t); i++) {
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CLRSET(SRSS->CLK_ROOT_SELECT[clocks[i]], SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk, 1); // choose PATH1
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CLRSET(SRSS->CLK_ROOT_SELECT[clocks[i]], SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Msk, 1 << SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Pos);
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if (clocks[i] != 0) // CLF_HF0 is already enabled
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SRSS->CLK_ROOT_SELECT[clocks[i]] |= SRSS_CLK_ROOT_SELECT_ENABLE_Msk; // enable clock root
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}
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// set systick frequency
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uint32_t tenms = SYS_FREQUENCY / 100 - 1; // number of cycles executed in 10ms
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CPUSS->SYSTICK_CTL = tenms | (3 << CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Pos); // select CLK_HF as source
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}
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