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203 lines
7.9 KiB
C
203 lines
7.9 KiB
C
// Copyright (c) 2024 Cesanta Software Limited
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// All rights reserved
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//
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// MCU and ek-ra6m4 eval board datasheets:
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// https://www.renesas.com/us/en/document/man/ra6m4-group-user-s-manual-hardware
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// https://www.renesas.com/us/en/document/man/ek-ra6m5-v1-users-manual
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#pragma once
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include "bsp_exceptions.h"
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#include "R7FA6M4AF.h"
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extern void hal_init(void);
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#define BIT(x) (1UL << (x))
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#define SETBITS(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define PIN(port, num) ((((port) - '0') << 8) | (num))
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#define PIN_NUM(pin) (pin & 255)
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#define PIN_PORT(pin) (pin >> 8)
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#define LED1 PIN('4', 15) // blue
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#define LED2 PIN('4', 4) // green
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#define LED3 PIN('4', 0) // red
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#define LED LED2 // Use green LED for blinking
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#define rng_read() 0
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#define rng_init()
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#define GENERATE_MAC_ADDRESS() \
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{ 2, 3, 4, 5, 6, 7 }
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// Clock
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// Board UM: P212 P213 24MHz xtal
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// - (8.1 Table 8.1) (50.3.1 Table 50.14): PLL 120 ~ 200 MHz; input 8 ~ 24 MHz.
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// System clock (ICLK) <= 200 MHz; PCLKA <= 100 MHz; PCLKB <= 50 MHz
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// - (8.2.2): ICLK >= other clocks of interest for us
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// - (8.7.3): FlashIF Clock (FCLK) (8.1 Table 8.1): 4 MHz to 50 MHz(P/E), up to
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// 50 MHz (R)
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// - (8.2.9): MOSCCR Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting
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// this register.
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// - (10.2.9) OPCCR : Operating Power Control Register, defaults to high-speed
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// mode
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// - (45.2.4) 1 wait state for SRAM (default);
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#define SYS_FREQUENCY 200000000
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#define PLL_MUL 49 // x25 ((n+1)/2)
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#define PLL_DIV 2 // /3 (n+1)
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#define ICLK_DIV 0 // /1 -> 200MHz (/(2^n))
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#define FCLK_DIV 2 // /4 -> 50MHz
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#define PCLKAD_DIV 1 // /2 -> 100MHz
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#define PCLKBC_DIV 2 // /4 -> 50MHz
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#define FLASH_MHZ (SYS_FREQUENCY / ((1 << FCLK_DIV) * 1000000))
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static inline void clock_init(void) {
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R_SYSTEM->PRCR = 0xA501; // enable writing to osc control regs (12.2.1)
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R_SYSTEM->MOSCWTCR = 9; // (8.2.5, 8.2.4)
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R_SYSTEM->MOSCCR = 0; // enable main oscillator, default cfg (20~24MHz)
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while (R_SYSTEM->OSCSF_b.MOSCSF == 0) (void) 0; // wait until it stabilizes
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R_SYSTEM->PLLCCR =
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(PLL_MUL << R_SYSTEM_PLLCCR_PLLMUL_Pos) |
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(PLL_DIV
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<< R_SYSTEM_PLLCCR_PLIDIV_Pos); // config PLL for MOSC /3 x 25 (8.2.4)
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R_SYSTEM->PLLCR = 0; // enable PLL
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R_SYSTEM->SCKDIVCR =
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(FCLK_DIV << R_SYSTEM_SCKDIVCR_FCK_Pos) |
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(ICLK_DIV << R_SYSTEM_SCKDIVCR_ICK_Pos) |
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(PCLKAD_DIV << R_SYSTEM_SCKDIVCR_BCK_Pos) |
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(PCLKAD_DIV << R_SYSTEM_SCKDIVCR_PCKA_Pos) |
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(PCLKBC_DIV << R_SYSTEM_SCKDIVCR_PCKB_Pos) |
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(PCLKBC_DIV << R_SYSTEM_SCKDIVCR_PCKC_Pos) |
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(PCLKAD_DIV << R_SYSTEM_SCKDIVCR_PCKD_Pos); // set dividers
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R_FCACHE->FLWT = 3; // flash: 3 wait states (47.4.3)
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R_FLAD->FCKMHZ = FLASH_MHZ; // flash: read speed optimization (47.4.28)
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R_FACI_HP->FPCKAR = (0x1E << 8) + FLASH_MHZ; // flash: write (47.4.26)
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while (R_SYSTEM->OSCSF_b.PLLSF == 0) (void) 0; // PLL stabilization
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while (R_FLAD->FCKMHZ != FLASH_MHZ) (void) 0; // flash module magic
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R_SYSTEM->SCKSCR = 5; // select PLL (8.2.3)
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}
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// GPIO
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#define GPIO(N) ((R_PORT0_Type *) (R_PORT0_BASE + 0x20 * (N)))
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF };
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t af) {
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R_PORT0_Type *gpio = GPIO(PIN_PORT(pin));
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if (mode == GPIO_MODE_OUTPUT) {
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gpio->PCNTR1 |= BIT(PIN_NUM(pin));
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} else if (mode == GPIO_MODE_INPUT) {
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gpio->PCNTR1 &= ~BIT(PIN_NUM(pin));
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} else { // GPIO_MODE_AF
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// TODO(): only non-analog supported (19.2.5)
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R_PMISC->PWPR_b.B0WI = 0; // (19.5.1--> (RM says this is PFS...)
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R_PMISC->PWPR_b.PFSWE = 1;
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R_PFS->PORT[PIN_PORT(pin)].PIN[PIN_NUM(pin)].PmnPFS_b.PMR = 0;
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R_PFS->PORT[PIN_PORT(pin)].PIN[PIN_NUM(pin)].PmnPFS_b.PSEL =
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af & (R_PFS_PORT_PIN_PmnPFS_PSEL_Msk >> R_PFS_PORT_PIN_PmnPFS_PSEL_Pos);
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R_PFS->PORT[PIN_PORT(pin)].PIN[PIN_NUM(pin)].PmnPFS_b.PMR = 1;
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R_PFS->PORT[PIN_PORT(pin)].PIN[PIN_NUM(pin)].PmnPFS_b.DSCR = 2; // high
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R_PMISC->PWPR_b.PFSWE = 0;
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R_PMISC->PWPR_b.B0WI = 1; // <--19.5.1)
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}
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, 0);
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, 0);
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}
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static inline bool gpio_read(uint16_t pin) {
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R_PORT0_Type *gpio = GPIO(PIN_PORT(pin));
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return gpio->PCNTR2 & BIT(PIN_NUM(pin)) ? true : false;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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R_PORT0_Type *gpio = GPIO(PIN_PORT(pin));
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gpio->PCNTR3 = BIT(PIN_NUM(pin)) << (val ? 0 : 16U);
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}
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static inline void gpio_toggle(uint16_t pin) {
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gpio_write(pin, !gpio_read(pin));
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}
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#ifndef UART_DEBUG
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#define UART_DEBUG R_SCI7
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#endif
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#define UART_TX PIN('6', 13) // SCI7
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#define UART_RX PIN('6', 14)
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// UART
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// (datasheet, after BSP rev.eng.) SCI uses PCLKA in this chip
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static inline void uart_init(R_SCI0_Type *uart, unsigned baud) {
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if (uart != R_SCI7) return;
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R_MSTP->MSTPCRB_b.MSTPB24 = 0; // enable SCI7
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(void) R_MSTP->MSTPCRB; // (10.10.15)
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uart->SCR = 0; // (29.3.7 -->) disable SCI
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uart->FCR_b.FM = 0; // disable FIFO
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uart->SIMR1 = 0; // disable I2C (default)
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uart->SPMR = 0; // disable SPI (default)
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uart->SCMR_b.SMIF = 0; // no smartcard (default)
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uart->SMR = 0; // async 8N1, use PCLK
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uart->SCMR_b.CHR1 = 1; // disable 9-bit mode (default)
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uart->SEMR = 0; // 16x clocking (other SCIs need internal clock setting)
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uart->SPTR = 3; // no inversions, high on idle
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uart->BRR = (uint8_t) (SYS_FREQUENCY / (32 * (1 << PCLKAD_DIV) * baud));
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gpio_init(UART_TX, GPIO_MODE_AF, 5); // (19.6)
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gpio_init(UART_RX, GPIO_MODE_AF, 5);
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(void) uart, (void) baud;
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uart->SCR = R_SCI0_SCR_TE_Msk | R_SCI0_SCR_RE_Msk; // enable Tx, Rx
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}
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static inline void uart_write_byte(R_SCI0_Type *uart, uint8_t byte) {
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uart->TDR = byte;
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while (uart->SSR_b.TDRE == 0) (void) 0;
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}
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static inline void uart_write_buf(R_SCI0_Type *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(R_SCI0_Type *uart) {
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return uart->SSR_b.RDRF; // If RDRF bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(R_SCI0_Type *uart) {
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return uart->RDR;
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}
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// Ethernet
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// - (13.3.2 Table 13.4) Event table: Event 0x16F, ETHER_EINT0
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// - (13.1) ICU (13.3.1) Interrupt Vector Table (13.5)
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// - Choose a IELSRx, that is IRQn=x in NVIC, write event number
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static inline void ethernet_init(void) {
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R_MSTP->MSTPCRB_b.MSTPB15 = 0; // enable ETHERC0 and EDMAC0
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(void) R_MSTP->MSTPCRB; // (10.10.15)
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// (Board manual: 4.3.3 Table 1, 6.1 Table 20) (RM: 19.6)
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R_SYSTEM->PRCR = 0xA502; // enable writing to next reg (12.2.1)
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R_SYSTEM->VBTICTLR = 0; // enable MDC pins (19.5.5) (11.2.6)
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gpio_init(PIN('4', 1), GPIO_MODE_AF, 0x17); // MDC
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gpio_init(PIN('4', 2), GPIO_MODE_AF, 0x17); // MDIO
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gpio_output(PIN('4', 3)); // PHY RST
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gpio_write(PIN('0', 2), 1); // prevent NAND_TREE
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gpio_write(PIN('4', 3), 0); // assert RST
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gpio_init(PIN('4', 5), GPIO_MODE_AF, 0x17); // TX_EN
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gpio_init(PIN('4', 6), GPIO_MODE_AF, 0x17); // TXD1
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gpio_init(PIN('7', 0), GPIO_MODE_AF, 0x17); // TXD0
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gpio_init(PIN('7', 1), GPIO_MODE_AF, 0x17); // REF50CK0
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gpio_init(PIN('7', 2), GPIO_MODE_AF, 0x17); // RXD0
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gpio_init(PIN('7', 3), GPIO_MODE_AF, 0x17); // RXD1
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gpio_init(PIN('7', 4), GPIO_MODE_AF, 0x17); // RX_ER
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gpio_init(PIN('7', 5), GPIO_MODE_AF, 0x17); // CRS_DV
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R_PMISC->PFENET_b.PHYMODE0 = 0; // select RMII
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for (volatile int i = 0; i < 0x2000; i++)
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(void) 0; // keep PHY RST low for a while
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gpio_write(PIN('4', 3), 1); // deassert RST
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gpio_input(PIN('0', 2)); // PHY IRQ, not used
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NVIC_EnableIRQ(0); // (13.5.1) no CMSIS support
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R_ICU->IELSR[0] = 0x16f; // (13.2.15)(13.5.4.1)
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}
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