mirror of
https://github.com/cesanta/mongoose.git
synced 2025-01-15 10:18:11 +08:00
229 lines
7.4 KiB
C
229 lines
7.4 KiB
C
#include "flash.h"
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#include "log.h"
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#include "ota.h"
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#if MG_OTA == MG_OTA_STM32F
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static bool mg_stm32f_write(void *, const void *, size_t);
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static bool mg_stm32f_swap(void);
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static struct mg_flash s_mg_flash_stm32f = {
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(void *) 0x08000000, // Start
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0, // Size, FLASH_SIZE_REG
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0, // Irregular sector size
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32, // Align, 256 bit
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mg_stm32f_write,
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mg_stm32f_swap,
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};
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#define MG_FLASH_BASE 0x40023c00
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#define MG_FLASH_KEYR 0x04
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#define MG_FLASH_SR 0x0c
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#define MG_FLASH_CR 0x10
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#define MG_FLASH_OPTCR 0x14
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#define MG_FLASH_SIZE_REG_F7 0x1FF0F442
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#define MG_FLASH_SIZE_REG_F4 0x1FFF7A22
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#define STM_DBGMCU_IDCODE 0xE0042000
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#define STM_DEV_ID (MG_REG(STM_DBGMCU_IDCODE) & (MG_BIT(12) - 1))
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#define SYSCFG_MEMRMP 0x40013800
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#define MG_FLASH_SIZE_REG_LOCATION \
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((STM_DEV_ID >= 0x449) ? MG_FLASH_SIZE_REG_F7 : MG_FLASH_SIZE_REG_F4)
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static size_t flash_size(void) {
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return (MG_REG(MG_FLASH_SIZE_REG_LOCATION) & 0xFFFF) * 1024;
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}
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MG_IRAM static int is_dualbank(void) {
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// only F42x/F43x series (0x419) support dual bank
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return STM_DEV_ID == 0x419;
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}
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MG_IRAM static void flash_unlock(void) {
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static bool unlocked = false;
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if (unlocked == false) {
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MG_REG(MG_FLASH_BASE + MG_FLASH_KEYR) = 0x45670123;
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MG_REG(MG_FLASH_BASE + MG_FLASH_KEYR) = 0xcdef89ab;
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unlocked = true;
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}
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}
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#define MG_FLASH_CONFIG_16_64_128 1 // used by STM32F7
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#define MG_FLASH_CONFIG_32_128_256 2 // used by STM32F4 and F2
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MG_IRAM static bool flash_page_start(volatile uint32_t *dst) {
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char *base = (char *) s_mg_flash_stm32f.start;
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char *end = base + s_mg_flash_stm32f.size;
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if (is_dualbank() && dst >= (uint32_t *) (base + (end - base) / 2)) {
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dst = (uint32_t *) ((uint32_t) dst - (end - base) / 2);
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}
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uint32_t flash_config = MG_FLASH_CONFIG_16_64_128;
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if (STM_DEV_ID >= 0x449) {
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flash_config = MG_FLASH_CONFIG_32_128_256;
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}
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volatile char *p = (char *) dst;
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if (p >= base && p < end) {
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if (p < base + 16 * 1024 * 4 * flash_config) {
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if ((p - base) % (16 * 1024 * flash_config) == 0) return true;
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} else if (p == base + 16 * 1024 * 4 * flash_config) {
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return true;
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} else if ((p - base) % (128 * 1024 * flash_config) == 0) {
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return true;
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}
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}
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return false;
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}
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MG_IRAM static int flash_sector(volatile uint32_t *addr) {
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char *base = (char *) s_mg_flash_stm32f.start;
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char *end = base + s_mg_flash_stm32f.size;
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bool addr_in_bank_2 = false;
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if (is_dualbank() && addr >= (uint32_t *) (base + (end - base) / 2)) {
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addr = (uint32_t *) ((uint32_t) addr - (end - base) / 2);
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addr_in_bank_2 = true;
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}
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volatile char *p = (char *) addr;
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uint32_t flash_config = MG_FLASH_CONFIG_16_64_128;
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if (STM_DEV_ID >= 0x449) {
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flash_config = MG_FLASH_CONFIG_32_128_256;
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}
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int sector = -1;
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if (p >= base && p < end) {
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if (p < base + 16 * 1024 * 4 * flash_config) {
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sector = (p - base) / (16 * 1024 * flash_config);
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} else if (p >= base + 64 * 1024 * flash_config &&
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p < base + 128 * 1024 * flash_config) {
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sector = 4;
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} else {
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sector = (p - base) / (128 * 1024 * flash_config) + 4;
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}
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}
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if (sector == -1) return -1;
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if (addr_in_bank_2) sector += 12; // a bank has 12 sectors
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return sector;
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}
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MG_IRAM static bool flash_is_err(void) {
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return MG_REG(MG_FLASH_BASE + MG_FLASH_SR) & ((MG_BIT(7) - 1) << 1);
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}
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MG_IRAM static void flash_wait(void) {
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while (MG_REG(MG_FLASH_BASE + MG_FLASH_SR) & (MG_BIT(16))) (void) 0;
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}
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MG_IRAM static void flash_clear_err(void) {
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flash_wait(); // Wait until ready
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MG_REG(MG_FLASH_BASE + MG_FLASH_SR) = 0xf2; // Clear all errors
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}
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MG_IRAM static bool mg_stm32f_erase(void *addr) {
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bool ok = false;
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if (flash_page_start(addr) == false) {
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MG_ERROR(("%p is not on a sector boundary", addr));
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} else {
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int sector = flash_sector(addr);
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if (sector < 0) return false;
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uint32_t sector_reg = sector;
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if (is_dualbank() && sector >= 12) {
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// 3.9.8 Flash control register (FLASH_CR) for F42xxx and F43xxx
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// BITS[7:3]
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sector_reg -= 12;
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sector_reg |= MG_BIT(4);
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}
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flash_unlock();
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flash_wait();
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uint32_t cr = MG_BIT(1); // SER
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cr |= MG_BIT(16); // STRT
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cr |= (sector_reg & 31) << 3; // sector
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MG_REG(MG_FLASH_BASE + MG_FLASH_CR) = cr;
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ok = !flash_is_err();
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MG_DEBUG(("Erase sector %lu @ %p %s. CR %#lx SR %#lx", sector, addr,
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ok ? "ok" : "fail", MG_REG(MG_FLASH_BASE + MG_FLASH_CR),
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MG_REG(MG_FLASH_BASE + MG_FLASH_SR)));
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// After we have erased the sector, set CR flags for programming
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// 2 << 8 is word write parallelism, bit(0) is PG. RM0385, section 3.7.5
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MG_REG(MG_FLASH_BASE + MG_FLASH_CR) = MG_BIT(0) | (2 << 8);
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flash_clear_err();
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}
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return ok;
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}
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MG_IRAM static bool mg_stm32f_swap(void) {
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// STM32 F42x/F43x support dual bank, however, the memory mapping
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// change will not be carried through a hard reset. Therefore, we will use
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// the single bank approach for this family as well.
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return true;
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}
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static bool s_flash_irq_disabled;
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MG_IRAM static bool mg_stm32f_write(void *addr,
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const void *buf,
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size_t len) {
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if ((len % s_mg_flash_stm32f.align) != 0) {
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MG_ERROR(("%lu is not aligned to %lu", len, s_mg_flash_stm32f.align));
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return false;
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}
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uint32_t *dst = (uint32_t *) addr;
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uint32_t *src = (uint32_t *) buf;
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uint32_t *end = (uint32_t *) ((char *) buf + len);
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bool ok = true;
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MG_ARM_DISABLE_IRQ();
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flash_unlock();
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flash_clear_err();
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MG_REG(MG_FLASH_BASE + MG_FLASH_CR) = MG_BIT(0) | MG_BIT(9); // PG, 32-bit
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flash_wait();
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MG_DEBUG(("Writing flash @ %p, %lu bytes", addr, len));
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while (ok && src < end) {
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if (flash_page_start(dst) && mg_stm32f_erase(dst) == false) break;
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*(volatile uint32_t *) dst++ = *src++;
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MG_DSB(); // ensure flash is written with no errors
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flash_wait();
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if (flash_is_err()) ok = false;
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}
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if (!s_flash_irq_disabled) MG_ARM_ENABLE_IRQ();
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MG_DEBUG(("Flash write %lu bytes @ %p: %s. CR %#lx SR %#lx", len, dst,
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ok ? "ok" : "fail", MG_REG(MG_FLASH_BASE + MG_FLASH_CR),
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MG_REG(MG_FLASH_BASE + MG_FLASH_SR)));
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MG_REG(MG_FLASH_BASE + MG_FLASH_CR) &= ~MG_BIT(0); // Clear programming flag
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return ok;
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}
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// just overwrite instead of swap
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MG_IRAM void single_bank_swap(char *p1, char *p2,
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size_t size) {
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// no stdlib calls here
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mg_stm32f_write(p1, p2, size);
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*(volatile unsigned long *) 0xe000ed0c = 0x5fa0004;
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}
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bool mg_ota_begin(size_t new_firmware_size) {
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s_mg_flash_stm32f.size = flash_size();
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return mg_ota_flash_begin(new_firmware_size, &s_mg_flash_stm32f);
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}
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bool mg_ota_write(const void *buf, size_t len) {
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return mg_ota_flash_write(buf, len, &s_mg_flash_stm32f);
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}
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bool mg_ota_end(void) {
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if (mg_ota_flash_end(&s_mg_flash_stm32f)) {
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// Swap partitions. Pray power does not go away
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MG_INFO(("Swapping partitions, size %u (%u sectors)",
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s_mg_flash_stm32f.size, STM_DEV_ID == 0x449 ? 8 : 12));
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MG_INFO(("Do NOT power off..."));
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mg_log_level = MG_LL_NONE;
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s_flash_irq_disabled = true;
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char *p1 = (char *) s_mg_flash_stm32f.start;
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char *p2 = p1 + s_mg_flash_stm32f.size / 2;
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size_t size = s_mg_flash_stm32f.size / 2;
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// Runs in RAM, will reset when finished
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single_bank_swap(p1, p2, size);
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}
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return false;
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}
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#endif |