mirror of
https://github.com/cesanta/mongoose.git
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258 lines
9.8 KiB
C
258 lines
9.8 KiB
C
// Copyright (c) 2022 Cesanta Software Limited
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// All rights reserved
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// https://www.ti.com/lit/pdf/spms433
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((bank << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) pinbank(pin >> 8)
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// This MCU doesn't have GPIOI nor GPIOO
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static inline unsigned int pinbank(unsigned int bank) {
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bank = bank > 'O' ? bank - 2 : bank > 'I' ? bank - 1 : bank;
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return bank - 'A';
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}
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// 5.5, Table 5-12: configure flash (and EEPROM) timing in accordance to clock
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// freq
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enum {
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PLL_CLK = 25,
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PLL_M = 96,
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PLL_N = 5,
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PLL_Q = 1,
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PSYSDIV = 4
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}; // Run at 120 Mhz
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#define PLL_FREQ (PLL_CLK * PLL_M / PLL_N / PLL_Q / PSYSDIV)
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#define FLASH_CLKHIGH 6
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#define FLASH_WAITST 5
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#define FREQ (PLL_FREQ * 1000000)
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static inline void spin(volatile uint32_t count) {
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while (count--) asm("nop");
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}
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struct systick {
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volatile uint32_t CTRL, LOAD, VAL, CALIB;
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};
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#define SYSTICK ((struct systick *) 0xe000e010)
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static inline void systick_init(uint32_t ticks) {
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if ((ticks - 1) > 0xffffff) return; // Systick timer is 24 bit
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SYSTICK->LOAD = ticks - 1;
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SYSTICK->VAL = 0;
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SYSTICK->CTRL = BIT(0) | BIT(1) | BIT(2); // Enable systick
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}
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struct nvic {
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volatile uint32_t ISER[8], RESERVED0[24], ICER[8], RSERVED1[24], ISPR[8],
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RESERVED2[24], ICPR[8], RESERVED3[24], IABR[8], RESERVED4[56], IP[240],
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RESERVED5[644], STIR;
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};
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#define NVIC ((struct nvic *) 0xe000e100)
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static inline void nvic_set_prio(int irq, uint32_t prio) {
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NVIC->IP[irq] = prio << 4;
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}
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static inline void nvic_enable_irq(int irq) {
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NVIC->ISER[irq >> 5] = (uint32_t) (1 << (irq & 31));
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}
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struct scb {
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volatile uint32_t CPUID, ICSR, VTOR, AIRCR, SCR, CCR, SHPR[3], SHCSR, CFSR,
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HFSR, DFSR, MMFAR, BFAR, AFSR, ID_PFR[2], ID_DFR, ID_AFR, ID_MFR[4],
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ID_ISAR[5], RESERVED0[1], CLIDR, CTR, CCSIDR, CSSELR, CPACR,
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RESERVED3[93], STIR, RESERVED4[15], MVFR0, MVFR1, MVFR2, RESERVED5[1],
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ICIALLU, RESERVED6[1], ICIMVAU, DCIMVAC, DCISW, DCCMVAU, DCCMVAC, DCCSW,
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DCCIMVAC, DCCISW, RESERVED7[6], ITCMCR, DTCMCR, AHBPCR, CACR, AHBSCR,
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RESERVED8[1], ABFSR;
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};
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#define SCB ((struct scb *) 0xe000ed00)
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struct sysctl {
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volatile uint32_t DONTCARE0[31], MOSCCTL, RESERVED0[12], RSCLKCFG,
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RESERVED1[3], MEMTIM0, DONTCARE1[39], PLLFREQ0, PLLFREQ1, PLLSTAT,
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DONTCARE2[241], SREPHY, DONTCARE3[26], SREMAC, DONTCARE4[26], RCGCGPIO,
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DONTCARE5[3], RCGCUART, DONTCARE6[5], RCGCEPHY, DONTCARE7[26], RCGCEMAC,
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DONTCARE8[228], PREPHY, DONTCARE9[26], PREMAC;
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};
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#define SYSCTL ((struct sysctl *) 0x400FE000)
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_HIGH };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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// 10.3, 10.6
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struct gpio {
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volatile uint32_t GPIODATA[256], GPIODIR, GPIOIS, GPIOIBE, GPIOIEV, GPIOIM,
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GPIORIS, GPIOMIS, GPIOICR, GPIOAFSEL, RESERVED1[55], GPIODR2R, GPIODR4R,
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GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, GPIODEN, GPIOLOCK, GPIOCR,
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GPIOAMSEL, GPIOPCTL, GPIOADCCTL, GPIODMACTL, GPIOSI, GPIODR12R,
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GPIOWAKEPEN, GPIOWAKELVL, GPIOWAKESTAT, RESERVED2[669], GPIOPP, GPIOPC,
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RESERVED3[2], GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, GPIOPeriphID7,
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GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, GPIOPeriphID3, GPIOPCellID0,
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GPIOPCellID1, GPIOPCellID2, GPIOPCellID3;
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};
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#define GPIO(N) ((struct gpio *) (0x40058000 + 0x1000 * (N)))
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static struct gpio *gpio_bank(uint16_t pin) {
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return GPIO(PINBANK(pin));
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}
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static inline void gpio_toggle(uint16_t pin) {
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struct gpio *gpio = gpio_bank(pin);
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uint8_t mask = BIT(PINNO(pin));
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gpio->GPIODATA[mask] ^= mask;
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}
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static inline int gpio_read(uint16_t pin) {
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return gpio_bank(pin)->GPIODATA[BIT(PINNO(pin))] ? 1 : 0;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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struct gpio *gpio = gpio_bank(pin);
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uint8_t mask = BIT(PINNO(pin));
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gpio->GPIODATA[mask] = val ? mask : 0;
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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struct gpio *gpio = gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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SYSCTL->RCGCGPIO |= BIT(PINBANK(pin)); // Enable GPIO clock
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if (mode == GPIO_MODE_ANALOG) {
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gpio->GPIOAMSEL |= BIT(PINNO(pin));
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return;
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}
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if (mode == GPIO_MODE_INPUT) {
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gpio->GPIODIR &= ~BIT(PINNO(pin));
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} else if (mode == GPIO_MODE_OUTPUT) {
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gpio->GPIODIR |= BIT(PINNO(pin));
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} else { // GPIO_MODE_AF
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SETBITS(gpio->GPIOPCTL, 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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gpio->GPIOAFSEL |= BIT(PINNO(pin));
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}
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gpio->GPIODEN |= BIT(PINNO(pin)); // Enable pin as digital function
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if (type == GPIO_OTYPE_OPEN_DRAIN)
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gpio->GPIOODR |= BIT(PINNO(pin));
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else // GPIO_OTYPE_PUSH_PULL
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gpio->GPIOODR &= ~BIT(PINNO(pin));
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if (speed == GPIO_SPEED_LOW)
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gpio->GPIOSLR |= BIT(PINNO(pin));
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else // GPIO_SPEED_HIGH
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gpio->GPIOSLR &= ~BIT(PINNO(pin));
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if (pull == GPIO_PULL_UP) {
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gpio->GPIOPUR |= BIT(PINNO(pin)); // setting one...
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} else if (pull == GPIO_PULL_DOWN) {
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gpio->GPIOPDR |= BIT(PINNO(pin)); // ...just clears the other
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} else {
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gpio->GPIOPUR &= ~BIT(PINNO(pin));
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gpio->GPIOPDR &= ~BIT(PINNO(pin));
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}
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_UP, 0); // EK does not have pull-up resistors
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_irq_attach(uint16_t pin) {
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uint8_t irqvecs[] = {16, 17, 18, 19, 20, 30, 31, 32,
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51, 52, 53, 72, 73, 76, 84};
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struct gpio *gpio = gpio_bank(pin);
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gpio->GPIOIS &= ~BIT(PINNO(pin)); // edge sensitive
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gpio->GPIOIBE |= BIT(PINNO(pin)); // both edges
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gpio->GPIOIM |= BIT(PINNO(pin)); // enable pin irq
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int irqvec = irqvecs[PINBANK(pin)]; // IRQ vector index, 2.5.2
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nvic_set_prio(irqvec, 3);
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nvic_enable_irq(irqvec);
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}
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struct uart {
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volatile uint32_t UARTDR, UARTRSR, RESERVED0[4], UARTFR, RESERVED1, UARTILPR,
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UARTIBRD, UARTFBRD, UARTLCRH, UARTCTL, UARTIFLS, UARTIM, UARTRIS, UARTMIS,
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UARTICR, UARTDMACTL, RESERVED2[22], UART9BITADDR, UART9BITAMASK,
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RESERVED3[965], UARTPP, RESERVED4, UARTCC, RESERVED5, UARTPeriphID4,
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UARTPeriphID5, UARTPeriphID6, UARTPeriphID7, UARTPeriphID0, UARTPeriphID1,
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UARTPeriphID2, UARTPeriphID3, UARTPCellID0, UARTPCellID1, UARTPCellID2,
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UARTPCellID3;
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};
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#define UARTECR UARTRSR
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#define USART_BASE 0x4000C000
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#define USART_OFFSET 0x1000
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#define USART(N) ((struct uart *) (USART_BASE + USART_OFFSET * (N)))
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#define UARTNO(u) ((uint8_t)(((unsigned int) (u) - USART_BASE) / USART_OFFSET))
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#define UART0 USART(0)
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static inline void uart_init(struct uart *uart, unsigned long baud) {
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struct uarthw {
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uint16_t rx, tx; // pins
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uint8_t af; // Alternate function
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};
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// af, rx, tx for UART0
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struct uarthw uarthw[1] = {{PIN('A', 0), PIN('A', 1), 1}};
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if (uart != UART0) return; // uarthw is not populated for other UARTs
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uint8_t uartno = UARTNO(uart);
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SYSCTL->RCGCUART |= BIT(uartno); // Enable peripheral clock
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gpio_init(uarthw[uartno].tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, 0, uarthw[uartno].af);
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gpio_init(uarthw[uartno].rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL,
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GPIO_SPEED_HIGH, 0, uarthw[uartno].af);
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// (16.3.2) ClkDiv = 16 (HSE=0)
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// BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
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// UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
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// must write in this order
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uart->UARTCTL = 0; // Disable this UART, clear HSE
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uart->UARTIBRD = FREQ / (16 * baud); // Baud rate, integer part
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uart->UARTFBRD =
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((FREQ % (16 * baud)) >> 26) & 0x3F; // Baud rate, fractional part
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uart->UARTLCRH = (3 << 5); // 8N1, no FIFOs;
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uart->UARTCTL |= BIT(0) | BIT(9) | BIT(8); // Set UARTEN, RXE, TXE
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}
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static inline void uart_write_byte(struct uart *uart, uint8_t byte) {
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uart->UARTDR = byte;
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while ((uart->UARTFR & BIT(7)) == 0) spin(1);
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}
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static inline void uart_write_buf(struct uart *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(struct uart *uart) {
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return uart->UARTFR & BIT(6); // If RXFF bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(struct uart *uart) {
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return (uint8_t) (uart->UARTDR & 0xFF);
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}
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static inline void clock_init(void) { // Set clock frequency
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
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asm("DSB");
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asm("ISB");
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SETBITS(SYSCTL->MOSCCTL, BIT(3) | BIT(2),
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BIT(4)); // Enable MOSC circuit (clear NOXTAL and PWRDN, set >10MHz
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// range)
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SETBITS(SYSCTL->MEMTIM0,
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BIT(21) | BIT(5) | 0x1F << 21 | 0xF << 16 | 0x1F << 5 | 0xF << 0,
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FLASH_CLKHIGH << 22 | FLASH_WAITST << 16 | FLASH_CLKHIGH << 5 |
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FLASH_WAITST << 0); // Configure flash timing (not yet applied)
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SETBITS(SYSCTL->RSCLKCFG, 0xF << 24 | (BIT(9) - 1),
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3 << 24); // Clear PLL divider, set MOSC as PLL source
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SYSCTL->PLLFREQ1 = (PLL_Q - 1) << 8 | (PLL_N - 1)
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<< 0; // Set PLL_Q and PLL_N
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SYSCTL->PLLFREQ0 =
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BIT(23) | PLL_M << 0; // Set PLL_Q, power up PLL (if it were on, we'd
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// need to set NEWFREQ in RSCLKCFG instead)
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while ((SYSCTL->PLLSTAT & BIT(0)) == 0) spin(1); // Wait for lock
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SYSCTL->RSCLKCFG |=
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BIT(31) | BIT(28) |
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(PSYSDIV - 1) << 0; // Update memory timing, use PLL, set clock divisor
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}
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