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https://github.com/cesanta/mongoose.git
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Use linux ephemeral range (start from 32768). More TCP debug
This commit is contained in:
cpq
parent
12f00d785d
commit
b6fc67fff2
277
mongoose.c
277
mongoose.c
@ -5934,6 +5934,268 @@ size_t mg_ws_wrap(struct mg_connection *c, size_t len, int op) {
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return c->send.len;
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}
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#ifdef MG_ENABLE_LINES
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#line 1 "src/tcpip/driver_nxpimxrt1020.c"
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#endif
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT1020)
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struct imx_rt1020_enet {
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volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3], ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR, RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2, RESERVED8, RXIC0, RXIC1, RXIC2, RESERVED9[3], IAUR, IALR, GAUR, GALR, RESERVED10[7], TFWR, RESERVED11[14], RDSR, TDSR, MRBR[2], RSFL, RSEM, RAEM, RAFL, TSEM, TAEM, TAFL, TIPG, FTRL, RESERVED12[3], TACC, RACC, RESERVED13[15], RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2048, RMON_T_GTE2048, RMON_T_OCTETS, IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, IEEE_T_FDXFC, IEEE_T_OCTETS_OK, RESERVED14[3], RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, RESERVED15, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, RMON_R_GTE2048, RMON_R_OCTETS, IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, IEEE_R_FDXFC, IEEE_R_OCTETS_OK, RESERVED16[71], ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP, RESERVED17[122], TGSR, TCSR0, TCCR0, TCSR1, TCCR1, TCSR2, TCCR2, TCSR3;
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};
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#undef ENET
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#define ENET ((struct imx_rt1020_enet *) (uintptr_t) 0x402D8000u)
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#undef BIT
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#define BIT(x) ((uint32_t) 1 << (x))
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#define ENET_RXBUFF_SIZE 1536 // 1522 Buffer must be 64bits aligned
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#define ENET_TXBUFF_SIZE 1536 // 1522 hence set to 0x600 (1536)
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#define ENET_RXBD_NUM (4)
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#define ENET_TXBD_NUM (4)
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const uint32_t EIMR_RX_ERR = 0x2400000; // Intr mask RXF+EBERR
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void ETH_IRQHandler(void);
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static bool mg_tcpip_driver_imxrt1020_init(struct mip_if *ifp);
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static void wait_phy_complete(void);
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static struct mip_if *s_ifp; // MIP interface
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static size_t mg_tcpip_driver_imxrt1020_tx(const void *, size_t , struct mip_if *);
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static bool mg_tcpip_driver_imxrt1020_up(struct mip_if *ifp);
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enum { PHY_ADDR = 0x02, PHY_BCR = 0, PHY_BSR = 1 }; // PHY constants
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void delay(uint32_t);
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void delay (uint32_t di) {
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volatile int dno = 0; // Prevent optimization
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for (uint32_t i = 0; i < di; i++)
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for (int j=0; j<20; j++) // PLLx20 (500 MHz/24MHz)
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dno++;
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}
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static void wait_phy_complete(void) {
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delay(0x00010000);
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const uint32_t delay_max = 0x00100000;
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uint32_t delay_cnt = 0;
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while (!(ENET->EIR & BIT(23)) && (delay_cnt < delay_max))
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{delay_cnt++;}
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ENET->EIR |= BIT(23); // MII interrupt clear
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}
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static uint32_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ENET->EIR |= BIT(23); // MII interrupt clear
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uint32_t mask_phy_adr_reg = 0x1f; // 0b00011111: Ensure we write 5 bits (Phy address & register)
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uint32_t phy_transaction = 0x00;
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phy_transaction = (0x1 << 30) \
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| (0x2 << 28) \
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| ((uint32_t)(addr & mask_phy_adr_reg) << 23) \
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| ((uint32_t)(reg & mask_phy_adr_reg) << 18) \
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| (0x2 << 16);
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ENET->MMFR = phy_transaction;
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wait_phy_complete();
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return (ENET->MMFR & 0x0000ffff);
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}
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static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
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ENET->EIR |= BIT(23); // MII interrupt clear
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uint8_t mask_phy_adr_reg = 0x1f; // 0b00011111: Ensure we write 5 bits (Phy address & register)
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uint32_t mask_phy_data = 0x0000ffff; // Ensure we write 16 bits (data)
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addr &= mask_phy_adr_reg;
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reg &= mask_phy_adr_reg;
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val &= mask_phy_data;
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uint32_t phy_transaction = 0x00;
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phy_transaction = (uint32_t)(0x1 << 30) \
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| (uint32_t)(0x1 << 28) \
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| (uint32_t)(addr << 23) \
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| (uint32_t)(reg << 18) \
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| (uint32_t)(0x2 << 16) \
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| (uint32_t)(val);
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ENET->MMFR = phy_transaction;
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wait_phy_complete();
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}
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// FEC RX/TX descriptors (Enhanced descriptor not enabled)
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// Descriptor buffer structure, little endian
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typedef struct enet_bd_struct_def
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{
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uint16_t length; // Data length
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uint16_t control; // Control and status
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uint32_t *buffer; // Data ptr
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} enet_bd_struct_t;
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// Descriptor and buffer globals, in non-cached area, 64 bits aligned.
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__attribute__((section("NonCacheable,\"aw\",%nobits @"))) enet_bd_struct_t rx_buffer_descriptor[(ENET_RXBD_NUM)] __attribute__((aligned((64U))));
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__attribute__((section("NonCacheable,\"aw\",%nobits @"))) enet_bd_struct_t tx_buffer_descriptor[(ENET_TXBD_NUM)] __attribute__((aligned((64U))));
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uint8_t rx_data_buffer[(ENET_RXBD_NUM)][((unsigned int)(((ENET_RXBUFF_SIZE)) + (((64U))-1U)) & (unsigned int)(~(unsigned int)(((64U))-1U)))] __attribute__((aligned((64U))));
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uint8_t tx_data_buffer[(ENET_TXBD_NUM)][((unsigned int)(((ENET_TXBUFF_SIZE)) + (((64U))-1U)) & (unsigned int)(~(unsigned int)(((64U))-1U)))] __attribute__((aligned((64U))));
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// Initialise driver imx_rt1020
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// static bool mg_tcpip_driver_imxrt1020_init(uint8_t *mac, void *data) { // VO
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static bool mg_tcpip_driver_imxrt1020_init(struct mip_if *ifp) {
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struct mg_tcpip_driver_imxrt1020_data *d = (struct mg_tcpip_driver_imxrt1020_data *) ifp->driver_data;
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s_ifp = ifp;
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// ENET Reset, wait complete
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ENET->ECR |= BIT(0);
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while((ENET->ECR & BIT(0)) != 0) {}
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// Re-latches the pin strapping pin values
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ENET->ECR |= BIT(0);
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while((ENET->ECR & BIT(0)) != 0) {}
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// Setup MII/RMII MDC clock divider (<= 2.5MHz).
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ENET->MSCR = 0x130; // HOLDTIME 2 clk, Preamble enable, MDC MII_Speed Div 0x30
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eth_write_phy(PHY_ADDR, PHY_BCR, 0x8000); // PHY W @0x00 D=0x8000 Soft reset
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while (eth_read_phy(PHY_ADDR, PHY_BSR) & BIT(15)) {delay(0x5000);} // Wait finished poll 10ms
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// PHY: Start Link
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{
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eth_write_phy(PHY_ADDR, PHY_BCR, 0x1200); // PHY W @0x00 D=0x1200 Autonego enable + start
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eth_write_phy(PHY_ADDR, 0x1f, 0x8180); // PHY W @0x1f D=0x8180 Ref clock 50 MHz at XI input
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uint32_t bcr = eth_read_phy(PHY_ADDR, PHY_BCR);
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bcr &= ~BIT(10); // Isolation -> Normal
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eth_write_phy(PHY_ADDR, PHY_BCR, bcr);
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}
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// Disable ENET
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ENET->ECR = 0x0; // Disable before configuration
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// Configure ENET
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ENET->RCR = 0x05ee0104; // #CRCFWD=0 (CRC kept in frame) + RMII + MII Enable
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ENET->TCR = BIT(8) | BIT(2); // Addins (MAC address from PAUR+PALR) + Full duplex enable
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//ENET->TFWR = BIT(8); // Store And Forward Enable, 64 bytes (minimize tx latency)
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// Configure descriptors and buffers
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// RX
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for (int i = 0; i < ENET_RXBD_NUM; i++) {
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// Wrap last descriptor buffer ptr
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rx_buffer_descriptor[i].control = (BIT(15) | ((i<(ENET_RXBD_NUM-1))?0:BIT(13))); // E+(W*)
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rx_buffer_descriptor[i].buffer = (uint32_t *)rx_data_buffer[i];
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}
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// TX
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for (int i = 0; i < ENET_TXBD_NUM; i++) {
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// Wrap last descriptor buffer ptr
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tx_buffer_descriptor[i].control = ((i<(ENET_RXBD_NUM-1))?0:BIT(13)) | BIT(10); // (W*)+TC
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tx_buffer_descriptor[i].buffer = (uint32_t *)tx_data_buffer[i];
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}
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// Continue ENET configuration
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ENET->RDSR = (uint32_t)(uintptr_t)rx_buffer_descriptor;
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ENET->TDSR = (uint32_t)(uintptr_t)tx_buffer_descriptor;
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ENET->MRBR[0] = ENET_RXBUFF_SIZE; // Same size for RX/TX buffers
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// MAC address filtering (bytes in reversed order)
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ENET->PAUR = ((uint32_t) ifp->mac[4] << 24U) | (uint32_t) ifp->mac[5] << 16U;
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ENET->PALR = (uint32_t) (ifp->mac[0] << 24U) | ((uint32_t) ifp->mac[1] << 16U) |
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((uint32_t) ifp->mac[2] << 8U) | ifp->mac[3];
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// Init Hash tables (mac filtering)
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ENET->IAUR = 0; // Unicast
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ENET->IALR = 0;
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ENET->GAUR = 0; // Multicast
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ENET->GALR = 0;
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// Set ENET Online
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ENET->ECR |= BIT(8); // ENET Set Little-endian + (FEC buffer desc.)
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ENET->ECR |= BIT(1); // Enable
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// Set interrupt mask
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ENET->EIMR = EIMR_RX_ERR;
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// RX Descriptor activation
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ENET->RDAR = BIT(24); // Activate Receive Descriptor
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if (ifp->queue.len == 0) ifp->queue.len = 8192;
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return true;
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}
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// Transmit frame
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static uint32_t s_txno;
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static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len, struct mip_if *ifp) {
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if (len > sizeof(tx_data_buffer[ENET_TXBD_NUM])) {
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// MG_ERROR(("Frame too big, %ld", (long) len));
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len = 0; // Frame is too big
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} else if ((tx_buffer_descriptor[s_txno].control & BIT(15))) {
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MG_ERROR(("No free descriptors"));
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// printf("D0 %lx SR %lx\n", (long) s_txdesc[0][0], (long) ETH->DMASR);
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len = 0; // All descriptors are busy, fail
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} else {
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memcpy(tx_data_buffer[s_txno], buf, len); // Copy data
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tx_buffer_descriptor[s_txno].length = (uint16_t) len; // Set data len
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tx_buffer_descriptor[s_txno].control |= (uint16_t)(BIT(10)); // TC (transmit CRC)
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// tx_buffer_descriptor[s_txno].control &= (uint16_t)(BIT(14) | BIT(12)); // Own doesn't affect HW
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tx_buffer_descriptor[s_txno].control |= (uint16_t)(BIT(15) | BIT(11)); // R+L (ready+last)
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ENET->TDAR = BIT(24); // Descriptor updated. Hand over to DMA.
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// INFO
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// Relevant Descriptor bits: 15(R) Ready
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// 11(L) last in frame
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// 10(TC) transmis CRC
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// __DSB(); // ARM errata 838869 Cortex-M4, M4F, M7, M7F: "store immediate overlapping
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// exception" return might vector to incorrect interrupt.
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if (++s_txno >= ENET_TXBD_NUM) s_txno = 0;
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}
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(void) ifp;
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return len;
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}
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// IRQ (RX)
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static uint32_t s_rxno;
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void ENET_IRQHandler(void) {
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ENET->EIMR = 0; // Mask interrupts.
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uint32_t eir = ENET->EIR; // Read EIR
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ENET->EIR = 0xffffffff; // Clear interrupts
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qp_mark(QP_IRQTRIGGERED, 0);
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if (eir & EIMR_RX_ERR) // Global mask used
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{
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if (rx_buffer_descriptor[s_rxno].control & BIT(15)) {
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ENET->EIMR = EIMR_RX_ERR; // Enable interrupts
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return; // Empty? -> exit.
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}
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// Read inframes
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else { // Frame received, loop
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for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever
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if (rx_buffer_descriptor[s_rxno].control & BIT(15)) break; // exit when done
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uint32_t len = (rx_buffer_descriptor[s_rxno].length);
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mg_tcpip_qwrite(rx_buffer_descriptor[s_rxno].buffer, len > 4 ? len - 4 : len, s_ifp);
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rx_buffer_descriptor[s_rxno].control |= BIT(15); // Inform DMA RX is empty
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if (++s_rxno >= ENET_RXBD_NUM) s_rxno = 0;
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}
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}
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}
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ENET->EIMR = EIMR_RX_ERR; // Enable interrupts
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}
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// Up/down status
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static bool mg_tcpip_driver_imxrt1020_up(struct mip_if *ifp) {
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uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
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(void) ifp;
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return bsr & BIT(2) ? 1 : 0;
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}
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// API
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struct mg_tcpip_driver mg_tcpip_driver_imxrt1020 = {
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mg_tcpip_driver_imxrt1020_init, mg_tcpip_driver_imxrt1020_tx, mip_driver_rx,
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mg_tcpip_driver_imxrt1020_up};
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#endif
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#ifdef MG_ENABLE_LINES
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#line 1 "src/tcpip/driver_stm32.c"
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#endif
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@ -6791,7 +7053,7 @@ struct mg_tcpip_driver mg_tcpip_driver_w5500 = {w5500_init, w5500_tx, w5500_rx,
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#if MG_ENABLE_TCPIP
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#define MIP_EPHEMERAL_PORT 49152
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#define MG_EPHEMERAL_PORT_BASE 32768
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#define PDIFF(a, b) ((size_t) (((char *) (b)) - ((char *) (a))))
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#ifndef MIP_TCP_KEEPALIVE_MS
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@ -7272,6 +7534,9 @@ static size_t tx_tcp(struct mg_tcpip_if *ifp, uint8_t *dst_mac, uint32_t dst_ip,
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cs = csumup(cs, &ip->dst, sizeof(ip->dst));
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cs = csumup(cs, pseudo, sizeof(pseudo));
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tcp->csum = csumfin(cs);
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MG_DEBUG(("TCP %M:%hu -> %M:%hu fl %x len %u", mg_print_ip4, &ip->src,
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mg_ntohs(tcp->sport), mg_print_ip4, &ip->dst, mg_ntohs(tcp->dport),
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tcp->flags, (int) len));
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return ether_output(ifp, PDIFF(ifp->tx.ptr, tcp + 1) + len);
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}
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@ -7642,12 +7907,8 @@ void mg_tcpip_init(struct mg_mgr *mgr, struct mg_tcpip_if *ifp) {
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mgr->extraconnsize = sizeof(struct connstate);
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if (ifp->ip == 0) ifp->enable_dhcp_client = true;
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memset(ifp->gwmac, 255, sizeof(ifp->gwmac)); // Set to broadcast
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// Randomise initial ephemeral port
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uint16_t jitter;
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mg_random(&jitter, sizeof(jitter));
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ifp->eport = MIP_EPHEMERAL_PORT +
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(uint16_t) (jitter % (0xffffu - MIP_EPHEMERAL_PORT));
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mg_random(&ifp->eport, sizeof(ifp->eport)); // Randomise the initial
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ifp->eport += MG_EPHEMERAL_PORT_BASE; // ephemeral port
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}
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}
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@ -7673,7 +7934,7 @@ static void send_syn(struct mg_connection *c) {
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void mg_connect_resolved(struct mg_connection *c) {
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struct mg_tcpip_if *ifp = (struct mg_tcpip_if *) c->mgr->priv;
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c->is_resolving = 0;
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if (ifp->eport < MIP_EPHEMERAL_PORT) ifp->eport = MIP_EPHEMERAL_PORT;
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if (ifp->eport < MG_EPHEMERAL_PORT_BASE) ifp->eport = MG_EPHEMERAL_PORT_BASE;
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c->loc.ip = ifp->ip;
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c->loc.port = mg_htons(ifp->eport++);
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MG_DEBUG(("%lu %M -> %M", c->id, mg_print_ip_port, &c->loc, mg_print_ip_port,
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16
mongoose.h
16
mongoose.h
@ -1511,6 +1511,7 @@ extern struct mg_tcpip_driver mg_tcpip_driver_stm32;
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extern struct mg_tcpip_driver mg_tcpip_driver_w5500;
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extern struct mg_tcpip_driver mg_tcpip_driver_tm4c;
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extern struct mg_tcpip_driver mg_tcpip_driver_stm32h;
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extern struct mg_tcpip_driver mg_tcpip_driver_imxrt1020;
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// Drivers that require SPI, can use this SPI abstraction
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struct mg_tcpip_spi {
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@ -1529,6 +1530,21 @@ struct mg_tcpip_spi {
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#endif
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struct mg_tcpip_driver_imxrt1020_data {
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// MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk),
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// must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz
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// ipg_clk MSCR mdc_cr VALUE
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// -------------------------------------
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// -1 <-- tell driver to guess the value
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// 25 MHz 0x04 0
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// 33 MHz 0x06 1
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// 40 MHz 0x07 2
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||||
// 50 MHz 0x09 3
|
||||
// 66 MHz 0x0D 4 <-- value for iMXRT1020-EVK at max freq.
|
||||
int mdc_cr; // Valid values: -1, 0, 1, 2, 3, 4
|
||||
};
|
||||
|
||||
|
||||
struct mg_tcpip_driver_stm32_data {
|
||||
// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz
|
||||
// HCLK range DIVIDER mdc_cr VALUE
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
|
||||
#if MG_ENABLE_TCPIP
|
||||
|
||||
#define MIP_EPHEMERAL_PORT 49152
|
||||
#define MG_EPHEMERAL_PORT_BASE 32768
|
||||
#define PDIFF(a, b) ((size_t) (((char *) (b)) - ((char *) (a))))
|
||||
|
||||
#ifndef MIP_TCP_KEEPALIVE_MS
|
||||
@ -483,6 +483,9 @@ static size_t tx_tcp(struct mg_tcpip_if *ifp, uint8_t *dst_mac, uint32_t dst_ip,
|
||||
cs = csumup(cs, &ip->dst, sizeof(ip->dst));
|
||||
cs = csumup(cs, pseudo, sizeof(pseudo));
|
||||
tcp->csum = csumfin(cs);
|
||||
MG_DEBUG(("TCP %M:%hu -> %M:%hu fl %x len %u", mg_print_ip4, &ip->src,
|
||||
mg_ntohs(tcp->sport), mg_print_ip4, &ip->dst, mg_ntohs(tcp->dport),
|
||||
tcp->flags, (int) len));
|
||||
return ether_output(ifp, PDIFF(ifp->tx.ptr, tcp + 1) + len);
|
||||
}
|
||||
|
||||
@ -853,12 +856,8 @@ void mg_tcpip_init(struct mg_mgr *mgr, struct mg_tcpip_if *ifp) {
|
||||
mgr->extraconnsize = sizeof(struct connstate);
|
||||
if (ifp->ip == 0) ifp->enable_dhcp_client = true;
|
||||
memset(ifp->gwmac, 255, sizeof(ifp->gwmac)); // Set to broadcast
|
||||
|
||||
// Randomise initial ephemeral port
|
||||
uint16_t jitter;
|
||||
mg_random(&jitter, sizeof(jitter));
|
||||
ifp->eport = MIP_EPHEMERAL_PORT +
|
||||
(uint16_t) (jitter % (0xffffu - MIP_EPHEMERAL_PORT));
|
||||
mg_random(&ifp->eport, sizeof(ifp->eport)); // Randomise the initial
|
||||
ifp->eport += MG_EPHEMERAL_PORT_BASE; // ephemeral port
|
||||
}
|
||||
}
|
||||
|
||||
@ -884,7 +883,7 @@ static void send_syn(struct mg_connection *c) {
|
||||
void mg_connect_resolved(struct mg_connection *c) {
|
||||
struct mg_tcpip_if *ifp = (struct mg_tcpip_if *) c->mgr->priv;
|
||||
c->is_resolving = 0;
|
||||
if (ifp->eport < MIP_EPHEMERAL_PORT) ifp->eport = MIP_EPHEMERAL_PORT;
|
||||
if (ifp->eport < MG_EPHEMERAL_PORT_BASE) ifp->eport = MG_EPHEMERAL_PORT_BASE;
|
||||
c->loc.ip = ifp->ip;
|
||||
c->loc.port = mg_htons(ifp->eport++);
|
||||
MG_DEBUG(("%lu %M -> %M", c->id, mg_print_ip_port, &c->loc, mg_print_ip_port,
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user