mirror of
https://github.com/cesanta/mongoose.git
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Nit picks
This commit is contained in:
cpq
parent
d1b0342a18
commit
b379f81004
@ -22,14 +22,17 @@ uint64_t mg_millis(void) { // Let Mongoose use our uptime function
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return millis();
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}
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static void fn(struct mg_connection *c, int ev, void *ev_data, void *fn_data) {
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// Simple HTTP server that prints "x" characters followed by newline.
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// 100 characters is a default. Example curl request to print 2000 characters:
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// curl IP:8000 -d '{"n":2000}'
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static void simple_http_listener(struct mg_connection *c, int ev, void *ev_data,
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void *fn_data) {
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if (ev == MG_EV_HTTP_MSG) {
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struct mg_http_message *hm = (struct mg_http_message *) ev_data;
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long n = mg_json_get_long(hm->body, "$.n", 100);
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mg_xprintf(mg_pfn_iobuf, &c->send,
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"HTTP/1.1 200 OK\r\nContent-Length: %ld\r\n\r\n", n + 1);
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for (long i = 0; i < n; i++) mg_iobuf_add(&c->send, c->send.len, "x", 1);
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mg_iobuf_add(&c->send, c->send.len, "\n", 1);
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mg_printf(c, "HTTP/1.1 200 OK\r\nContent-Length: %ld\r\n\r\n", n + 1);
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for (long i = 0; i < n; i++) mg_printf(c, "x");
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mg_printf(c, "\n");
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c->is_resp = 0;
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}
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}
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@ -50,10 +53,13 @@ void setup() {
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MG_INFO(("Waiting for IP..."));
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while (mif.state != MG_TCPIP_STATE_READY) mg_mgr_poll(&mgr, 1);
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// We start two HTTP listeners: one is a simple one on port 8000,
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// with event handler function defined above - simple_http_listener
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// See https://mongoose.ws/documentation/#2-minute-integration-guide
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// Another listener is for a more sophisticated Web device dashboard
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MG_INFO(("Starting web dashboard"));
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web_init(&mgr);
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mg_http_listen(&mgr, "http://0.0.0.0:8000", fn, NULL);
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mg_http_listen(&mgr, "http://0.0.0.0:8000", simple_http_listener, NULL);
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web_init(&mgr); // Sophisticated Web UI, see net.c :: fn()
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}
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void loop() {
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@ -65,10 +71,7 @@ void loop() {
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mg_mgr_poll(&mgr, 1); // Process network events
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}
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extern "C" {
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extern void (*volatile _VectorsRam[176])(void);
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extern void ENET_IRQHandler(void);
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};
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extern "C" void ENET_IRQHandler(void);
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define RMII_PAD_INPUT_PULLDOWN 0x30E9
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@ -132,6 +135,6 @@ void ethernet_init(void) {
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delay(1);
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// Setup IRQ handler
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_VectorsRam[16 + IRQ_ENET] = ENET_IRQHandler;
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attachInterruptVector(IRQ_ENET, ENET_IRQHandler);
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NVIC_ENABLE_IRQ(IRQ_ENET);
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}
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@ -18,7 +18,7 @@ micropython:
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$(DOCKER) git clone https://github.com/micropython/micropython.git
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clean:
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$(DOCKER) rm -rf micropython
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test -d micropython && $(DOCKER) rm -rf micropython || true
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flash:
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flash: DA = --device $(PORT)
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49
mongoose.c
49
mongoose.c
@ -8677,21 +8677,21 @@ struct rt1020_enet {
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#define ETH_PKT_SIZE 1536 // Max frame size, 64-bit aligned
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#define ETH_DESC_CNT 4 // Descriptors count
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typedef struct {
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struct rt10xx_desc {
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uint16_t length; // Data length
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uint16_t control; // Control and status
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uint32_t *buffer; // Data ptr
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} enet_bd_t;
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};
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// TODO(): handle these in a portable compiler-independent CMSIS-friendly way
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#define MG_A64 __attribute__((aligned((64U))))
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#define MG_64BIT_ALIGNED __attribute__((aligned((64U))))
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// Descriptors: in non-cached area (TODO(scaprile)), 64-bit aligned
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// Buffers: 64-bit aligned
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static volatile enet_bd_t s_rxdesc[ETH_DESC_CNT] MG_A64;
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static volatile enet_bd_t s_txdesc[ETH_DESC_CNT] MG_A64;
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_A64;
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_A64;
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static volatile struct rt10xx_desc s_rxdesc[ETH_DESC_CNT] MG_64BIT_ALIGNED;
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static volatile struct rt10xx_desc s_txdesc[ETH_DESC_CNT] MG_64BIT_ALIGNED;
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_64BIT_ALIGNED;
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_64BIT_ALIGNED;
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static struct mg_tcpip_if *s_ifp; // MIP interface
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enum { PHY_BCR = 0, PHY_BSR = 1, PHY_ID1 = 2, PHY_ID2 = 3 };
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@ -8727,7 +8727,7 @@ static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
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// Init TX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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//s_txdesc[i].control = MG_BIT(10); // Own (TC)
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// s_txdesc[i].control = MG_BIT(10); // Own (TC)
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s_txdesc[i].buffer = (uint32_t *) s_txbuf[i];
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}
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s_txdesc[ETH_DESC_CNT - 1].control |= MG_BIT(13); // Wrap last descriptor
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@ -8744,17 +8744,17 @@ static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
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rt10xx_phy_write(d->phy_addr, PHY_BCR, MG_BIT(12)); // Set autonegotiation
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// PHY: Enable 50 MHz external ref clock at XI (preserve defaults)
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uint16_t phy_id2 = rt10xx_phy_read(d->phy_addr, PHY_ID1);
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uint16_t phy_id3 = rt10xx_phy_read(d->phy_addr, PHY_ID2);
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MG_INFO(("PHY ID: %#04x %#04x", phy_id2, phy_id3));
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uint16_t phy_id1 = rt10xx_phy_read(d->phy_addr, PHY_ID1);
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uint16_t phy_id2 = rt10xx_phy_read(d->phy_addr, PHY_ID2);
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MG_INFO(("PHY ID: %#04x %#04x", phy_id1, phy_id2));
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// 2000 a140 - TI DP83825I
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// 0007 c0fx - LAN8720
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// 0022 1561 - KSZ8081RNB
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if (phy_id2 == 0x22) { // KSZ8081RNB, like EVK-RTxxxx boards
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if (phy_id1 == 0x22) { // KSZ8081RNB, like EVK-RTxxxx boards
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rt10xx_phy_write(d->phy_addr, 31,
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MG_BIT(15) | MG_BIT(8) | MG_BIT(7)); // PC2R
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} else if (phy_id2 == 0x2000) { // DP83825I, like Teensy4.1
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} else if (phy_id1 == 0x2000) { // DP83825I, like Teensy4.1
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rt10xx_phy_write(d->phy_addr, 23, 0x81); // 50Mhz clock input
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rt10xx_phy_write(d->phy_addr, 24, 0x280); // LED status, active high
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} else { // Default to LAN8720
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@ -8776,14 +8776,15 @@ static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
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ENET->ECR = MG_BIT(8) | MG_BIT(1); // Little-endian CPU, Enable
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ENET->EIMR = MG_BIT(25); // Set interrupt mask
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ENET->RDAR = MG_BIT(24); // Receive Descriptors have changed
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ENET->TDAR = MG_BIT(24); // Transmit Descriptors have changed
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// ENET->OPD = 0x10014;
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return true;
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}
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// Transmit frame
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static uint32_t s_txno;
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static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len,
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struct mg_tcpip_if *ifp) {
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static int s_txno; // Current descriptor index
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if (len > sizeof(s_txbuf[ETH_DESC_CNT])) {
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ifp->nerr++;
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MG_ERROR(("Frame too big, %ld", (long) len));
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@ -8792,14 +8793,18 @@ static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len,
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MG_ERROR(("No descriptors available"));
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len = 0; // retry later
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} else {
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MG_DEBUG(("sending %lu bytes, desc %u", len, s_txno));
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MG_DEBUG(("sending %4lu, d=%u, c=%#hx %#lx %#lx", len, s_txno,
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s_txdesc[s_txno].control, ENET->EIR, ENET->ATSTMP));
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno].length = (uint16_t) len; // Set data len
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// Table 37-34, R, L, TC (Ready, last, transmit CRC after frame
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s_txdesc[s_txno].control |=
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(uint16_t) (MG_BIT(15) | MG_BIT(11) | MG_BIT(10));
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ENET->TDAR |= MG_BIT(24); // Descriptor ring updated
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ENET->TDAR = MG_BIT(24); // Descriptor ring updated
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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// Artificial delay. TODO(cpq): find a proper way to transmit reliably
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for (volatile int i = 0; i < 99999; i++) (void) 0;
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}
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(void) ifp;
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return len;
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@ -8832,12 +8837,12 @@ void ENET_IRQHandler(void) {
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ENET->EIR = MG_BIT(25); // Ack IRQ
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// Frame received, loop
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for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever
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if (s_rxdesc[s_rxno].control & MG_BIT(15)) break; // exit when done
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uint32_t r = s_rxdesc[s_rxno].control;
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if (r & MG_BIT(15)) break; // exit when done
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// skip partial/errored frames (Table 37-32)
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if ((s_rxdesc[s_rxno].control & MG_BIT(11)) &&
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!(s_rxdesc[s_rxno].control &
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(MG_BIT(5) | MG_BIT(4) | MG_BIT(2) | MG_BIT(1) | MG_BIT(0)))) {
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uint32_t len = (s_rxdesc[s_rxno].length);
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if ((r & MG_BIT(11)) &&
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!(r & (MG_BIT(5) | MG_BIT(4) | MG_BIT(2) | MG_BIT(1) | MG_BIT(0)))) {
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size_t len = s_rxdesc[s_rxno].length;
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mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
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}
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s_rxdesc[s_rxno].control |= MG_BIT(15);
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@ -32,21 +32,21 @@ struct rt1020_enet {
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#define ETH_PKT_SIZE 1536 // Max frame size, 64-bit aligned
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#define ETH_DESC_CNT 4 // Descriptors count
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typedef struct {
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struct rt10xx_desc {
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uint16_t length; // Data length
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uint16_t control; // Control and status
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uint32_t *buffer; // Data ptr
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} enet_bd_t;
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};
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// TODO(): handle these in a portable compiler-independent CMSIS-friendly way
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#define MG_A64 __attribute__((aligned((64U))))
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#define MG_64BIT_ALIGNED __attribute__((aligned((64U))))
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// Descriptors: in non-cached area (TODO(scaprile)), 64-bit aligned
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// Buffers: 64-bit aligned
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static volatile enet_bd_t s_rxdesc[ETH_DESC_CNT] MG_A64;
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static volatile enet_bd_t s_txdesc[ETH_DESC_CNT] MG_A64;
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_A64;
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_A64;
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static volatile struct rt10xx_desc s_rxdesc[ETH_DESC_CNT] MG_64BIT_ALIGNED;
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static volatile struct rt10xx_desc s_txdesc[ETH_DESC_CNT] MG_64BIT_ALIGNED;
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_64BIT_ALIGNED;
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_64BIT_ALIGNED;
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static struct mg_tcpip_if *s_ifp; // MIP interface
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enum { PHY_BCR = 0, PHY_BSR = 1, PHY_ID1 = 2, PHY_ID2 = 3 };
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@ -82,7 +82,7 @@ static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
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// Init TX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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//s_txdesc[i].control = MG_BIT(10); // Own (TC)
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// s_txdesc[i].control = MG_BIT(10); // Own (TC)
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s_txdesc[i].buffer = (uint32_t *) s_txbuf[i];
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}
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s_txdesc[ETH_DESC_CNT - 1].control |= MG_BIT(13); // Wrap last descriptor
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@ -99,17 +99,17 @@ static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
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rt10xx_phy_write(d->phy_addr, PHY_BCR, MG_BIT(12)); // Set autonegotiation
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// PHY: Enable 50 MHz external ref clock at XI (preserve defaults)
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uint16_t phy_id2 = rt10xx_phy_read(d->phy_addr, PHY_ID1);
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uint16_t phy_id3 = rt10xx_phy_read(d->phy_addr, PHY_ID2);
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MG_INFO(("PHY ID: %#04x %#04x", phy_id2, phy_id3));
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uint16_t phy_id1 = rt10xx_phy_read(d->phy_addr, PHY_ID1);
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uint16_t phy_id2 = rt10xx_phy_read(d->phy_addr, PHY_ID2);
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MG_INFO(("PHY ID: %#04x %#04x", phy_id1, phy_id2));
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// 2000 a140 - TI DP83825I
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// 0007 c0fx - LAN8720
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// 0022 1561 - KSZ8081RNB
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if (phy_id2 == 0x22) { // KSZ8081RNB, like EVK-RTxxxx boards
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if (phy_id1 == 0x22) { // KSZ8081RNB, like EVK-RTxxxx boards
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rt10xx_phy_write(d->phy_addr, 31,
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MG_BIT(15) | MG_BIT(8) | MG_BIT(7)); // PC2R
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} else if (phy_id2 == 0x2000) { // DP83825I, like Teensy4.1
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} else if (phy_id1 == 0x2000) { // DP83825I, like Teensy4.1
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rt10xx_phy_write(d->phy_addr, 23, 0x81); // 50Mhz clock input
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rt10xx_phy_write(d->phy_addr, 24, 0x280); // LED status, active high
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} else { // Default to LAN8720
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@ -131,14 +131,15 @@ static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
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ENET->ECR = MG_BIT(8) | MG_BIT(1); // Little-endian CPU, Enable
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ENET->EIMR = MG_BIT(25); // Set interrupt mask
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ENET->RDAR = MG_BIT(24); // Receive Descriptors have changed
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ENET->TDAR = MG_BIT(24); // Transmit Descriptors have changed
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// ENET->OPD = 0x10014;
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return true;
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}
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// Transmit frame
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static uint32_t s_txno;
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static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len,
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struct mg_tcpip_if *ifp) {
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static int s_txno; // Current descriptor index
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if (len > sizeof(s_txbuf[ETH_DESC_CNT])) {
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ifp->nerr++;
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MG_ERROR(("Frame too big, %ld", (long) len));
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@ -147,14 +148,18 @@ static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len,
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MG_ERROR(("No descriptors available"));
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len = 0; // retry later
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} else {
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MG_DEBUG(("sending %lu bytes, desc %u", len, s_txno));
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MG_DEBUG(("sending %4lu, d=%u, c=%#hx %#lx %#lx", len, s_txno,
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s_txdesc[s_txno].control, ENET->EIR, ENET->ATSTMP));
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno].length = (uint16_t) len; // Set data len
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// Table 37-34, R, L, TC (Ready, last, transmit CRC after frame
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s_txdesc[s_txno].control |=
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(uint16_t) (MG_BIT(15) | MG_BIT(11) | MG_BIT(10));
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ENET->TDAR |= MG_BIT(24); // Descriptor ring updated
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ENET->TDAR = MG_BIT(24); // Descriptor ring updated
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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// Artificial delay. TODO(cpq): find a proper way to transmit reliably
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for (volatile int i = 0; i < 99999; i++) (void) 0;
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}
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(void) ifp;
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return len;
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@ -187,12 +192,12 @@ void ENET_IRQHandler(void) {
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ENET->EIR = MG_BIT(25); // Ack IRQ
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// Frame received, loop
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for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever
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if (s_rxdesc[s_rxno].control & MG_BIT(15)) break; // exit when done
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uint32_t r = s_rxdesc[s_rxno].control;
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if (r & MG_BIT(15)) break; // exit when done
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// skip partial/errored frames (Table 37-32)
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if ((s_rxdesc[s_rxno].control & MG_BIT(11)) &&
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!(s_rxdesc[s_rxno].control &
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(MG_BIT(5) | MG_BIT(4) | MG_BIT(2) | MG_BIT(1) | MG_BIT(0)))) {
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uint32_t len = (s_rxdesc[s_rxno].length);
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if ((r & MG_BIT(11)) &&
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!(r & (MG_BIT(5) | MG_BIT(4) | MG_BIT(2) | MG_BIT(1) | MG_BIT(0)))) {
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size_t len = s_rxdesc[s_rxno].length;
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mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
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}
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s_rxdesc[s_rxno].control |= MG_BIT(15);
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