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Merge pull request #2767 from cesanta/frdm-n94

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FRDM-MCXN947
This commit is contained in:
Sergey Lyubka 2024-05-28 21:39:51 +01:00 committed by GitHub
commit 9ec2022447
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45
examples/nxp/frdm-mcxn947-make-baremetal-builtin/Makefile Normal file
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CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
CFLAGS += -Wformat-truncation -fno-common # -Wconversion is not SDK-friendly
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MCXN947/
CFLAGS += -Icmsis_mcu/devices/MCXN947/drivers
CFLAGS += -DCPU_MCXN947VDF -DCPU_MCXN947VDF_cm33 -DCPU_MCXN947VDF_cm33_core0
CFLAGS += -mcpu=cortex-m33 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 $(CFLAGS_EXTRA)
CFLAGS += -Wno-old-style-declaration -Wno-unused-parameter # due to NXP FSL code
LDSCRIPT = link.ld
LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
SOURCES = main.c hal.c
SOURCES += startup.c
SOURCES += cmsis_mcu/devices/MCXN947/drivers/fsl_clock.c cmsis_mcu/devices/MCXN947/drivers/fsl_spc.c cmsis_mcu/devices/MCXN947/drivers/fsl_common_arm.c # NXP support files
# Mongoose options are defined in mongoose_config.h
SOURCES += mongoose.c net.c packed_fs.c
# Example specific build options. See README.md
CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\"
ifeq ($(OS),Windows_NT)
RM = cmd /C del /Q /F /S
else
RM = rm -rf
endif
all build example: firmware.bin
firmware.bin: firmware.elf
arm-none-eabi-objcopy -O binary $< $@
firmware.elf: cmsis_core cmsis_mcu $(SOURCES) hal.h link.ld Makefile
arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
arm-none-eabi-size $@
cmsis_core: # ARM CMSIS core headers
git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
cmsis_mcu:
wget -O $@.zip https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MCXN947_DFP.17.0.0.pack
mkdir $@ && cd $@ && unzip -q ../$@.zip
clean:
$(RM) firmware.* *.su cmsis_core cmsis_mcu *.zip

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examples/nxp/frdm-mcxn947-make-baremetal-builtin/hal.c Normal file
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// Copyright (c) 2024 Cesanta Software Limited
// All rights reserved
#include "hal.h"
static volatile uint64_t s_ticks; // Milliseconds since boot
void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
s_ticks++;
}
#if 0
void mg_random(void *buf, size_t len) { // Use on-board RNG
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
uint32_t r = rng_read();
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
}
}
#endif
uint64_t mg_millis(void) { // Let Mongoose use our uptime function
return s_ticks; // Return number of milliseconds since boot
}
void hal_init(void) {
clock_init(); // Set system clock to SYS_FREQUENCY
SystemCoreClock = SYS_FREQUENCY; // Update SystemCoreClock global var
SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
// rng_init(); // TRNG is part of ELS and there is no info on that
uart_init(UART_DEBUG, 115200); // Initialise UART
gpio_output(LED1); // Initialise LED1
gpio_write(LED1, 1);
gpio_output(LED2); // Initialise LED2
gpio_write(LED2, 1);
gpio_output(LED3); // Initialise LED3
gpio_write(LED3, 1);
ethernet_init(); // Initialise Ethernet pins
}
#if defined(__ARMCC_VERSION)
// Keil specific - implement IO printf redirection
int fputc(int c, FILE *stream) {
if (stream == stdout || stream == stderr) uart_write_byte(UART_DEBUG, c);
return c;
}
#elif defined(__GNUC__)
// ARM GCC specific. ARM GCC is shipped with Newlib C library.
// Implement newlib syscalls:
// _sbrk() for malloc
// _write() for printf redirection
// the rest are just stubs
#include <sys/stat.h> // For _fstat()
#if !defined(__MCUXPRESSO)
uint32_t SystemCoreClock;
// evaluate your use of Secure/non-Secure and modify accordingly
void SystemInit(void) { // Called automatically by startup code
SCB->CPACR |=
#if 0
(3UL << 0 * 2) | (3UL << 1 * 2) | // Enable PowerQuad (CPO/CP1)
#endif
(3UL << 10 * 2) | (3UL << 11 * 2); // Enable FPU
__DSB();
__ISB();
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; // enable LPCAC
// Read TRM 36.1 and decide whether you really want to enable aGDET and dGDET
#if 1
// Disable aGDET and dGDET
ITRC0->OUT_SEL[4][0] =
(ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) |
(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
ITRC0->OUT_SEL[4][1] =
(ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) |
(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK;
SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK;
SPC0->GLITCH_DETECT_SC = 0x3C;
SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK;
ITRC0->OUT_SEL[4][0] =
(ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) |
(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
ITRC0->OUT_SEL[4][1] =
(ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) |
(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
GDET0->GDET_ENABLE1 = 0;
GDET1->GDET_ENABLE1 = 0;
#endif
}
#endif
int _fstat(int fd, struct stat *st) {
(void) fd, (void) st;
return -1;
}
#if !defined(__MCUXPRESSO)
extern unsigned char _end[]; // End of data section, start of heap. See link.ld
static unsigned char *s_current_heap_end = _end;
size_t hal_ram_used(void) {
return (size_t) (s_current_heap_end - _end);
}
size_t hal_ram_free(void) {
unsigned char endofstack;
return (size_t) (&endofstack - s_current_heap_end);
}
void *_sbrk(int incr) {
unsigned char *prev_heap;
unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
prev_heap = s_current_heap_end;
// Check how much space we got from the heap end to the stack end
if (s_current_heap_end + incr > heap_end) return (void *) -1;
s_current_heap_end += incr;
return prev_heap;
}
#endif
int _open(const char *path) {
(void) path;
return -1;
}
int _close(int fd) {
(void) fd;
return -1;
}
int _isatty(int fd) {
(void) fd;
return 1;
}
int _lseek(int fd, int ptr, int dir) {
(void) fd, (void) ptr, (void) dir;
return 0;
}
void _exit(int status) {
(void) status;
for (;;) asm volatile("BKPT #0");
}
void _kill(int pid, int sig) {
(void) pid, (void) sig;
}
int _getpid(void) {
return -1;
}
int _write(int fd, char *ptr, int len) {
(void) fd, (void) ptr, (void) len;
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
return -1;
}
int _read(int fd, char *ptr, int len) {
(void) fd, (void) ptr, (void) len;
return -1;
}
int _link(const char *a, const char *b) {
(void) a, (void) b;
return -1;
}
int _unlink(const char *a) {
(void) a;
return -1;
}
int _stat(const char *path, struct stat *st) {
(void) path, (void) st;
return -1;
}
int mkdir(const char *path, mode_t mode) {
(void) path, (void) mode;
return -1;
}
void _init(void) {
}
#endif // __GNUC__

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examples/nxp/frdm-mcxn947-make-baremetal-builtin/hal.h Normal file
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// Copyright (c) 2023 Cesanta Software Limited
// All rights reserved
#pragma once
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#define LED1 PIN(0, 10)
#define LED2 PIN(0, 27)
#define LED3 PIN(1, 2)
#ifndef UART_DEBUG
#define UART_DEBUG LPUART4
#endif
#include "MCXN947_cm33_core0.h"
#define BIT(x) (1UL << (x))
#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
#define PIN(bank, num) ((bank << 8) | (num))
#define PINNO(pin) (pin & 255)
#define PINBANK(pin) (pin >> 8)
void hal_init(void);
size_t hal_ram_free(void);
size_t hal_ram_used(void);
static inline void spin(volatile uint32_t count) {
while (count--) (void) 0;
}
#define SYS_FREQUENCY 150000000UL
enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT };
enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
enum { GPIO_SPEED_LOW, GPIO_SPEED_HIGH };
enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP };
static inline GPIO_Type *gpio_bank(uint16_t pin) {
static GPIO_Type *const g[] = GPIO_BASE_PTRS;
return g[PINBANK(pin)];
}
static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
uint8_t speed, uint8_t pull, uint8_t af) {
static PORT_Type *const p[] = PORT_BASE_PTRS;
PORT_Type *port = p[PINBANK(pin)];
GPIO_Type *gpio = gpio_bank(pin);
uint32_t mask = (uint32_t) BIT(PINNO(pin));
bool dopull = pull > 0;
if (dopull) --pull;
if (gpio != GPIO5) {
SYSCON->AHBCLKCTRL0 |=
(1 << (SYSCON_AHBCLKCTRL0_GPIO0_SHIFT + PINBANK(pin))) |
(1 << (SYSCON_AHBCLKCTRL0_PORT0_SHIFT + PINBANK(pin)));
};
port->PCR[PINNO(pin)] = PORT_PCR_IBE(1) | PORT_PCR_MUX(af) | PORT_PCR_DSE(1) |
PORT_PCR_ODE(type) |
PORT_PCR_SRE(speed != GPIO_SPEED_HIGH) |
PORT_PCR_PE(dopull) | PORT_PCR_PS(pull);
gpio->ICR[PINNO(pin)] = GPIO_ICR_ISF_MASK;
if (mode == GPIO_MODE_INPUT) {
gpio->PDDR &= ~mask;
} else {
gpio->PDDR |= mask;
}
}
static inline void gpio_input(uint16_t pin) {
gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
GPIO_PULL_NONE, 0);
}
static inline void gpio_output(uint16_t pin) {
gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
GPIO_PULL_NONE, 0);
}
static inline bool gpio_read(uint16_t pin) {
GPIO_Type *gpio = gpio_bank(pin);
return gpio->PDR[PINNO(pin)];
}
static inline void gpio_write(uint16_t pin, bool value) {
GPIO_Type *gpio = gpio_bank(pin);
if (value) {
gpio->PDR[PINNO(pin)] = 1;
} else {
gpio->PDR[PINNO(pin)] = 0;
}
}
static inline void gpio_toggle(uint16_t pin) {
GPIO_Type *gpio = gpio_bank(pin);
uint32_t mask = (uint32_t) BIT(PINNO(pin));
gpio->PTOR = mask;
}
// MCU-Link UART (P1_9/8; FC4_P1/0)
// Arduino J1_2/4 UART (P4_3/2; FC2_P3/2)
// 33.3.23 LP_FLEXCOMM clocking
// 66.2.4 LP_FLEXCOMM init
// 66.5 LPUART
static inline void uart_init(LPUART_Type *uart, unsigned long baud) {
static LP_FLEXCOMM_Type *const f[] = LP_FLEXCOMM_BASE_PTRS;
uint8_t af = 2, fc = 0; // Alternate function, FlexComm instance
uint16_t pr = 0, pt = 0; // pins
uint32_t freq = 12000000; // fro_12_m
if (uart == LPUART2) fc = 2, pt = PIN(4, 3), pr = PIN(4, 2);
if (uart == LPUART4) fc = 4, pt = PIN(1, 9), pr = PIN(1, 8);
SYSCON->AHBCLKCTRL1 |= (1 << (SYSCON_AHBCLKCTRL1_FC0_SHIFT + fc));
SYSCON->PRESETCTRL1 |= (1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc));
SYSCON->PRESETCTRL1 &= ~(1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc));
SYSCON->FCCLKSEL[fc] = SYSCON_FCCLKSEL_SEL(2); // clock from FRO_12M / 1
SYSCON->FLEXCOMMCLKDIV[fc] = SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(0);
LP_FLEXCOMM_Type *flexcomm = f[fc];
flexcomm->PSELID = LP_FLEXCOMM_PSELID_PERSEL(1); // configure as UART
gpio_init(pt, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
GPIO_PULL_UP, af);
gpio_init(pr, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
GPIO_PULL_UP, af);
uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
// use a weird oversample ratio of 26x to fit specs, standard 16x won't do
CLRSET(uart->BAUD,
LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK,
LPUART_BAUD_OSR(26 - 1) | LPUART_BAUD_SBR(freq / (26 * baud)));
CLRSET(uart->CTRL,
LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
LPUART_CTRL_IDLECFG_MASK,
LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) |
LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit
uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
}
static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
uart->DATA = byte;
while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1);
}
static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
}
static inline void rng_init(void) {
}
static inline uint32_t rng_read(void) {
return 42;
}
// - PHY and MAC clocked via a 50MHz oscillator, P1_4 (ENET0_TXCLK)
// - 33.3.30 ENET clocking
// - SMI clocked from AHB module clock (CSR)
// - PHY RST connected to P5_8
// - PHY RXD0,1,DV = 1 on RST enable autonegotiation, no hw pull-ups
static inline void ethernet_init(void) {
// '0' in clk_rmii, set for RMII mode
SYSCON->ENETRMIICLKSEL = SYSCON_ENETRMIICLKSEL_SEL(0);
SYSCON->ENETRMIICLKDIV = SYSCON_ENETRMIICLKDIV_DIV(0);
SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_ENET_MASK; // enable bus clk
SYSCON0->PRESETCTRL2 = SYSCON_PRESETCTRL2_ENET_RST_MASK; // reset MAC
SYSCON0->PRESETCTRL2 &= ~SYSCON_PRESETCTRL2_ENET_RST_MASK; // then set RMII
SYSCON0->ENET_PHY_INTF_SEL |= SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_MASK;
gpio_init(PIN(5, 8), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
GPIO_PULL_NONE, 0); // set P5_8 as GPIO (PHY \RST)
gpio_write(PIN(5, 8), 0); // reset PHY
gpio_init(PIN(1, 4), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 9); // set P1_4 as ENET0_TXCLK
gpio_init(PIN(1, 5), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 9); // set P1_5 as ENET0_TXEN
gpio_init(PIN(1, 6), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 9); // set P1_6 as ENET0_TXD0
gpio_init(PIN(1, 7), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 9); // set P1_7 as ENET0_TXD1
gpio_init(PIN(1, 13), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_UP, 9); // set P1_13 as ENET0_RXDV
gpio_init(PIN(1, 14), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_UP, 9); // set P1_14 as ENET0_RXD0
gpio_init(PIN(1, 15), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_UP, 9); // set P1_15 as ENET0_RXD1
gpio_init(PIN(1, 20), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 9); // set P1_20 as ENET0_MDC
gpio_init(PIN(1, 21), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
GPIO_PULL_NONE, 9); // set P1_21 as ENET0_MDIO
spin(10000); // keep PHY RST low for a while
gpio_write(PIN(5, 8), 1); // deassert RST
NVIC_EnableIRQ(ETHERNET_IRQn); // Setup Ethernet IRQ handler
}
#include "fsl_clock.h"
#include "fsl_spc.h"
// 33.2 Figure 127 SCG main clock
static inline void clock_init(void) {
SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_SCG_MASK; // enable SCG clk
CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(2)); // clock main_clock
spc_active_mode_dcdc_option_t dcdc = {
.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength};
SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdc); // Set DCDC to 1.2 V
spc_active_mode_core_ldo_option_t ldo = {
.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength};
SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo); // Set LDO_CORE to 1.2 V
CLRSET(FMU0->FCTRL, FMU_FCTRL_RWSC_MASK, FMU_FCTRL_RWSC(3)); // Set Flash WS
spc_sram_voltage_config_t sram = {.operateVoltage = kSPC_sramOperateAt1P2V,
.requestVoltageUpdate = true};
SPC_SetSRAMOperateVoltage(SPC0, &sram); // Set SRAM timing for 1.2V
CLOCK_SetupFROHFClocking(48000000U); // Enable FRO HF
const pll_setup_t pll0 = {.pllctrl = SCG_APLLCTRL_SOURCE(1U) |
SCG_APLLCTRL_SELI(27U) |
SCG_APLLCTRL_SELP(13U),
.pllndiv = SCG_APLLNDIV_NDIV(8U),
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
.pllRate = 150000000U};
CLOCK_SetPLL0Freq(&pll0); // Setup PLL0 (APLL),
CLOCK_SetPll0MonitorMode(0); // disable monitor mode
CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(5)); // clock main_clock
SYSCON->AHBCLKDIV = SYSCON_AHBCLKDIV_DIV(0); // /1
}

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examples/nxp/frdm-mcxn947-make-baremetal-builtin/link.ld Normal file
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OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(Reset_Handler)
MEMORY
{
flash(RX) : ORIGIN = 0x0, LENGTH = 0x100000
flash2(RX) : ORIGIN = 0x100000, LENGTH = 0x100000
sram(!RX) : ORIGIN = 0x20000000, LENGTH = 0x60000
}
_estack = ORIGIN(sram) + LENGTH(sram);
SECTIONS
{
.vectors : { FILL(256) KEEP(*(.isr_vector)) } > flash
.text : { *(.text*) } > flash
.data : {
_sdata = .;
*(.first_data)
*(.data SORT(.data.*))
_edata = .;
} > sram AT > flash
_sidata = LOADADDR(.data);
.bss : { _sbss = .; *(.bss SORT(.bss.*) COMMON) _ebss = .; } > sram
. = ALIGN(8);
_end = .;
}

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// Copyright (c) 2024 Cesanta Software Limited
// All rights reserved
#include "hal.h"
#include "mongoose.h"
#include "net.h"
#define BLINK_PERIOD_MS 1000
static void timer_fn(void *arg) {
gpio_toggle(LED1); // Blink LED
(void) arg; // Unused
}
int main(void) {
struct mg_mgr mgr; // Mongoose event manager
hal_init(); // Cross-platform hardware init
mg_mgr_init(&mgr); // Initialise it
mg_log_set(MG_LL_DEBUG); // Set log level to debug
mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mgr);
MG_INFO(("Initialising application..."));
web_init(&mgr);
for (;;) {
mg_mgr_poll(&mgr, 0);
}
return 0;
}

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examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose.c Symbolic link
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../../../mongoose.c

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examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose.h Symbolic link
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../../../mongoose.h

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examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose_config.h Normal file
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#pragma once
// See https://mongoose.ws/documentation/#build-options
#define MG_ARCH MG_ARCH_NEWLIB
#define MG_ENABLE_TCPIP 1
#define MG_ENABLE_DRIVER_MCXN 1
#define MG_ENABLE_CUSTOM_MILLIS 1
//#define MG_ENABLE_CUSTOM_RANDOM 1
#define MG_ENABLE_PACKED_FS 1
// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
// By default, those are set to zero, meaning that DHCP is used
//
// #define MG_TCPIP_IP MG_IPV4(192, 168, 1, 10)
// #define MG_TCPIP_GW MG_IPV4(192, 168, 1, 1)
// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)
// Set custom MAC address. By default, it is randomly generated
// Using a build-time constant:
// #define MG_SET_MAC_ADDRESS(mac) do { uint8_t buf_[6] = {2,3,4,5,6,7}; memmove(mac, buf_, sizeof(buf_)); } while (0)
//
// Using custom function:
// extern void my_function(unsigned char *mac);
// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)

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examples/nxp/frdm-mcxn947-make-baremetal-builtin/net.c Symbolic link
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../../device-dashboard/net.c

1
examples/nxp/frdm-mcxn947-make-baremetal-builtin/net.h Symbolic link
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../../device-dashboard/net.h

1
examples/nxp/frdm-mcxn947-make-baremetal-builtin/packed_fs.c Symbolic link
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../../device-dashboard/packed_fs.c

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examples/nxp/frdm-mcxn947-make-baremetal-builtin/startup.c Normal file
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#include "MCXN947_cm33_core0.h"
void Reset_Handler(void); // Defined below
void Dummy_Handler(void); // Defined below
void SysTick_Handler(void); // Defined in main.c
void SystemInit(void); // Defined in main.c, called by reset handler
void _estack(void); // Defined in link.ld
#define WEAK_ALIAS __attribute__((weak, alias("Default_Handler")))
WEAK_ALIAS void NMI_Handler(void);
WEAK_ALIAS void HardFault_Handler(void);
WEAK_ALIAS void MemManage_Handler(void);
WEAK_ALIAS void BusFault_Handler(void);
WEAK_ALIAS void UsageFault_Handler(void);
WEAK_ALIAS void SecureFault_Handler(void);
WEAK_ALIAS void DebugMon_Handler(void);
WEAK_ALIAS void SVC_Handler(void);
WEAK_ALIAS void PendSV_Handler(void);
WEAK_ALIAS void SysTick_Handler(void);
WEAK_ALIAS void OR_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH0_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH1_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH2_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH3_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH4_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH5_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH6_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH7_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH8_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH9_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH10_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH11_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH12_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH13_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH14_IRQHandler(void);
WEAK_ALIAS void EDMA_0_CH15_IRQHandler(void);
WEAK_ALIAS void GPIO00_IRQHandler(void);
WEAK_ALIAS void GPIO01_IRQHandler(void);
WEAK_ALIAS void GPIO10_IRQHandler(void);
WEAK_ALIAS void GPIO11_IRQHandler(void);
WEAK_ALIAS void GPIO20_IRQHandler(void);
WEAK_ALIAS void GPIO21_IRQHandler(void);
WEAK_ALIAS void GPIO30_IRQHandler(void);
WEAK_ALIAS void GPIO31_IRQHandler(void);
WEAK_ALIAS void GPIO40_IRQHandler(void);
WEAK_ALIAS void GPIO41_IRQHandler(void);
WEAK_ALIAS void GPIO50_IRQHandler(void);
WEAK_ALIAS void GPIO51_IRQHandler(void);
WEAK_ALIAS void UTICK0_IRQHandler(void);
WEAK_ALIAS void MRT0_IRQHandler(void);
WEAK_ALIAS void CTIMER0_IRQHandler(void);
WEAK_ALIAS void CTIMER1_IRQHandler(void);
WEAK_ALIAS void SCT0_IRQHandler(void);
WEAK_ALIAS void CTIMER2_IRQHandler(void);
WEAK_ALIAS void LP_FLEXCOMM0_IRQHandler(void);
WEAK_ALIAS void LP_FLEXCOMM1_IRQHandler(void);
WEAK_ALIAS void LP_FLEXCOMM2_IRQHandler(void);
WEAK_ALIAS void LP_FLEXCOMM3_IRQHandler(void);
WEAK_ALIAS void LP_FLEXCOMM4_IRQHandler(void);
WEAK_ALIAS void LP_FLEXCOMM5_IRQHandler(void);
WEAK_ALIAS void LP_FLEXCOMM6_IRQHandler(void);
WEAK_ALIAS void LP_FLEXCOMM7_IRQHandler(void);
WEAK_ALIAS void LP_FLEXCOMM8_IRQHandler(void);
WEAK_ALIAS void LP_FLEXCOMM9_IRQHandler(void);
WEAK_ALIAS void ADC0_IRQHandler(void);
WEAK_ALIAS void ADC1_IRQHandler(void);
WEAK_ALIAS void PINT0_IRQHandler(void);
WEAK_ALIAS void PDM_EVENT_IRQHandler(void);
WEAK_ALIAS void Reserved65_IRQHandler(void);
WEAK_ALIAS void USB0_FS_IRQHandler(void);
WEAK_ALIAS void USB0_DCD_IRQHandler(void);
WEAK_ALIAS void RTC_IRQHandler(void);
WEAK_ALIAS void SMARTDMA_IRQHandler(void);
WEAK_ALIAS void MAILBOX_IRQHandler(void);
WEAK_ALIAS void CTIMER3_IRQHandler(void);
WEAK_ALIAS void CTIMER4_IRQHandler(void);
WEAK_ALIAS void OS_EVENT_IRQHandler(void);
WEAK_ALIAS void FLEXSPI0_IRQHandler(void);
WEAK_ALIAS void SAI0_IRQHandler(void);
WEAK_ALIAS void SAI1_IRQHandler(void);
WEAK_ALIAS void USDHC0_IRQHandler(void);
WEAK_ALIAS void CAN0_IRQHandler(void);
WEAK_ALIAS void CAN1_IRQHandler(void);
WEAK_ALIAS void Reserved80_IRQHandler(void);
WEAK_ALIAS void Reserved81_IRQHandler(void);
WEAK_ALIAS void USB1_HS_PHY_IRQHandler(void);
WEAK_ALIAS void USB1_HS_IRQHandler(void);
WEAK_ALIAS void SEC_HYPERVISOR_CALL_IRQHandler(void);
WEAK_ALIAS void Reserved85_IRQHandler(void);
WEAK_ALIAS void PLU_IRQHandler(void);
WEAK_ALIAS void Freqme_IRQHandler(void);
WEAK_ALIAS void SEC_VIO_IRQHandler(void);
WEAK_ALIAS void ELS_IRQHandler(void);
WEAK_ALIAS void PKC_IRQHandler(void);
WEAK_ALIAS void PUF_IRQHandler(void);
WEAK_ALIAS void PQ_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH0_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH1_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH2_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH3_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH4_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH5_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH6_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH7_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH8_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH9_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH10_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH11_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH12_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH13_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH14_IRQHandler(void);
WEAK_ALIAS void EDMA_1_CH15_IRQHandler(void);
WEAK_ALIAS void CDOG0_IRQHandler(void);
WEAK_ALIAS void CDOG1_IRQHandler(void);
WEAK_ALIAS void I3C0_IRQHandler(void);
WEAK_ALIAS void I3C1_IRQHandler(void);
WEAK_ALIAS void NPU_IRQHandler(void);
WEAK_ALIAS void GDET_IRQHandler(void);
WEAK_ALIAS void VBAT0_IRQHandler(void);
WEAK_ALIAS void EWM0_IRQHandler(void);
WEAK_ALIAS void TSI_END_OF_SCAN_IRQHandler(void);
WEAK_ALIAS void TSI_OUT_OF_SCAN_IRQHandler(void);
WEAK_ALIAS void EMVSIM0_IRQHandler(void);
WEAK_ALIAS void EMVSIM1_IRQHandler(void);
WEAK_ALIAS void FLEXIO_IRQHandler(void);
WEAK_ALIAS void DAC0_IRQHandler(void);
WEAK_ALIAS void DAC1_IRQHandler(void);
WEAK_ALIAS void DAC2_IRQHandler(void);
WEAK_ALIAS void HSCMP0_IRQHandler(void);
WEAK_ALIAS void HSCMP1_IRQHandler(void);
WEAK_ALIAS void HSCMP2_IRQHandler(void);
WEAK_ALIAS void FLEXPWM0_RELOAD_ERROR_IRQHandler(void);
WEAK_ALIAS void FLEXPWM0_FAULT_IRQHandler(void);
WEAK_ALIAS void FLEXPWM0_SUBMODULE0_IRQHandler(void);
WEAK_ALIAS void FLEXPWM0_SUBMODULE1_IRQHandler(void);
WEAK_ALIAS void FLEXPWM0_SUBMODULE2_IRQHandler(void);
WEAK_ALIAS void FLEXPWM0_SUBMODULE3_IRQHandler(void);
WEAK_ALIAS void FLEXPWM1_RELOAD_ERROR_IRQHandler(void);
WEAK_ALIAS void FLEXPWM1_FAULT_IRQHandler(void);
WEAK_ALIAS void FLEXPWM1_SUBMODULE0_IRQHandler(void);
WEAK_ALIAS void FLEXPWM1_SUBMODULE1_IRQHandler(void);
WEAK_ALIAS void FLEXPWM1_SUBMODULE2_IRQHandler(void);
WEAK_ALIAS void FLEXPWM1_SUBMODULE3_IRQHandler(void);
WEAK_ALIAS void ENC0_COMPARE_IRQHandler(void);
WEAK_ALIAS void ENC0_HOME_IRQHandler(void);
WEAK_ALIAS void ENC0_WDG_SAB_IRQHandler(void);
WEAK_ALIAS void ENC0_IDX_IRQHandler(void);
WEAK_ALIAS void ENC1_COMPARE_IRQHandler(void);
WEAK_ALIAS void ENC1_HOME_IRQHandler(void);
WEAK_ALIAS void ENC1_WDG_SAB_IRQHandler(void);
WEAK_ALIAS void ENC1_IDX_IRQHandler(void);
WEAK_ALIAS void ITRC0_IRQHandler(void);
WEAK_ALIAS void BSP32_IRQHandler(void);
WEAK_ALIAS void ELS_ERR_IRQHandler(void);
WEAK_ALIAS void PKC_ERR_IRQHandler(void);
WEAK_ALIAS void ERM_SINGLE_BIT_ERROR_IRQHandler(void);
WEAK_ALIAS void ERM_MULTI_BIT_ERROR_IRQHandler(void);
WEAK_ALIAS void FMU0_IRQHandler(void);
WEAK_ALIAS void ETHERNET_IRQHandler(void);
WEAK_ALIAS void ETHERNET_PMT_IRQHandler(void);
WEAK_ALIAS void ETHERNET_MACLP_IRQHandler(void);
WEAK_ALIAS void SINC_FILTER_IRQHandler(void);
WEAK_ALIAS void LPTMR0_IRQHandler(void);
WEAK_ALIAS void LPTMR1_IRQHandler(void);
WEAK_ALIAS void SCG_IRQHandler(void);
WEAK_ALIAS void SPC_IRQHandler(void);
WEAK_ALIAS void WUU_IRQHandler(void);
WEAK_ALIAS void PORT_EFT_IRQHandler(void);
WEAK_ALIAS void ETB0_IRQHandler(void);
WEAK_ALIAS void SM3_IRQHandler(void);
WEAK_ALIAS void TRNG0_IRQHandler(void);
WEAK_ALIAS void WWDT0_IRQHandler(void);
WEAK_ALIAS void WWDT1_IRQHandler(void);
WEAK_ALIAS void CMC0_IRQHandler(void);
WEAK_ALIAS void CTI0_IRQHandler(void);
__attribute__((section(".vectors"))) void (*const tab[16 + 156])(void) = {
_estack, Reset_Handler,
NMI_Handler, // NMI Handler
HardFault_Handler, // Hard Fault Handler
MemManage_Handler, // MPU Fault Handler
BusFault_Handler, // Bus Fault Handler
UsageFault_Handler, // Usage Fault Handler
SecureFault_Handler, // Secure Fault Handler
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall Handler
DebugMon_Handler, // Debug Monitor Handler
0, // Reserved
PendSV_Handler, // PendSV Handler
SysTick_Handler, // SysTick Handler
// Chip Level - MCXN947_cm33_core0
OR_IRQHandler, // 16 : OR IRQ
EDMA_0_CH0_IRQHandler, // 17 : eDMA_0_CH0 error or transfer complete
EDMA_0_CH1_IRQHandler, // 18 : eDMA_0_CH1 error or transfer complete
EDMA_0_CH2_IRQHandler, // 19 : eDMA_0_CH2 error or transfer complete
EDMA_0_CH3_IRQHandler, // 20 : eDMA_0_CH3 error or transfer complete
EDMA_0_CH4_IRQHandler, // 21 : eDMA_0_CH4 error or transfer complete
EDMA_0_CH5_IRQHandler, // 22 : eDMA_0_CH5 error or transfer complete
EDMA_0_CH6_IRQHandler, // 23 : eDMA_0_CH6 error or transfer complete
EDMA_0_CH7_IRQHandler, // 24 : eDMA_0_CH7 error or transfer complete
EDMA_0_CH8_IRQHandler, // 25 : eDMA_0_CH8 error or transfer complete
EDMA_0_CH9_IRQHandler, // 26 : eDMA_0_CH9 error or transfer complete
EDMA_0_CH10_IRQHandler, // 27 : eDMA_0_CH10 error or transfer complete
EDMA_0_CH11_IRQHandler, // 28 : eDMA_0_CH11 error or transfer complete
EDMA_0_CH12_IRQHandler, // 29 : eDMA_0_CH12 error or transfer complete
EDMA_0_CH13_IRQHandler, // 30 : eDMA_0_CH13 error or transfer complete
EDMA_0_CH14_IRQHandler, // 31 : eDMA_0_CH14 error or transfer complete
EDMA_0_CH15_IRQHandler, // 32 : eDMA_0_CH15 error or transfer complete
GPIO00_IRQHandler, // 33 : GPIO0 interrupt 0
GPIO01_IRQHandler, // 34 : GPIO0 interrupt 1
GPIO10_IRQHandler, // 35 : GPIO1 interrupt 0
GPIO11_IRQHandler, // 36 : GPIO1 interrupt 1
GPIO20_IRQHandler, // 37 : GPIO2 interrupt 0
GPIO21_IRQHandler, // 38 : GPIO2 interrupt 1
GPIO30_IRQHandler, // 39 : GPIO3 interrupt 0
GPIO31_IRQHandler, // 40 : GPIO3 interrupt 1
GPIO40_IRQHandler, // 41 : GPIO4 interrupt 0
GPIO41_IRQHandler, // 42 : GPIO4 interrupt 1
GPIO50_IRQHandler, // 43 : GPIO5 interrupt 0
GPIO51_IRQHandler, // 44 : GPIO5 interrupt 1
UTICK0_IRQHandler, // 45 : Micro-Tick Timer interrupt
MRT0_IRQHandler, // 46 : Multi-Rate Timer interrupt
CTIMER0_IRQHandler, // 47 : Standard counter/timer 0 interrupt
CTIMER1_IRQHandler, // 48 : Standard counter/timer 1 interrupt
SCT0_IRQHandler, // 49 : SCTimer/PWM interrupt
CTIMER2_IRQHandler, // 50 : Standard counter/timer 2 interrupt
LP_FLEXCOMM0_IRQHandler, // 51 : LP_FLEXCOMM0 (LPSPI interrupt or LPI2C
// interrupt or LPUART Receive/Transmit interrupt)
LP_FLEXCOMM1_IRQHandler, // 52 : LP_FLEXCOMM1 (LPSPI interrupt or LPI2C
// interrupt or LPUART Receive/Transmit interrupt)
LP_FLEXCOMM2_IRQHandler, // 53 : LP_FLEXCOMM2 (LPSPI interrupt or LPI2C
// interrupt or LPUART Receive/Transmit interrupt)
LP_FLEXCOMM3_IRQHandler, // 54 : LP_FLEXCOMM3 (LPSPI interrupt or LPI2C
// interrupt or LPUART Receive/Transmit interrupt)
LP_FLEXCOMM4_IRQHandler, // 55 : LP_FLEXCOMM4 (LPSPI interrupt or LPI2C
// interrupt or LPUART Receive/Transmit interrupt)
LP_FLEXCOMM5_IRQHandler, // 56 : LP_FLEXCOMM5 (LPSPI interrupt or LPI2C
// interrupt or LPUART Receive/Transmit interrupt)
LP_FLEXCOMM6_IRQHandler, // 57 : LP_FLEXCOMM6 (LPSPI interrupt or LPI2C
// interrupt or LPUART Receive/Transmit interrupt)
LP_FLEXCOMM7_IRQHandler, // 58 : LP_FLEXCOMM7 (LPSPI interrupt or LPI2C
// interrupt or LPUART Receive/Transmit interrupt)
LP_FLEXCOMM8_IRQHandler, // 59 : LP_FLEXCOMM8 (LPSPI interrupt or LPI2C
// interrupt or LPUART Receive/Transmit interrupt)
LP_FLEXCOMM9_IRQHandler, // 60 : LP_FLEXCOMM9 (LPSPI interrupt or LPI2C
// interrupt or LPUART Receive/Transmit interrupt)
ADC0_IRQHandler, // 61 : Analog-to-Digital Converter 0 - General Purpose
// interrupt
ADC1_IRQHandler, // 62 : Analog-to-Digital Converter 1 - General Purpose
// interrupt
PINT0_IRQHandler, // 63 : Pin Interrupt Pattern Match Interrupt
PDM_EVENT_IRQHandler, // 64 : Microphone Interface interrupt
Reserved65_IRQHandler, // 65 : Reserved interrupt
USB0_FS_IRQHandler, // 66 : Universal Serial Bus - Full Speed interrupt
USB0_DCD_IRQHandler, // 67 : Universal Serial Bus - Device Charge Detect
// interrupt
RTC_IRQHandler, // 68 : RTC Subsystem interrupt (RTC interrupt or Wake
// timer interrupt)
SMARTDMA_IRQHandler, // 69 : SmartDMA_IRQ
MAILBOX_IRQHandler, // 70 : Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU
// Mailbox interrupt1 for CPU1
CTIMER3_IRQHandler, // 71 : Standard counter/timer 3 interrupt
CTIMER4_IRQHandler, // 72 : Standard counter/timer 4 interrupt
OS_EVENT_IRQHandler, // 73 : OS event timer interrupt
FLEXSPI0_IRQHandler, // 74 : Flexible Serial Peripheral Interface interrupt
SAI0_IRQHandler, // 75 : Serial Audio Interface 0 interrupt
SAI1_IRQHandler, // 76 : Serial Audio Interface 1 interrupt
USDHC0_IRQHandler, // 77 : Ultra Secured Digital Host Controller interrupt
CAN0_IRQHandler, // 78 : Controller Area Network 0 interrupt
CAN1_IRQHandler, // 79 : Controller Area Network 1 interrupt
Reserved80_IRQHandler, // 80 : Reserved interrupt
Reserved81_IRQHandler, // 81 : Reserved interrupt
USB1_HS_PHY_IRQHandler, // 82 : USBHS DCD or USBHS Phy interrupt
USB1_HS_IRQHandler, // 83 : USB High Speed OTG Controller interrupt
SEC_HYPERVISOR_CALL_IRQHandler, // 84 : AHB Secure Controller hypervisor
// call interrupt
Reserved85_IRQHandler, // 85 : Reserved interrupt
PLU_IRQHandler, // 86 : Programmable Logic Unit interrupt
Freqme_IRQHandler, // 87 : Frequency Measurement interrupt
SEC_VIO_IRQHandler, // 88 : Secure violation interrupt (Memory Block
// Checker interrupt or secure AHB matrix violation
// interrupt)
ELS_IRQHandler, // 89 : ELS interrupt
PKC_IRQHandler, // 90 : PKC interrupt
PUF_IRQHandler, // 91 : Physical Unclonable Function interrupt
PQ_IRQHandler, // 92 : Power Quad interrupt
EDMA_1_CH0_IRQHandler, // 93 : eDMA_1_CH0 error or transfer complete
EDMA_1_CH1_IRQHandler, // 94 : eDMA_1_CH1 error or transfer complete
EDMA_1_CH2_IRQHandler, // 95 : eDMA_1_CH2 error or transfer complete
EDMA_1_CH3_IRQHandler, // 96 : eDMA_1_CH3 error or transfer complete
EDMA_1_CH4_IRQHandler, // 97 : eDMA_1_CH4 error or transfer complete
EDMA_1_CH5_IRQHandler, // 98 : eDMA_1_CH5 error or transfer complete
EDMA_1_CH6_IRQHandler, // 99 : eDMA_1_CH6 error or transfer complete
EDMA_1_CH7_IRQHandler, // 100: eDMA_1_CH7 error or transfer complete
EDMA_1_CH8_IRQHandler, // 101: eDMA_1_CH8 error or transfer complete
EDMA_1_CH9_IRQHandler, // 102: eDMA_1_CH9 error or transfer complete
EDMA_1_CH10_IRQHandler, // 103: eDMA_1_CH10 error or transfer complete
EDMA_1_CH11_IRQHandler, // 104: eDMA_1_CH11 error or transfer complete
EDMA_1_CH12_IRQHandler, // 105: eDMA_1_CH12 error or transfer complete
EDMA_1_CH13_IRQHandler, // 106: eDMA_1_CH13 error or transfer complete
EDMA_1_CH14_IRQHandler, // 107: eDMA_1_CH14 error or transfer complete
EDMA_1_CH15_IRQHandler, // 108: eDMA_1_CH15 error or transfer complete
CDOG0_IRQHandler, // 109: Code Watchdog Timer 0 interrupt
CDOG1_IRQHandler, // 110: Code Watchdog Timer 1 interrupt
I3C0_IRQHandler, // 111: Improved Inter Integrated Circuit interrupt 0
I3C1_IRQHandler, // 112: Improved Inter Integrated Circuit interrupt 1
NPU_IRQHandler, // 113: NPU interrupt
GDET_IRQHandler, // 114: Digital Glitch Detect 0 interrupt or Digital
// Glitch Detect 1 interrupt
VBAT0_IRQHandler, // 115: VBAT interrupt( VBAT interrupt or digital tamper
// interrupt)
EWM0_IRQHandler, // 116: External Watchdog Monitor interrupt
TSI_END_OF_SCAN_IRQHandler, // 117: TSI End of Scan interrupt
TSI_OUT_OF_SCAN_IRQHandler, // 118: TSI Out of Scan interrupt
EMVSIM0_IRQHandler, // 119: EMVSIM0 interrupt
EMVSIM1_IRQHandler, // 120: EMVSIM1 interrupt
FLEXIO_IRQHandler, // 121: Flexible Input/Output interrupt
DAC0_IRQHandler, // 122: Digital-to-Analog Converter 0 - General Purpose
// interrupt
DAC1_IRQHandler, // 123: Digital-to-Analog Converter 1 - General Purpose
// interrupt
DAC2_IRQHandler, // 124: 14-bit Digital-to-Analog Converter interrupt
HSCMP0_IRQHandler, // 125: High-Speed comparator0 interrupt
HSCMP1_IRQHandler, // 126: High-Speed comparator1 interrupt
HSCMP2_IRQHandler, // 127: High-Speed comparator2 interrupt
FLEXPWM0_RELOAD_ERROR_IRQHandler, // 128: FlexPWM0_reload_error interrupt
FLEXPWM0_FAULT_IRQHandler, // 129: FlexPWM0_fault interrupt
FLEXPWM0_SUBMODULE0_IRQHandler, // 130: FlexPWM0 Submodule 0
// capture/compare/reload interrupt
FLEXPWM0_SUBMODULE1_IRQHandler, // 131: FlexPWM0 Submodule 1
// capture/compare/reload interrupt
FLEXPWM0_SUBMODULE2_IRQHandler, // 132: FlexPWM0 Submodule 2
// capture/compare/reload interrupt
FLEXPWM0_SUBMODULE3_IRQHandler, // 133: FlexPWM0 Submodule 3
// capture/compare/reload interrupt
FLEXPWM1_RELOAD_ERROR_IRQHandler, // 134: FlexPWM1_reload_error interrupt
FLEXPWM1_FAULT_IRQHandler, // 135: FlexPWM1_fault interrupt
FLEXPWM1_SUBMODULE0_IRQHandler, // 136: FlexPWM1 Submodule 0
// capture/compare/reload interrupt
FLEXPWM1_SUBMODULE1_IRQHandler, // 137: FlexPWM1 Submodule 1
// capture/compare/reload interrupt
FLEXPWM1_SUBMODULE2_IRQHandler, // 138: FlexPWM1 Submodule 2
// capture/compare/reload interrupt
FLEXPWM1_SUBMODULE3_IRQHandler, // 139: FlexPWM1 Submodule 3
// capture/compare/reload interrupt
ENC0_COMPARE_IRQHandler, // 140: ENC0_Compare interrupt
ENC0_HOME_IRQHandler, // 141: ENC0_Home interrupt
ENC0_WDG_SAB_IRQHandler, // 142: ENC0_WDG_IRQ/SAB interrupt
ENC0_IDX_IRQHandler, // 143: ENC0_IDX interrupt
ENC1_COMPARE_IRQHandler, // 144: ENC1_Compare interrupt
ENC1_HOME_IRQHandler, // 145: ENC1_Home interrupt
ENC1_WDG_SAB_IRQHandler, // 146: ENC1_WDG_IRQ/SAB interrupt
ENC1_IDX_IRQHandler, // 147: ENC1_IDX interrupt
ITRC0_IRQHandler, // 148: Intrusion and Tamper Response Controller
// interrupt
BSP32_IRQHandler, // 149: CoolFlux BSP32 interrupt
ELS_ERR_IRQHandler, // 150: ELS error interrupt
PKC_ERR_IRQHandler, // 151: PKC error interrupt
ERM_SINGLE_BIT_ERROR_IRQHandler, // 152: ERM Single Bit error interrupt
ERM_MULTI_BIT_ERROR_IRQHandler, // 153: ERM Multi Bit error interrupt
FMU0_IRQHandler, // 154: Flash Management Unit interrupt
ETHERNET_IRQHandler, // 155: Ethernet QoS interrupt
ETHERNET_PMT_IRQHandler, // 156: Ethernet QoS power management interrupt
ETHERNET_MACLP_IRQHandler, // 157: Ethernet QoS MAC interrupt
SINC_FILTER_IRQHandler, // 158: SINC Filter interrupt
LPTMR0_IRQHandler, // 159: Low Power Timer 0 interrupt
LPTMR1_IRQHandler, // 160: Low Power Timer 1 interrupt
SCG_IRQHandler, // 161: System Clock Generator interrupt
SPC_IRQHandler, // 162: System Power Controller interrupt
WUU_IRQHandler, // 163: Wake Up Unit interrupt
PORT_EFT_IRQHandler, // 164: PORT0~5 EFT interrupt
ETB0_IRQHandler, // 165: ETB counter expires interrupt
SM3_IRQHandler, // 166: Secure Generic Interface (SGI) SAFO interrupt
TRNG0_IRQHandler, // 167: True Random Number Generator interrupt
WWDT0_IRQHandler, // 168: Windowed Watchdog Timer 0 interrupt
WWDT1_IRQHandler, // 169: Windowed Watchdog Timer 1 interrupt
CMC0_IRQHandler, // 170: Core Mode Controller interrupt
CTI0_IRQHandler, // 171: Cross Trigger Interface interrupt
};
extern unsigned char _end[]; // End of data section, start of heap. See link.ld
__attribute__((naked, noreturn)) void Reset_Handler(void) {
__asm("cpsid i"); // Disable interrupts
// set SPLIM to somewhere, trick the linker
__asm volatile("MSR MSPLIM, %1 \n"
:
: "r"(tab), "r"(_end)
: "r0", "r1");
SYSCON->ECC_ENABLE_CTRL = 0; // disable RAM ECC, must do for this link.ld
// Clear BSS section, and copy data section from flash to RAM
extern long _sbss, _ebss, _sdata, _edata, _sidata;
for (long *dst = &_sbss; dst < &_ebss; dst++) *dst = 0;
for (long *dst = &_sdata, *src = &_sidata; dst < &_edata;) *dst++ = *src++;
SystemInit();
__asm("cpsie i"); // Reenable interrupts
// Call main()
extern void main(void);
main();
for (;;) (void) 0; // Infinite loop
}
void Default_Handler(void) {
for (;;) (void) 0;
}

1
examples/stm32/nucleo-f429zi-make-baremetal-builtin/hal.h
View File

@ -137,6 +137,7 @@ static inline uint32_t rng_read(void) {
return RNG->DR;
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see
// https://www.farnell.com/datasheets/2014265.pdf section 6.10

1
examples/stm32/nucleo-f429zi-make-freertos-builtin/hal.h
View File

@ -137,6 +137,7 @@ static inline uint32_t rng_read(void) {
return RNG->DR;
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see
// https://www.farnell.com/datasheets/2014265.pdf section 6.10

1
examples/stm32/nucleo-f746zg-make-baremetal-builtin-cmsis_driver/hal.h
View File

@ -138,6 +138,7 @@ static inline uint32_t rng_read(void) {
return RNG->DR;
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see
// https://www.farnell.com/datasheets/2014265.pdf section 6.10

1
examples/stm32/nucleo-f746zg-make-baremetal-builtin/hal.h
View File

@ -138,6 +138,7 @@ static inline uint32_t rng_read(void) {
return RNG->DR;
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see
// https://www.farnell.com/datasheets/2014265.pdf section 6.10

1
examples/stm32/nucleo-f746zg-make-freertos-builtin/hal.h
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@ -138,6 +138,7 @@ static inline uint32_t rng_read(void) {
return RNG->DR;
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see
// https://www.farnell.com/datasheets/2014265.pdf section 6.10

1
examples/stm32/nucleo-h563zi-make-baremetal-builtin/hal.h
View File

@ -149,6 +149,7 @@ static inline bool ldo_is_on(void) {
return (PWR->SCCR & PWR_SCCR_LDOEN) == PWR_SCCR_LDOEN;
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see UM3115 section 10.7
uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),

1
examples/stm32/nucleo-h563zi-make-freertos-builtin/hal.h
View File

@ -149,6 +149,7 @@ static inline bool ldo_is_on(void) {
return (PWR->SCCR & PWR_SCCR_LDOEN) == PWR_SCCR_LDOEN;
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see UM3115 section 10.7
uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),

1
examples/stm32/nucleo-h723zg-make-baremetal-builtin/hal.h
View File

@ -161,6 +161,7 @@ static inline uint32_t rng_read(void) {
return RNG->DR;
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see
// https://www.st.com/resource/en/user_manual/um2407-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf

1
examples/stm32/nucleo-h723zg-make-freertos-builtin/hal.h
View File

@ -161,6 +161,7 @@ static inline uint32_t rng_read(void) {
return RNG->DR;
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see
// https://www.st.com/resource/en/user_manual/um2407-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf

1
examples/stm32/nucleo-h743zi-make-baremetal-builtin/hal.h
View File

@ -208,6 +208,7 @@ static inline void clock_init(void) {
FLASH->ACR = FLASH_LATENCY; // default is larger
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see
// https://www.st.com/resource/en/user_manual/um2407-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf

1
examples/stm32/nucleo-h743zi-make-freertos-builtin/hal.h
View File

@ -159,6 +159,7 @@ static inline char chiprev(void) {
return '?';
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see
// https://www.st.com/resource/en/user_manual/um2407-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf

1
examples/stm32/stm32h573i-dk-make-baremetal-builtin/hal.h
View File

@ -149,6 +149,7 @@ static inline bool ldo_is_on(void) {
return (PWR->SCCR & PWR_SCCR_LDOEN) == PWR_SCCR_LDOEN;
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see UM3115 section 10.7
uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),

1
examples/stm32/stm32h573i-dk-make-freertos-builtin/hal.h
View File

@ -149,6 +149,7 @@ static inline bool ldo_is_on(void) {
return (PWR->SCCR & PWR_SCCR_LDOEN) == PWR_SCCR_LDOEN;
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see UM3115 section 10.7
uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),

1
examples/stm32/stm32h747i-disco-make-baremetal-builtin/hal.h
View File

@ -161,6 +161,7 @@ static inline char chiprev(void) {
return '?';
}
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
static inline void ethernet_init(void) {
// Initialise Ethernet. Enable MAC GPIO pins, see UM2411
uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),