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https://github.com/cesanta/mongoose.git
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Fix #2487 - correct GMAC_DCFGR, receive size -> full size
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cpq
parent
36748ee406
commit
9cfd3124ef
33
mongoose.c
33
mongoose.c
@ -8874,9 +8874,7 @@ struct mg_tcpip_driver mg_tcpip_driver_imxrt = {mg_tcpip_driver_imxrt_init,
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#endif
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_SAME54) && \
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MG_ENABLE_DRIVER_SAME54
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#if defined(MG_ENABLE_DRIVER_SAME54) && MG_ENABLE_DRIVER_SAME54
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#include <sam.h>
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#define ETH_PKT_SIZE 1536 // Max frame size
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@ -8933,12 +8931,8 @@ int get_clock_rate(struct mg_tcpip_driver_same54_data *d) {
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case GCLK_GENCTRL_SRC_XOSC1_Val:
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mclk = 32000000UL; /* 32MHz */
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break;
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case GCLK_GENCTRL_SRC_OSCULP32K_Val:
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mclk = 32000UL;
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break;
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case GCLK_GENCTRL_SRC_XOSC32K_Val:
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mclk = 32000UL;
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break;
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case GCLK_GENCTRL_SRC_OSCULP32K_Val: mclk = 32000UL; break;
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case GCLK_GENCTRL_SRC_XOSC32K_Val: mclk = 32000UL; break;
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case GCLK_GENCTRL_SRC_DFLL_Val:
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mclk = 48000000UL; /* 48MHz */
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break;
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@ -8948,13 +8942,12 @@ int get_clock_rate(struct mg_tcpip_driver_same54_data *d) {
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case GCLK_GENCTRL_SRC_DPLL1_Val:
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mclk = 200000000UL; /* 200MHz */
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break;
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default:
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mclk = 200000000UL; /* 200MHz */
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default: mclk = 200000000UL; /* 200MHz */
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}
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mclk /= div;
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uint8_t crs[] = {0, 1, 2, 3, 4, 5}; // GMAC->NCFGR::CLK values
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uint8_t dividers[] = {8, 16, 32, 48, 64, 128}; // Respective CLK dividers
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uint8_t crs[] = {0, 1, 2, 3, 4, 5}; // GMAC->NCFGR::CLK values
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uint8_t dividers[] = {8, 16, 32, 48, 64, 96}; // Respective CLK dividers
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for (int i = 0; i < 6; i++) {
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if (mclk / dividers[i] <= 2375000UL /* 2.5MHz - 5% */) {
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return crs[i];
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@ -8978,14 +8971,16 @@ static bool mg_tcpip_driver_same54_init(struct mg_tcpip_if *ifp) {
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for (int i = 0; i < ETH_DESC_CNT; i++) { // Init TX descriptors
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s_txdesc[i][0] = (uint32_t) s_txbuf[i]; // Point to data buffer
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s_txdesc[i][1] = MG_BIT(31); // OWN bit
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s_txdesc[i][1] = MG_BIT(31); // OWN bit
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}
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s_txdesc[ETH_DESC_CNT - 1][1] |= MG_BIT(30); // Last tx descriptor - wrap
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GMAC_REGS->GMAC_DCFGR = GMAC_DCFGR_DRBS(0x18); // DMA recv buf 1536
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for (int i = 0; i < ETH_DESC_CNT; i++) { // Init RX descriptors
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s_rxdesc[i][0] = (uint32_t) s_rxbuf[i]; // Address of the data buffer
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s_rxdesc[i][1] = 0; // Clear status
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GMAC_REGS->GMAC_DCFGR = GMAC_DCFGR_DRBS(0x18) // DMA recv buf 1536
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| GMAC_DCFGR_RXBMS(GMAC_DCFGR_RXBMS_FULL_Val) |
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GMAC_DCFGR_TXPBMS(1); // See #2487
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for (int i = 0; i < ETH_DESC_CNT; i++) { // Init RX descriptors
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s_rxdesc[i][0] = (uint32_t) s_rxbuf[i]; // Address of the data buffer
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s_rxdesc[i][1] = 0; // Clear status
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}
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s_rxdesc[ETH_DESC_CNT - 1][0] |= MG_BIT(1); // Last rx descriptor - wrap
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@ -9028,7 +9023,7 @@ static size_t mg_tcpip_driver_same54_tx(const void *buf, size_t len,
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} else {
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uint32_t status = len | MG_BIT(15); // Frame length, last chunk
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if (s_txno == ETH_DESC_CNT - 1) status |= MG_BIT(30); // wrap
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][1] = status;
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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@ -1856,14 +1856,10 @@ struct mg_tcpip_driver_imxrt_data {
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};
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_SAME54) && MG_ENABLE_DRIVER_SAME54
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struct mg_tcpip_driver_same54_data {
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int mdc_cr;
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};
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#endif
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struct mg_tcpip_driver_stm32_data {
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// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz
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@ -1,8 +1,6 @@
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#include "tcpip.h"
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_SAME54) && \
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MG_ENABLE_DRIVER_SAME54
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#if defined(MG_ENABLE_DRIVER_SAME54) && MG_ENABLE_DRIVER_SAME54
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#include <sam.h>
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#define ETH_PKT_SIZE 1536 // Max frame size
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@ -59,12 +57,8 @@ int get_clock_rate(struct mg_tcpip_driver_same54_data *d) {
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case GCLK_GENCTRL_SRC_XOSC1_Val:
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mclk = 32000000UL; /* 32MHz */
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break;
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case GCLK_GENCTRL_SRC_OSCULP32K_Val:
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mclk = 32000UL;
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break;
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case GCLK_GENCTRL_SRC_XOSC32K_Val:
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mclk = 32000UL;
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break;
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case GCLK_GENCTRL_SRC_OSCULP32K_Val: mclk = 32000UL; break;
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case GCLK_GENCTRL_SRC_XOSC32K_Val: mclk = 32000UL; break;
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case GCLK_GENCTRL_SRC_DFLL_Val:
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mclk = 48000000UL; /* 48MHz */
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break;
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@ -74,13 +68,12 @@ int get_clock_rate(struct mg_tcpip_driver_same54_data *d) {
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case GCLK_GENCTRL_SRC_DPLL1_Val:
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mclk = 200000000UL; /* 200MHz */
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break;
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default:
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mclk = 200000000UL; /* 200MHz */
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default: mclk = 200000000UL; /* 200MHz */
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}
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mclk /= div;
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uint8_t crs[] = {0, 1, 2, 3, 4, 5}; // GMAC->NCFGR::CLK values
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uint8_t dividers[] = {8, 16, 32, 48, 64, 128}; // Respective CLK dividers
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uint8_t crs[] = {0, 1, 2, 3, 4, 5}; // GMAC->NCFGR::CLK values
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uint8_t dividers[] = {8, 16, 32, 48, 64, 96}; // Respective CLK dividers
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for (int i = 0; i < 6; i++) {
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if (mclk / dividers[i] <= 2375000UL /* 2.5MHz - 5% */) {
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return crs[i];
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@ -104,14 +97,16 @@ static bool mg_tcpip_driver_same54_init(struct mg_tcpip_if *ifp) {
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for (int i = 0; i < ETH_DESC_CNT; i++) { // Init TX descriptors
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s_txdesc[i][0] = (uint32_t) s_txbuf[i]; // Point to data buffer
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s_txdesc[i][1] = MG_BIT(31); // OWN bit
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s_txdesc[i][1] = MG_BIT(31); // OWN bit
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}
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s_txdesc[ETH_DESC_CNT - 1][1] |= MG_BIT(30); // Last tx descriptor - wrap
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GMAC_REGS->GMAC_DCFGR = GMAC_DCFGR_DRBS(0x18); // DMA recv buf 1536
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for (int i = 0; i < ETH_DESC_CNT; i++) { // Init RX descriptors
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s_rxdesc[i][0] = (uint32_t) s_rxbuf[i]; // Address of the data buffer
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s_rxdesc[i][1] = 0; // Clear status
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GMAC_REGS->GMAC_DCFGR = GMAC_DCFGR_DRBS(0x18) // DMA recv buf 1536
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| GMAC_DCFGR_RXBMS(GMAC_DCFGR_RXBMS_FULL_Val) |
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GMAC_DCFGR_TXPBMS(1); // See #2487
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for (int i = 0; i < ETH_DESC_CNT; i++) { // Init RX descriptors
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s_rxdesc[i][0] = (uint32_t) s_rxbuf[i]; // Address of the data buffer
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s_rxdesc[i][1] = 0; // Clear status
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}
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s_rxdesc[ETH_DESC_CNT - 1][0] |= MG_BIT(1); // Last rx descriptor - wrap
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@ -154,7 +149,7 @@ static size_t mg_tcpip_driver_same54_tx(const void *buf, size_t len,
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} else {
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uint32_t status = len | MG_BIT(15); // Frame length, last chunk
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if (s_txno == ETH_DESC_CNT - 1) status |= MG_BIT(30); // wrap
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][1] = status;
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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@ -1,9 +1,5 @@
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#pragma once
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_SAME54) && MG_ENABLE_DRIVER_SAME54
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struct mg_tcpip_driver_same54_data {
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int mdc_cr;
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};
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#endif
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