diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 4f859c49..ca07cd76 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -219,6 +219,19 @@ jobs: run: sudo apt -y update; sudo apt -y install gcc-arm-none-eabi - if: ${{ env.GO == 1 }} run: make -C examples/stm32/nucleo-h563zi-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}} +# - if: ${{ env.GO == 1 }} +# WIP run: make -C examples/stm32/nucleo-h563zi-make-freertos-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}} + + test_rt1020: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + with: { fetch-depth: 3 } + - run: if ./test/match_changed_files.sh "^src|examples/nxp/rt1020.*-make-" ; then echo GO=1 >> $GITHUB_ENV ; fi + - if: ${{ env.GO == 1 }} + run: sudo apt -y update; sudo apt -y install gcc-arm-none-eabi + - if: ${{ env.GO == 1 }} + run: make -C examples/nxp/rt1020-evk-make-baremetal-builtin test VCON_API_KEY=${{secrets.VCON_API_KEY}} test_tm4c: runs-on: ubuntu-latest @@ -301,6 +314,7 @@ jobs: - path: nxp/nxp-lpcxpresso54608-lwip-freertos - path: nxp/nxp-lpcxpresso54618-lwip-freertos - path: nxp/nxp-lpcxpresso54628-lwip-freertos + - path: nxp/rt1020-evk-make-baremetal-builtin - path: nxp/nxp-twrk65f180m-lwip-freertos - path: nxp/nxp-twrkv58f220m-lwip-freertos - path: rp2040/pico-rmii @@ -314,7 +328,9 @@ jobs: - path: stm32/nucleo-f746zg-make-freertos-builtin - path: stm32/nucleo-f746zg-make-freertos-tcp - path: stm32/nucleo-f746zg-make-baremetal-builtin-rndis + - path: stm32/nucleo-g031-make-baremetal-builtin - path: stm32/nucleo-h563zi-make-baremetal-builtin + - path: stm32/nucleo-h563zi-make-freertos-builtin - path: stm32/nucleo-h743zi-make-baremetal-builtin - path: stm32/nucleo-h743zi-make-freertos-builtin - path: ti/ti-ek-tm4c1294xl-http-server diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile b/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile index 3807cff2..89a0216f 100644 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile +++ b/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile @@ -10,7 +10,7 @@ SOURCES += cmsis_mcu/devices/MIMXRT1021/gcc/startup_MIMXRT1021.S CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS # Make startup code work as expected # Mongoose-specific. See https://mongoose.ws/documentation/#build-options -SOURCES += mongoose.c #net.c packed_fs.c +SOURCES += mongoose.c CFLAGS += -DMG_ENABLE_TCPIP=1 -DMG_ARCH=MG_ARCH_NEWLIB -DMG_ENABLE_CUSTOM_MILLIS=1 CFLAGS += -DMG_ENABLE_CUSTOM_RANDOM=1 -DMG_ENABLE_PACKED_FS=1 -DMG_ENABLE_DRIVER_IMXRT1020=1 @@ -57,9 +57,9 @@ endif DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/4 update: firmware.bin curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$< - curl -su :$(VCON_API_KEY) https://dash.vcon.io/api/v3/devices/4/rpc/swd.exec -d '{"req":"init"}' - curl -su :$(VCON_API_KEY) https://dash.vcon.io/api/v3/devices/4/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1 wm,e000ed0c,5fa0004"}' - curl -su :$(VCON_API_KEY) https://dash.vcon.io/api/v3/devices/4/rpc/swd.exec -d '{"req":"init"}' + curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}' + curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1 wm,e000ed0c,5fa0004"}' + curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}' PC=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,4"}' | jq -r .resp[5:]` && \ SP=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,0"}' | jq -r .resp[5:]` && \ REQ="wm,e000ed08,0 wr,d,$$SP wr,f,$$PC" && \ diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h b/examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h index eb9dffa5..37c41f41 100644 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h +++ b/examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h @@ -281,8 +281,10 @@ static inline void ethernet_init(void) { NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler } -// Helper macro for MAC generation -#define GENERATE_LOCALLY_ADMINISTERED_MAC() \ - { 2, 0, 2, 5, 7, 91 } -// *((uint32_t *)(uintptr_t)&uid[0]) = OCOTP->CFG0; -// *((uint32_t *)(uintptr_t)&uid[4]) = OCOTP->CFG1; +// Helper macro for MAC generation, byte reads not allowed +#define GENERATE_LOCALLY_ADMINISTERED_MAC() \ + { \ + 2, OCOTP->CFG0 & 255, (OCOTP->CFG0 >> 10) & 255, \ + ((OCOTP->CFG0 >> 19) ^ (OCOTP->CFG1 >> 19)) & 255, \ + (OCOTP->CFG1 >> 10) & 255, OCOTP->CFG1 & 255 \ + } diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/main.c b/examples/nxp/rt1020-evk-make-baremetal-builtin/main.c index 9f60d034..0a245b2e 100644 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/main.c +++ b/examples/nxp/rt1020-evk-make-baremetal-builtin/main.c @@ -31,6 +31,29 @@ static void timer_fn(void *arg) { ifp->ndrop, ifp->nerr)); } +static void fn(struct mg_connection *c, int ev, void *ev_data, void *fn_data) { + struct mg_tcpip_if *ifp = (struct mg_tcpip_if *) fn_data; + if (ev == MG_EV_HTTP_MSG) { + struct mg_http_message *hm = (struct mg_http_message *) ev_data; + if (mg_http_match_uri(hm, "/api/hello")) { // Request to /api/hello + mg_http_reply(c, 200, "", "{%m:%u,%m:%u,%m:%u,%m:%u,%m:%u}\n", + MG_ESC("eth"), ifp->state, MG_ESC("frames_received"), + ifp->nrecv, MG_ESC("frames_sent"), ifp->nsent, + MG_ESC("frames_dropped"), ifp->ndrop, + MG_ESC("interface_errors"), ifp->nerr); + } else if (mg_http_match_uri(hm, "/")) { // Index page + mg_http_reply( + c, 200, "", "%s", + "" + "

Welcome to Mongoose

" + "See /api/hello for REST example" + ""); + } else { // All other URIs + mg_http_reply(c, 404, "", "Not Found\n"); + } + } +} + int main(void) { gpio_output(LED); // Setup blue LED uart_init(UART_DEBUG, 115200); // Initialise debug printf @@ -42,7 +65,7 @@ int main(void) { mg_log_set(MG_LL_DEBUG); // Set log level // Initialise Mongoose network stack - struct mg_tcpip_driver_imxrt1020_data driver_data = {.mdc_cr = 4}; + struct mg_tcpip_driver_imxrt1020_data driver_data = {.mdc_cr = 24}; struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(), // Uncomment below for static configuration: // .ip = mg_htonl(MG_U32(192, 168, 0, 223)), @@ -59,7 +82,7 @@ int main(void) { } MG_INFO(("Initialising application...")); -// web_init(&mgr); + mg_http_listen(&mgr, "http://0.0.0.0:80", fn, &mif); MG_INFO(("Starting event loop")); for (;;) { diff --git a/mongoose.c b/mongoose.c index 0e20ccda..0a6fe05a 100644 --- a/mongoose.c +++ b/mongoose.c @@ -8391,16 +8391,30 @@ size_t mg_ws_wrap(struct mg_connection *c, size_t len, int op) { #endif -/* - * Todo - * This driver doesn't support 10M line autoconfiguration yet. - * Packets aren't sent if the link negociated 10M line. - * todo: MAC back auto reconfiguration. - */ - -#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT1020) +#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT1020) && \ + MG_ENABLE_DRIVER_IMXRT1020 struct imx_rt1020_enet { -volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3], ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR, RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2, RESERVED8, RXIC0, RXIC1, RXIC2, RESERVED9[3], IAUR, IALR, GAUR, GALR, RESERVED10[7], TFWR, RESERVED11[14], RDSR, TDSR, MRBR[2], RSFL, RSEM, RAEM, RAFL, TSEM, TAEM, TAFL, TIPG, FTRL, RESERVED12[3], TACC, RACC, RESERVED13[15], RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2048, RMON_T_GTE2048, RMON_T_OCTETS, IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, IEEE_T_FDXFC, IEEE_T_OCTETS_OK, RESERVED14[3], RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, RESERVED15, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, RMON_R_GTE2048, RMON_R_OCTETS, IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, IEEE_R_FDXFC, IEEE_R_OCTETS_OK, RESERVED16[71], ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP, RESERVED17[122], TGSR, TCSR0, TCCR0, TCSR1, TCCR1, TCSR2, TCCR2, TCSR3; + volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3], + ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR, + RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2, + RESERVED8, RXIC0, RXIC1, RXIC2, RESERVED9[3], IAUR, IALR, GAUR, GALR, + RESERVED10[7], TFWR, RESERVED11[14], RDSR, TDSR, MRBR[2], RSFL, RSEM, + RAEM, RAFL, TSEM, TAEM, TAFL, TIPG, FTRL, RESERVED12[3], TACC, RACC, + RESERVED13[15], RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, + RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, + RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, + RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2048, RMON_T_GTE2048, + RMON_T_OCTETS, IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, + IEEE_T_DEF, IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, + IEEE_T_SQE, IEEE_T_FDXFC, IEEE_T_OCTETS_OK, RESERVED14[3], RMON_R_PACKETS, + RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, RMON_R_UNDERSIZE, + RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, RESERVED15, RMON_R_P64, + RMON_R_P65TO127, RMON_R_P128TO255, RMON_R_P256TO511, RMON_R_P512TO1023, + RMON_R_P1024TO2047, RMON_R_GTE2048, RMON_R_OCTETS, IEEE_R_DROP, + IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, IEEE_R_FDXFC, + IEEE_R_OCTETS_OK, RESERVED16[71], ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, + ATSTMP, RESERVED17[122], TGSR, TCSR0, TCCR0, TCSR1, TCCR1, TCSR2, TCCR2, + TCSR3; }; #undef ENET @@ -8409,249 +8423,159 @@ volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3], ECR #undef BIT #define BIT(x) ((uint32_t) 1 << (x)) -#define ENET_RXBUFF_SIZE 1536 // 1522 Buffer must be 64bits aligned -#define ENET_TXBUFF_SIZE 1536 // 1522 hence set to 0x600 (1536) -#define ENET_RXBD_NUM (4) -#define ENET_TXBD_NUM (4) +// Max frame size, every buffer must be 64-bit aligned (1536 = 0x600) +#define ETH_PKT_SIZE 1536 +#define ETH_DESC_CNT 4 // Descriptors count -const uint32_t EIMR_RX_ERR = 0x2400000; // Intr mask RXF+EBERR +typedef struct { + uint16_t length; // Data length + uint16_t control; // Control and status + uint32_t *buffer; // Data ptr +} enet_bd_t; -void ETH_IRQHandler(void); -static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp); -static void wait_phy_complete(void); -static struct mg_tcpip_if *s_ifp; // MIP interface - -static size_t mg_tcpip_driver_imxrt1020_tx(const void *, size_t , struct mg_tcpip_if *); -static bool mg_tcpip_driver_imxrt1020_up(struct mg_tcpip_if *ifp); - -enum { IMXRT1020_PHY_ADDR = 0x02, IMXRT1020_PHY_BCR = 0, IMXRT1020_PHY_BSR = 1 }; // PHY constants - -void delay(uint32_t); -void delay (uint32_t di) { - volatile int dno = 0; // Prevent optimization - for (uint32_t i = 0; i < di; i++) - for (int j=0; j<20; j++) // PLLx20 (500 MHz/24MHz) - dno++; -} - -static void wait_phy_complete(void) { - delay(0x00010000); - const uint32_t delay_max = 0x00100000; - uint32_t delay_cnt = 0; - while (!(ENET->EIR & BIT(23)) && (delay_cnt < delay_max)) - {delay_cnt++;} - ENET->EIR |= BIT(23); // MII interrupt clear -} - -static uint32_t imxrt1020_eth_read_phy(uint8_t addr, uint8_t reg) { - ENET->EIR |= BIT(23); // MII interrupt clear - uint32_t mask_phy_adr_reg = 0x1f; // 0b00011111: Ensure we write 5 bits (Phy address & register) - uint32_t phy_transaction = 0x00; - phy_transaction = (0x1 << 30) \ - | (0x2 << 28) \ - | ((uint32_t)(addr & mask_phy_adr_reg) << 23) \ - | ((uint32_t)(reg & mask_phy_adr_reg) << 18) \ - | (0x2 << 16); - - ENET->MMFR = phy_transaction; - wait_phy_complete(); - - return (ENET->MMFR & 0x0000ffff); -} - -static void imxrt1020_eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) { - ENET->EIR |= BIT(23); // MII interrupt clear - uint8_t mask_phy_adr_reg = 0x1f; // 0b00011111: Ensure we write 5 bits (Phy address & register) - uint32_t mask_phy_data = 0x0000ffff; // Ensure we write 16 bits (data) - addr &= mask_phy_adr_reg; - reg &= mask_phy_adr_reg; - val &= mask_phy_data; - uint32_t phy_transaction = 0x00; - phy_transaction = (uint32_t)(0x1 << 30) \ - | (uint32_t)(0x1 << 28) \ - | (uint32_t)(addr << 23) \ - | (uint32_t)(reg << 18) \ - | (uint32_t)(0x2 << 16) \ - | (uint32_t)(val); - ENET->MMFR = phy_transaction; - wait_phy_complete(); -} - -// FEC RX/TX descriptors (Enhanced descriptor not enabled) -// Descriptor buffer structure, little endian - -typedef struct enet_bd_struct_def -{ - uint16_t length; // Data length - uint16_t control; // Control and status - uint32_t *buffer; // Data ptr -} enet_bd_struct_t; - -// Descriptor and buffer globals, in non-cached area, 64 bits aligned. // TODO(): handle these in a portable compiler-independent CMSIS-friendly way -/*__attribute__((section("NonCacheable,\"aw\",%nobits @")))*/ enet_bd_struct_t rx_buffer_descriptor[(ENET_RXBD_NUM)] __attribute__((aligned((64U)))); -/*__attribute__((section("NonCacheable,\"aw\",%nobits @")))*/ enet_bd_struct_t tx_buffer_descriptor[(ENET_TXBD_NUM)] __attribute__((aligned((64U)))); +// Descriptors: in non-cached area (TODO(scaprile)), 64-bit aligned +enet_bd_t s_rxdesc[ETH_DESC_CNT] __attribute__((aligned((64U)))); +enet_bd_t s_txdesc[ETH_DESC_CNT] __attribute__((aligned((64U)))); +// Buffers: 64-bit aligned +uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] __attribute__((aligned((64U)))); +uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] __attribute__((aligned((64U)))); -uint8_t rx_data_buffer[(ENET_RXBD_NUM)][((unsigned int)(((ENET_RXBUFF_SIZE)) + (((64U))-1U)) & (unsigned int)(~(unsigned int)(((64U))-1U)))] __attribute__((aligned((64U)))); -uint8_t tx_data_buffer[(ENET_TXBD_NUM)][((unsigned int)(((ENET_TXBUFF_SIZE)) + (((64U))-1U)) & (unsigned int)(~(unsigned int)(((64U))-1U)))] __attribute__((aligned((64U)))); +static struct mg_tcpip_if *s_ifp; // MIP interface -// Initialise driver imx_rt1020 +enum { PHY_ADDR = 2, PHY_BCR = 0, PHY_BSR = 1, PHY_PC1R = 30, PHY_PC2R = 31 }; -// static bool mg_tcpip_driver_imxrt1020_init(uint8_t *mac, void *data) { // VO +static uint32_t eth_read_phy(uint8_t addr, uint8_t reg) { + ENET->EIR |= BIT(23); // MII interrupt clear + ENET->MMFR = (1 << 30) | (2 << 28) | (addr << 23) | (reg << 18) | (2 << 16); + while ((ENET->EIR & BIT(23)) == 0) (void) 0; + return ENET->MMFR & 0xffff; +} + +static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) { + ENET->EIR |= BIT(23); // MII interrupt clear + ENET->MMFR = + (1 << 30) | (1 << 28) | (addr << 23) | (reg << 18) | (2 << 16) | val; + while ((ENET->EIR & BIT(23)) == 0) (void) 0; +} + +// MDC clock is generated from IPS Bus clock (ipg_clk); as per 802.3, +// it must not exceed 2.5MHz +// The PHY receives the PLL6-generated 50MHz clock static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) { - -// TODO(scaprile): struct mg_tcpip_driver_imxrt1020_data *d = (struct mg_tcpip_driver_imxrt1020_data *) ifp->driver_data; + struct mg_tcpip_driver_imxrt1020_data *d = + (struct mg_tcpip_driver_imxrt1020_data *) ifp->driver_data; s_ifp = ifp; - // ENET Reset, wait complete - ENET->ECR |= BIT(0); - while((ENET->ECR & BIT(0)) != 0) {} - - // Re-latches the pin strapping pin values - ENET->ECR |= BIT(0); - while((ENET->ECR & BIT(0)) != 0) {} - - // Setup MII/RMII MDC clock divider (<= 2.5MHz). - ENET->MSCR = 0x130; // HOLDTIME 2 clk, Preamble enable, MDC MII_Speed Div 0x30 - imxrt1020_eth_write_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BCR, 0x8000); // PHY W @0x00 D=0x8000 Soft reset - while (imxrt1020_eth_read_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BSR) & BIT(15)) {delay(0x5000);} // Wait finished poll 10ms - - // PHY: Start Link - { - imxrt1020_eth_write_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BCR, 0x1200); // PHY W @0x00 D=0x1200 Autonego enable + start - imxrt1020_eth_write_phy(IMXRT1020_PHY_ADDR, 0x1f, 0x8180); // PHY W @0x1f D=0x8180 Ref clock 50 MHz at XI input - - uint32_t bcr = imxrt1020_eth_read_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BCR); - bcr &= ~BIT(10); // Isolation -> Normal - imxrt1020_eth_write_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BCR, bcr); + // Init RX descriptors + for (int i = 0; i < ETH_DESC_CNT; i++) { + s_rxdesc[i].control = BIT(15); // Own (E) + s_rxdesc[i].buffer = (uint32_t *) s_rxbuf[i]; // Point to data buffer } + s_rxdesc[ETH_DESC_CNT - 1].control |= BIT(13); // Wrap last descriptor - // Disable ENET - ENET->ECR = 0x0; // Disable before configuration - - // Configure ENET - ENET->RCR = 0x05ee0104; // #CRCFWD=0 (CRC kept in frame) + RMII + MII Enable - //ENET->RCR |= BIT(3); // Receive all - - ENET->TCR = BIT(8) | BIT(2); // Addins (MAC address from PAUR+PALR) + Full duplex enable - //ENET->TFWR = BIT(8); // Store And Forward Enable, 64 bytes (minimize tx latency) - - // Configure descriptors and buffers - // RX - for (int i = 0; i < ENET_RXBD_NUM; i++) { - // Wrap last descriptor buffer ptr - rx_buffer_descriptor[i].control = (BIT(15) | ((i<(ENET_RXBD_NUM-1))?0:BIT(13))); // E+(W*) - rx_buffer_descriptor[i].buffer = (uint32_t *)rx_data_buffer[i]; + // Init TX descriptors + for (int i = 0; i < ETH_DESC_CNT; i++) { + s_txdesc[i].control = BIT(10); // Own (TC) + s_txdesc[i].buffer = (uint32_t *) s_txbuf[i]; } + s_txdesc[ETH_DESC_CNT - 1].control |= BIT(13); // Wrap last descriptor - // TX - for (int i = 0; i < ENET_TXBD_NUM; i++) { - // Wrap last descriptor buffer ptr - tx_buffer_descriptor[i].control = ((i<(ENET_RXBD_NUM-1))?0:BIT(13)) | BIT(10); // (W*)+TC - tx_buffer_descriptor[i].buffer = (uint32_t *)tx_data_buffer[i]; - } + ENET->ECR = BIT(0); // Software reset, disable + while ((ENET->ECR & BIT(0))) (void) 0; // Wait until done - // Continue ENET configuration - ENET->RDSR = (uint32_t)(uintptr_t)rx_buffer_descriptor; - ENET->TDSR = (uint32_t)(uintptr_t)tx_buffer_descriptor; - ENET->MRBR[0] = ENET_RXBUFF_SIZE; // Same size for RX/TX buffers + // Set MDC clock divider. If user told us the value, use it. + // TODO(): Otherwise, guess (currently assuming max freq) + int cr = (d == NULL || d->mdc_cr < 0) ? 24 : d->mdc_cr; + ENET->MSCR = (1 << 8) | ((cr & 0x3f) << 1); // HOLDTIME 2 clks + eth_write_phy(PHY_ADDR, PHY_BCR, BIT(15)); // Reset PHY + eth_write_phy(PHY_ADDR, PHY_BCR, BIT(12)); // Set autonegotiation + // PHY: Enable 50 MHz external ref clock at XI (preserve defaults) + eth_write_phy(PHY_ADDR, PHY_PC2R, BIT(15) | BIT(8) | BIT(7)); + // Select RMII mode, 100M, keep CRC, set max rx length, disable loop + ENET->RCR = (1518 << 16) | BIT(8) | BIT(2); + // ENET->RCR |= BIT(3); // Receive all + ENET->TCR = BIT(2); // Full-duplex + ENET->RDSR = (uint32_t) (uintptr_t) s_rxdesc; + ENET->TDSR = (uint32_t) (uintptr_t) s_txdesc; + ENET->MRBR[0] = ETH_PKT_SIZE; // Same size for RX/TX buffers // MAC address filtering (bytes in reversed order) ENET->PAUR = ((uint32_t) ifp->mac[4] << 24U) | (uint32_t) ifp->mac[5] << 16U; - ENET->PALR = (uint32_t) (ifp->mac[0] << 24U) | ((uint32_t) ifp->mac[1] << 16U) | - ((uint32_t) ifp->mac[2] << 8U) | ifp->mac[3]; - - // Init Hash tables (mac filtering) - ENET->IAUR = 0; // Unicast - ENET->IALR = 0; - ENET->GAUR = 0; // Multicast - ENET->GALR = 0; - - // Set ENET Online - ENET->ECR |= BIT(8); // ENET Set Little-endian + (FEC buffer desc.) - ENET->ECR |= BIT(1); // Enable - - // Set interrupt mask - ENET->EIMR = EIMR_RX_ERR; - - // RX Descriptor activation - ENET->RDAR = BIT(24); // Activate Receive Descriptor + ENET->PALR = (uint32_t) (ifp->mac[0] << 24U) | + ((uint32_t) ifp->mac[1] << 16U) | + ((uint32_t) ifp->mac[2] << 8U) | ifp->mac[3]; + ENET->ECR = BIT(8) | BIT(1); // Little-endian CPU, Enable + ENET->EIMR = BIT(25); // Set interrupt mask + ENET->RDAR = BIT(24); // Receive Descriptors have changed return true; } // Transmit frame -static uint32_t s_rt1020_txno; +static uint32_t s_txno; -static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len, struct mg_tcpip_if *ifp) { - - if (len > sizeof(tx_data_buffer[ENET_TXBD_NUM])) { - // MG_ERROR(("Frame too big, %ld", (long) len)); - len = 0; // Frame is too big - } else if ((tx_buffer_descriptor[s_rt1020_txno].control & BIT(15))) { - MG_ERROR(("No free descriptors")); - // printf("D0 %lx SR %lx\n", (long) s_txdesc[0][0], (long) ETH->DMASR); - len = 0; // All descriptors are busy, fail +static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len, + struct mg_tcpip_if *ifp) { + if (len > sizeof(s_txbuf[ETH_DESC_CNT])) { + MG_ERROR(("Frame too big, %ld", (long) len)); + len = 0; // fail + } else if ((s_txdesc[s_txno].control & BIT(15))) { + ifp->nerr++; + MG_ERROR(("No descriptors available")); + len = 0; // fail } else { - memcpy(tx_data_buffer[s_rt1020_txno], buf, len); // Copy data - tx_buffer_descriptor[s_rt1020_txno].length = (uint16_t) len; // Set data len - tx_buffer_descriptor[s_rt1020_txno].control |= (uint16_t)(BIT(10)); // TC (transmit CRC) - // tx_buffer_descriptor[s_rt1020_txno].control &= (uint16_t)(BIT(14) | BIT(12)); // Own doesn't affect HW - tx_buffer_descriptor[s_rt1020_txno].control |= (uint16_t)(BIT(15) | BIT(11)); // R+L (ready+last) - ENET->TDAR = BIT(24); // Descriptor updated. Hand over to DMA. - // INFO - // Relevant Descriptor bits: 15(R) Ready - // 11(L) last in frame - // 10(TC) transmis CRC - // __DSB(); // ARM errata 838869 Cortex-M4, M4F, M7, M7F: "store immediate overlapping - // exception" return might vector to incorrect interrupt. - if (++s_rt1020_txno >= ENET_TXBD_NUM) s_rt1020_txno = 0; + memcpy(s_txbuf[s_txno], buf, len); // Copy data + s_txdesc[s_txno].length = (uint16_t) len; // Set data len + // Table 37-34, R, L, TC (Ready, last, transmit CRC after frame + s_txdesc[s_txno].control |= (uint16_t) (BIT(15) | BIT(11) | BIT(10)); + ENET->TDAR = BIT(24); // Descriptor ring updated + if (++s_txno >= ETH_DESC_CNT) s_txno = 0; } (void) ifp; return len; } -// IRQ (RX) -static uint32_t s_rt1020_rxno; - -void ENET_IRQHandler(void) { - ENET->EIMR = 0; // Mask interrupts. - uint32_t eir = ENET->EIR; // Read EIR - ENET->EIR = 0xffffffff; // Clear interrupts - - if (eir & EIMR_RX_ERR) // Global mask used - { - if (rx_buffer_descriptor[s_rt1020_rxno].control & BIT(15)) { - ENET->EIMR = EIMR_RX_ERR; // Enable interrupts - return; // Empty? -> exit. - } - // Read inframes - else { // Frame received, loop - for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever - if (rx_buffer_descriptor[s_rt1020_rxno].control & BIT(15)) break; // exit when done - // Process if CRC OK and frame not truncated - if (!(rx_buffer_descriptor[s_rt1020_rxno].control & (BIT(2) | BIT(0)))) { - uint32_t len = (rx_buffer_descriptor[s_rt1020_rxno].length); - mg_tcpip_qwrite(rx_buffer_descriptor[s_rt1020_rxno].buffer, len > 4 ? len - 4 : len, s_ifp); - } - rx_buffer_descriptor[s_rt1020_rxno].control |= BIT(15); // Inform DMA RX is empty - if (++s_rt1020_rxno >= ENET_RXBD_NUM) s_rt1020_rxno = 0; - } - } - } - ENET->EIMR = EIMR_RX_ERR; // Enable interrupts -} - -// Up/down status static bool mg_tcpip_driver_imxrt1020_up(struct mg_tcpip_if *ifp) { - uint32_t bsr = imxrt1020_eth_read_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BSR); - (void) ifp; - return bsr & BIT(2) ? 1 : 0; + uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR); + bool up = bsr & BIT(2) ? 1 : 0; + if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up + uint32_t pc1r = eth_read_phy(PHY_ADDR, PHY_PC1R); + uint32_t tcr = ENET->TCR |= BIT(2); // Full-duplex + uint32_t rcr = ENET->RCR &= ~BIT(9); // 100M + if ((pc1r & 3) == 1) rcr |= BIT(9); // 10M + if ((pc1r & BIT(2)) == 0) tcr &= ~BIT(2); // Half-duplex + ENET->TCR = tcr; // IRQ handler does not fiddle with these registers + ENET->RCR = rcr; + MG_DEBUG(("Link is %uM %s-duplex", rcr & BIT(9) ? 10 : 100, + tcr & BIT(2) ? "full" : "half")); + } + return up; +} + +void ENET_IRQHandler(void); +static uint32_t s_rxno; +void ENET_IRQHandler(void) { + ENET->EIR = BIT(25); // Ack IRQ + // Frame received, loop + for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever + if (s_rxdesc[s_rxno].control & BIT(15)) break; // exit when done + // skip partial/errored frames (Table 37-32) + if ((s_rxdesc[s_rxno].control & BIT(11)) && + !(s_rxdesc[s_rxno].control & + (BIT(5) | BIT(4) | BIT(2) | BIT(1) | BIT(0)))) { + uint32_t len = (s_rxdesc[s_rxno].length); + mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp); + } + s_rxdesc[s_rxno].control |= BIT(15); + if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0; + } + ENET->RDAR = BIT(24); // Receive Descriptors have changed + // If b24 == 0, descriptors were exhausted and probably frames were dropped } -// API struct mg_tcpip_driver mg_tcpip_driver_imxrt1020 = { - mg_tcpip_driver_imxrt1020_init, mg_tcpip_driver_imxrt1020_tx, NULL, - mg_tcpip_driver_imxrt1020_up}; + mg_tcpip_driver_imxrt1020_init, mg_tcpip_driver_imxrt1020_tx, NULL, + mg_tcpip_driver_imxrt1020_up}; #endif diff --git a/mongoose.h b/mongoose.h index ab251ffb..ff6a87d7 100644 --- a/mongoose.h +++ b/mongoose.h @@ -1800,15 +1800,16 @@ struct mg_tcpip_spi { struct mg_tcpip_driver_imxrt1020_data { // MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk), // must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz - // ipg_clk MSCR mdc_cr VALUE - // ------------------------------------- - // -1 <-- tell driver to guess the value - // 25 MHz 0x04 0 - // 33 MHz 0x06 1 - // 40 MHz 0x07 2 - // 50 MHz 0x09 3 - // 66 MHz 0x0D 4 <-- value for iMXRT1020-EVK at max freq. - int mdc_cr; // Valid values: -1, 0, 1, 2, 3, 4 + // 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1)) + // ipg_clk mdc_cr VALUE + // -------------------------- + // -1 <-- TODO() tell driver to guess the value + // 25 MHz 4 + // 33 MHz 6 + // 40 MHz 7 + // 50 MHz 9 + // 66 MHz 13 + int mdc_cr; // Valid values: -1 to 63 }; diff --git a/src/drivers/rt1020.c b/src/drivers/rt1020.c index 363fd912..c96fb98b 100644 --- a/src/drivers/rt1020.c +++ b/src/drivers/rt1020.c @@ -1,15 +1,29 @@ #include "tcpip.h" -/* - * Todo - * This driver doesn't support 10M line autoconfiguration yet. - * Packets aren't sent if the link negociated 10M line. - * todo: MAC back auto reconfiguration. - */ - -#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT1020) +#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT1020) && \ + MG_ENABLE_DRIVER_IMXRT1020 struct imx_rt1020_enet { -volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3], ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR, RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2, RESERVED8, RXIC0, RXIC1, RXIC2, RESERVED9[3], IAUR, IALR, GAUR, GALR, RESERVED10[7], TFWR, RESERVED11[14], RDSR, TDSR, MRBR[2], RSFL, RSEM, RAEM, RAFL, TSEM, TAEM, TAFL, TIPG, FTRL, RESERVED12[3], TACC, RACC, RESERVED13[15], RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2048, RMON_T_GTE2048, RMON_T_OCTETS, IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, IEEE_T_FDXFC, IEEE_T_OCTETS_OK, RESERVED14[3], RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, RESERVED15, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, RMON_R_GTE2048, RMON_R_OCTETS, IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, IEEE_R_FDXFC, IEEE_R_OCTETS_OK, RESERVED16[71], ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP, RESERVED17[122], TGSR, TCSR0, TCCR0, TCSR1, TCCR1, TCSR2, TCCR2, TCSR3; + volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3], + ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR, + RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2, + RESERVED8, RXIC0, RXIC1, RXIC2, RESERVED9[3], IAUR, IALR, GAUR, GALR, + RESERVED10[7], TFWR, RESERVED11[14], RDSR, TDSR, MRBR[2], RSFL, RSEM, + RAEM, RAFL, TSEM, TAEM, TAFL, TIPG, FTRL, RESERVED12[3], TACC, RACC, + RESERVED13[15], RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, + RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, + RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, + RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2048, RMON_T_GTE2048, + RMON_T_OCTETS, IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, + IEEE_T_DEF, IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, + IEEE_T_SQE, IEEE_T_FDXFC, IEEE_T_OCTETS_OK, RESERVED14[3], RMON_R_PACKETS, + RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, RMON_R_UNDERSIZE, + RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, RESERVED15, RMON_R_P64, + RMON_R_P65TO127, RMON_R_P128TO255, RMON_R_P256TO511, RMON_R_P512TO1023, + RMON_R_P1024TO2047, RMON_R_GTE2048, RMON_R_OCTETS, IEEE_R_DROP, + IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, IEEE_R_FDXFC, + IEEE_R_OCTETS_OK, RESERVED16[71], ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, + ATSTMP, RESERVED17[122], TGSR, TCSR0, TCCR0, TCSR1, TCCR1, TCSR2, TCCR2, + TCSR3; }; #undef ENET @@ -18,248 +32,158 @@ volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3], ECR #undef BIT #define BIT(x) ((uint32_t) 1 << (x)) -#define ENET_RXBUFF_SIZE 1536 // 1522 Buffer must be 64bits aligned -#define ENET_TXBUFF_SIZE 1536 // 1522 hence set to 0x600 (1536) -#define ENET_RXBD_NUM (4) -#define ENET_TXBD_NUM (4) +// Max frame size, every buffer must be 64-bit aligned (1536 = 0x600) +#define ETH_PKT_SIZE 1536 +#define ETH_DESC_CNT 4 // Descriptors count -const uint32_t EIMR_RX_ERR = 0x2400000; // Intr mask RXF+EBERR +typedef struct { + uint16_t length; // Data length + uint16_t control; // Control and status + uint32_t *buffer; // Data ptr +} enet_bd_t; -void ETH_IRQHandler(void); -static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp); -static void wait_phy_complete(void); -static struct mg_tcpip_if *s_ifp; // MIP interface - -static size_t mg_tcpip_driver_imxrt1020_tx(const void *, size_t , struct mg_tcpip_if *); -static bool mg_tcpip_driver_imxrt1020_up(struct mg_tcpip_if *ifp); - -enum { IMXRT1020_PHY_ADDR = 0x02, IMXRT1020_PHY_BCR = 0, IMXRT1020_PHY_BSR = 1 }; // PHY constants - -void delay(uint32_t); -void delay (uint32_t di) { - volatile int dno = 0; // Prevent optimization - for (uint32_t i = 0; i < di; i++) - for (int j=0; j<20; j++) // PLLx20 (500 MHz/24MHz) - dno++; -} - -static void wait_phy_complete(void) { - delay(0x00010000); - const uint32_t delay_max = 0x00100000; - uint32_t delay_cnt = 0; - while (!(ENET->EIR & BIT(23)) && (delay_cnt < delay_max)) - {delay_cnt++;} - ENET->EIR |= BIT(23); // MII interrupt clear -} - -static uint32_t imxrt1020_eth_read_phy(uint8_t addr, uint8_t reg) { - ENET->EIR |= BIT(23); // MII interrupt clear - uint32_t mask_phy_adr_reg = 0x1f; // 0b00011111: Ensure we write 5 bits (Phy address & register) - uint32_t phy_transaction = 0x00; - phy_transaction = (0x1 << 30) \ - | (0x2 << 28) \ - | ((uint32_t)(addr & mask_phy_adr_reg) << 23) \ - | ((uint32_t)(reg & mask_phy_adr_reg) << 18) \ - | (0x2 << 16); - - ENET->MMFR = phy_transaction; - wait_phy_complete(); - - return (ENET->MMFR & 0x0000ffff); -} - -static void imxrt1020_eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) { - ENET->EIR |= BIT(23); // MII interrupt clear - uint8_t mask_phy_adr_reg = 0x1f; // 0b00011111: Ensure we write 5 bits (Phy address & register) - uint32_t mask_phy_data = 0x0000ffff; // Ensure we write 16 bits (data) - addr &= mask_phy_adr_reg; - reg &= mask_phy_adr_reg; - val &= mask_phy_data; - uint32_t phy_transaction = 0x00; - phy_transaction = (uint32_t)(0x1 << 30) \ - | (uint32_t)(0x1 << 28) \ - | (uint32_t)(addr << 23) \ - | (uint32_t)(reg << 18) \ - | (uint32_t)(0x2 << 16) \ - | (uint32_t)(val); - ENET->MMFR = phy_transaction; - wait_phy_complete(); -} - -// FEC RX/TX descriptors (Enhanced descriptor not enabled) -// Descriptor buffer structure, little endian - -typedef struct enet_bd_struct_def -{ - uint16_t length; // Data length - uint16_t control; // Control and status - uint32_t *buffer; // Data ptr -} enet_bd_struct_t; - -// Descriptor and buffer globals, in non-cached area, 64 bits aligned. // TODO(): handle these in a portable compiler-independent CMSIS-friendly way -/*__attribute__((section("NonCacheable,\"aw\",%nobits @")))*/ enet_bd_struct_t rx_buffer_descriptor[(ENET_RXBD_NUM)] __attribute__((aligned((64U)))); -/*__attribute__((section("NonCacheable,\"aw\",%nobits @")))*/ enet_bd_struct_t tx_buffer_descriptor[(ENET_TXBD_NUM)] __attribute__((aligned((64U)))); +// Descriptors: in non-cached area (TODO(scaprile)), 64-bit aligned +enet_bd_t s_rxdesc[ETH_DESC_CNT] __attribute__((aligned((64U)))); +enet_bd_t s_txdesc[ETH_DESC_CNT] __attribute__((aligned((64U)))); +// Buffers: 64-bit aligned +uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] __attribute__((aligned((64U)))); +uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] __attribute__((aligned((64U)))); -uint8_t rx_data_buffer[(ENET_RXBD_NUM)][((unsigned int)(((ENET_RXBUFF_SIZE)) + (((64U))-1U)) & (unsigned int)(~(unsigned int)(((64U))-1U)))] __attribute__((aligned((64U)))); -uint8_t tx_data_buffer[(ENET_TXBD_NUM)][((unsigned int)(((ENET_TXBUFF_SIZE)) + (((64U))-1U)) & (unsigned int)(~(unsigned int)(((64U))-1U)))] __attribute__((aligned((64U)))); +static struct mg_tcpip_if *s_ifp; // MIP interface -// Initialise driver imx_rt1020 +enum { PHY_ADDR = 2, PHY_BCR = 0, PHY_BSR = 1, PHY_PC1R = 30, PHY_PC2R = 31 }; -// static bool mg_tcpip_driver_imxrt1020_init(uint8_t *mac, void *data) { // VO +static uint32_t eth_read_phy(uint8_t addr, uint8_t reg) { + ENET->EIR |= BIT(23); // MII interrupt clear + ENET->MMFR = (1 << 30) | (2 << 28) | (addr << 23) | (reg << 18) | (2 << 16); + while ((ENET->EIR & BIT(23)) == 0) (void) 0; + return ENET->MMFR & 0xffff; +} + +static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) { + ENET->EIR |= BIT(23); // MII interrupt clear + ENET->MMFR = + (1 << 30) | (1 << 28) | (addr << 23) | (reg << 18) | (2 << 16) | val; + while ((ENET->EIR & BIT(23)) == 0) (void) 0; +} + +// MDC clock is generated from IPS Bus clock (ipg_clk); as per 802.3, +// it must not exceed 2.5MHz +// The PHY receives the PLL6-generated 50MHz clock static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) { - -// TODO(scaprile): struct mg_tcpip_driver_imxrt1020_data *d = (struct mg_tcpip_driver_imxrt1020_data *) ifp->driver_data; + struct mg_tcpip_driver_imxrt1020_data *d = + (struct mg_tcpip_driver_imxrt1020_data *) ifp->driver_data; s_ifp = ifp; - // ENET Reset, wait complete - ENET->ECR |= BIT(0); - while((ENET->ECR & BIT(0)) != 0) {} - - // Re-latches the pin strapping pin values - ENET->ECR |= BIT(0); - while((ENET->ECR & BIT(0)) != 0) {} - - // Setup MII/RMII MDC clock divider (<= 2.5MHz). - ENET->MSCR = 0x130; // HOLDTIME 2 clk, Preamble enable, MDC MII_Speed Div 0x30 - imxrt1020_eth_write_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BCR, 0x8000); // PHY W @0x00 D=0x8000 Soft reset - while (imxrt1020_eth_read_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BSR) & BIT(15)) {delay(0x5000);} // Wait finished poll 10ms - - // PHY: Start Link - { - imxrt1020_eth_write_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BCR, 0x1200); // PHY W @0x00 D=0x1200 Autonego enable + start - imxrt1020_eth_write_phy(IMXRT1020_PHY_ADDR, 0x1f, 0x8180); // PHY W @0x1f D=0x8180 Ref clock 50 MHz at XI input - - uint32_t bcr = imxrt1020_eth_read_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BCR); - bcr &= ~BIT(10); // Isolation -> Normal - imxrt1020_eth_write_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BCR, bcr); + // Init RX descriptors + for (int i = 0; i < ETH_DESC_CNT; i++) { + s_rxdesc[i].control = BIT(15); // Own (E) + s_rxdesc[i].buffer = (uint32_t *) s_rxbuf[i]; // Point to data buffer } + s_rxdesc[ETH_DESC_CNT - 1].control |= BIT(13); // Wrap last descriptor - // Disable ENET - ENET->ECR = 0x0; // Disable before configuration - - // Configure ENET - ENET->RCR = 0x05ee0104; // #CRCFWD=0 (CRC kept in frame) + RMII + MII Enable - //ENET->RCR |= BIT(3); // Receive all - - ENET->TCR = BIT(8) | BIT(2); // Addins (MAC address from PAUR+PALR) + Full duplex enable - //ENET->TFWR = BIT(8); // Store And Forward Enable, 64 bytes (minimize tx latency) - - // Configure descriptors and buffers - // RX - for (int i = 0; i < ENET_RXBD_NUM; i++) { - // Wrap last descriptor buffer ptr - rx_buffer_descriptor[i].control = (BIT(15) | ((i<(ENET_RXBD_NUM-1))?0:BIT(13))); // E+(W*) - rx_buffer_descriptor[i].buffer = (uint32_t *)rx_data_buffer[i]; + // Init TX descriptors + for (int i = 0; i < ETH_DESC_CNT; i++) { + s_txdesc[i].control = BIT(10); // Own (TC) + s_txdesc[i].buffer = (uint32_t *) s_txbuf[i]; } + s_txdesc[ETH_DESC_CNT - 1].control |= BIT(13); // Wrap last descriptor - // TX - for (int i = 0; i < ENET_TXBD_NUM; i++) { - // Wrap last descriptor buffer ptr - tx_buffer_descriptor[i].control = ((i<(ENET_RXBD_NUM-1))?0:BIT(13)) | BIT(10); // (W*)+TC - tx_buffer_descriptor[i].buffer = (uint32_t *)tx_data_buffer[i]; - } + ENET->ECR = BIT(0); // Software reset, disable + while ((ENET->ECR & BIT(0))) (void) 0; // Wait until done - // Continue ENET configuration - ENET->RDSR = (uint32_t)(uintptr_t)rx_buffer_descriptor; - ENET->TDSR = (uint32_t)(uintptr_t)tx_buffer_descriptor; - ENET->MRBR[0] = ENET_RXBUFF_SIZE; // Same size for RX/TX buffers + // Set MDC clock divider. If user told us the value, use it. + // TODO(): Otherwise, guess (currently assuming max freq) + int cr = (d == NULL || d->mdc_cr < 0) ? 24 : d->mdc_cr; + ENET->MSCR = (1 << 8) | ((cr & 0x3f) << 1); // HOLDTIME 2 clks + eth_write_phy(PHY_ADDR, PHY_BCR, BIT(15)); // Reset PHY + eth_write_phy(PHY_ADDR, PHY_BCR, BIT(12)); // Set autonegotiation + // PHY: Enable 50 MHz external ref clock at XI (preserve defaults) + eth_write_phy(PHY_ADDR, PHY_PC2R, BIT(15) | BIT(8) | BIT(7)); + // Select RMII mode, 100M, keep CRC, set max rx length, disable loop + ENET->RCR = (1518 << 16) | BIT(8) | BIT(2); + // ENET->RCR |= BIT(3); // Receive all + ENET->TCR = BIT(2); // Full-duplex + ENET->RDSR = (uint32_t) (uintptr_t) s_rxdesc; + ENET->TDSR = (uint32_t) (uintptr_t) s_txdesc; + ENET->MRBR[0] = ETH_PKT_SIZE; // Same size for RX/TX buffers // MAC address filtering (bytes in reversed order) ENET->PAUR = ((uint32_t) ifp->mac[4] << 24U) | (uint32_t) ifp->mac[5] << 16U; - ENET->PALR = (uint32_t) (ifp->mac[0] << 24U) | ((uint32_t) ifp->mac[1] << 16U) | - ((uint32_t) ifp->mac[2] << 8U) | ifp->mac[3]; - - // Init Hash tables (mac filtering) - ENET->IAUR = 0; // Unicast - ENET->IALR = 0; - ENET->GAUR = 0; // Multicast - ENET->GALR = 0; - - // Set ENET Online - ENET->ECR |= BIT(8); // ENET Set Little-endian + (FEC buffer desc.) - ENET->ECR |= BIT(1); // Enable - - // Set interrupt mask - ENET->EIMR = EIMR_RX_ERR; - - // RX Descriptor activation - ENET->RDAR = BIT(24); // Activate Receive Descriptor + ENET->PALR = (uint32_t) (ifp->mac[0] << 24U) | + ((uint32_t) ifp->mac[1] << 16U) | + ((uint32_t) ifp->mac[2] << 8U) | ifp->mac[3]; + ENET->ECR = BIT(8) | BIT(1); // Little-endian CPU, Enable + ENET->EIMR = BIT(25); // Set interrupt mask + ENET->RDAR = BIT(24); // Receive Descriptors have changed return true; } // Transmit frame -static uint32_t s_rt1020_txno; +static uint32_t s_txno; -static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len, struct mg_tcpip_if *ifp) { - - if (len > sizeof(tx_data_buffer[ENET_TXBD_NUM])) { - // MG_ERROR(("Frame too big, %ld", (long) len)); - len = 0; // Frame is too big - } else if ((tx_buffer_descriptor[s_rt1020_txno].control & BIT(15))) { - MG_ERROR(("No free descriptors")); - // printf("D0 %lx SR %lx\n", (long) s_txdesc[0][0], (long) ETH->DMASR); - len = 0; // All descriptors are busy, fail +static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len, + struct mg_tcpip_if *ifp) { + if (len > sizeof(s_txbuf[ETH_DESC_CNT])) { + MG_ERROR(("Frame too big, %ld", (long) len)); + len = 0; // fail + } else if ((s_txdesc[s_txno].control & BIT(15))) { + ifp->nerr++; + MG_ERROR(("No descriptors available")); + len = 0; // fail } else { - memcpy(tx_data_buffer[s_rt1020_txno], buf, len); // Copy data - tx_buffer_descriptor[s_rt1020_txno].length = (uint16_t) len; // Set data len - tx_buffer_descriptor[s_rt1020_txno].control |= (uint16_t)(BIT(10)); // TC (transmit CRC) - // tx_buffer_descriptor[s_rt1020_txno].control &= (uint16_t)(BIT(14) | BIT(12)); // Own doesn't affect HW - tx_buffer_descriptor[s_rt1020_txno].control |= (uint16_t)(BIT(15) | BIT(11)); // R+L (ready+last) - ENET->TDAR = BIT(24); // Descriptor updated. Hand over to DMA. - // INFO - // Relevant Descriptor bits: 15(R) Ready - // 11(L) last in frame - // 10(TC) transmis CRC - // __DSB(); // ARM errata 838869 Cortex-M4, M4F, M7, M7F: "store immediate overlapping - // exception" return might vector to incorrect interrupt. - if (++s_rt1020_txno >= ENET_TXBD_NUM) s_rt1020_txno = 0; + memcpy(s_txbuf[s_txno], buf, len); // Copy data + s_txdesc[s_txno].length = (uint16_t) len; // Set data len + // Table 37-34, R, L, TC (Ready, last, transmit CRC after frame + s_txdesc[s_txno].control |= (uint16_t) (BIT(15) | BIT(11) | BIT(10)); + ENET->TDAR = BIT(24); // Descriptor ring updated + if (++s_txno >= ETH_DESC_CNT) s_txno = 0; } (void) ifp; return len; } -// IRQ (RX) -static uint32_t s_rt1020_rxno; - -void ENET_IRQHandler(void) { - ENET->EIMR = 0; // Mask interrupts. - uint32_t eir = ENET->EIR; // Read EIR - ENET->EIR = 0xffffffff; // Clear interrupts - - if (eir & EIMR_RX_ERR) // Global mask used - { - if (rx_buffer_descriptor[s_rt1020_rxno].control & BIT(15)) { - ENET->EIMR = EIMR_RX_ERR; // Enable interrupts - return; // Empty? -> exit. - } - // Read inframes - else { // Frame received, loop - for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever - if (rx_buffer_descriptor[s_rt1020_rxno].control & BIT(15)) break; // exit when done - // Process if CRC OK and frame not truncated - if (!(rx_buffer_descriptor[s_rt1020_rxno].control & (BIT(2) | BIT(0)))) { - uint32_t len = (rx_buffer_descriptor[s_rt1020_rxno].length); - mg_tcpip_qwrite(rx_buffer_descriptor[s_rt1020_rxno].buffer, len > 4 ? len - 4 : len, s_ifp); - } - rx_buffer_descriptor[s_rt1020_rxno].control |= BIT(15); // Inform DMA RX is empty - if (++s_rt1020_rxno >= ENET_RXBD_NUM) s_rt1020_rxno = 0; - } - } - } - ENET->EIMR = EIMR_RX_ERR; // Enable interrupts -} - -// Up/down status static bool mg_tcpip_driver_imxrt1020_up(struct mg_tcpip_if *ifp) { - uint32_t bsr = imxrt1020_eth_read_phy(IMXRT1020_PHY_ADDR, IMXRT1020_PHY_BSR); - (void) ifp; - return bsr & BIT(2) ? 1 : 0; + uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR); + bool up = bsr & BIT(2) ? 1 : 0; + if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up + uint32_t pc1r = eth_read_phy(PHY_ADDR, PHY_PC1R); + uint32_t tcr = ENET->TCR |= BIT(2); // Full-duplex + uint32_t rcr = ENET->RCR &= ~BIT(9); // 100M + if ((pc1r & 3) == 1) rcr |= BIT(9); // 10M + if ((pc1r & BIT(2)) == 0) tcr &= ~BIT(2); // Half-duplex + ENET->TCR = tcr; // IRQ handler does not fiddle with these registers + ENET->RCR = rcr; + MG_DEBUG(("Link is %uM %s-duplex", rcr & BIT(9) ? 10 : 100, + tcr & BIT(2) ? "full" : "half")); + } + return up; +} + +void ENET_IRQHandler(void); +static uint32_t s_rxno; +void ENET_IRQHandler(void) { + ENET->EIR = BIT(25); // Ack IRQ + // Frame received, loop + for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever + if (s_rxdesc[s_rxno].control & BIT(15)) break; // exit when done + // skip partial/errored frames (Table 37-32) + if ((s_rxdesc[s_rxno].control & BIT(11)) && + !(s_rxdesc[s_rxno].control & + (BIT(5) | BIT(4) | BIT(2) | BIT(1) | BIT(0)))) { + uint32_t len = (s_rxdesc[s_rxno].length); + mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp); + } + s_rxdesc[s_rxno].control |= BIT(15); + if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0; + } + ENET->RDAR = BIT(24); // Receive Descriptors have changed + // If b24 == 0, descriptors were exhausted and probably frames were dropped } -// API struct mg_tcpip_driver mg_tcpip_driver_imxrt1020 = { - mg_tcpip_driver_imxrt1020_init, mg_tcpip_driver_imxrt1020_tx, NULL, - mg_tcpip_driver_imxrt1020_up}; + mg_tcpip_driver_imxrt1020_init, mg_tcpip_driver_imxrt1020_tx, NULL, + mg_tcpip_driver_imxrt1020_up}; #endif diff --git a/src/drivers/rt1020.h b/src/drivers/rt1020.h index a6cfc64c..f1a725ea 100644 --- a/src/drivers/rt1020.h +++ b/src/drivers/rt1020.h @@ -3,13 +3,14 @@ struct mg_tcpip_driver_imxrt1020_data { // MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk), // must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz - // ipg_clk MSCR mdc_cr VALUE - // ------------------------------------- - // -1 <-- tell driver to guess the value - // 25 MHz 0x04 0 - // 33 MHz 0x06 1 - // 40 MHz 0x07 2 - // 50 MHz 0x09 3 - // 66 MHz 0x0D 4 <-- value for iMXRT1020-EVK at max freq. - int mdc_cr; // Valid values: -1, 0, 1, 2, 3, 4 + // 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1)) + // ipg_clk mdc_cr VALUE + // -------------------------- + // -1 <-- TODO() tell driver to guess the value + // 25 MHz 4 + // 33 MHz 6 + // 40 MHz 7 + // 50 MHz 9 + // 66 MHz 13 + int mdc_cr; // Valid values: -1 to 63 };