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Merge pull request #2966 from cesanta/ota-h7-dual-core
H7 dual core OTA fix
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commit
8b95a22e75
14
mongoose.c
14
mongoose.c
@ -6654,7 +6654,7 @@ bool mg_ota_end(void) {
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#if MG_OTA == MG_OTA_STM32H7
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#if MG_OTA == MG_OTA_STM32H7 || MG_OTA == MG_OTA_STM32H7_DUAL_CORE
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// - H723/735 RM 4.3.3: Note: The application can simultaneously request a read
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// and a write operation through the AXI interface.
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@ -6687,7 +6687,15 @@ static struct mg_flash s_mg_flash_stm32h7 = {
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#define FLASH_OPTSR_PRG 0x20
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#define FLASH_SIZE_REG 0x1ff1e880
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#define IS_DUALCORE() (MG_OTA == MG_OTA_STM32H7_DUAL_CORE)
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MG_IRAM static bool is_dualbank(void) {
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if (IS_DUALCORE()) {
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// H745/H755 and H747/H757 are running on dual core.
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// Using only the 1st bank (mapped to CM7), in order not to interfere
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// with the 2nd bank (CM4), possibly causing CM4 to boot unexpectedly.
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return false;
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}
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return (s_mg_flash_stm32h7.size < 2 * 1024 * 1024) ? false : true;
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}
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@ -6824,6 +6832,10 @@ MG_IRAM static void single_bank_swap(char *p1, char *p2, size_t s, size_t ss) {
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bool mg_ota_begin(size_t new_firmware_size) {
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s_mg_flash_stm32h7.size = MG_REG(FLASH_SIZE_REG) * 1024;
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if (IS_DUALCORE()) {
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// Using only the 1st bank (mapped to CM7)
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s_mg_flash_stm32h7.size /= 2;
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}
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return mg_ota_flash_begin(new_firmware_size, &s_mg_flash_stm32h7);
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}
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@ -2651,7 +2651,8 @@ void mg_rpc_list(struct mg_rpc_req *r);
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#define MG_OTA_NONE 0 // No OTA support
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#define MG_OTA_STM32H5 1 // STM32 H5
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#define MG_OTA_STM32H7 2 // STM32 H7
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#define MG_OTA_STM32F 3 // STM32 F7/F4/F2
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#define MG_OTA_STM32H7_DUAL_CORE 3 // STM32 H7 dual core
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#define MG_OTA_STM32F 4 // STM32 F7/F4/F2
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#define MG_OTA_CH32V307 100 // WCH CH32V307
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#define MG_OTA_U2A 200 // Renesas U2A16, U2A8, U2A6
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#define MG_OTA_RT1020 300 // IMXRT1020
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@ -8,7 +8,8 @@
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#define MG_OTA_NONE 0 // No OTA support
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#define MG_OTA_STM32H5 1 // STM32 H5
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#define MG_OTA_STM32H7 2 // STM32 H7
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#define MG_OTA_STM32F 3 // STM32 F7/F4/F2
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#define MG_OTA_STM32H7_DUAL_CORE 3 // STM32 H7 dual core
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#define MG_OTA_STM32F 4 // STM32 F7/F4/F2
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#define MG_OTA_CH32V307 100 // WCH CH32V307
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#define MG_OTA_U2A 200 // Renesas U2A16, U2A8, U2A6
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#define MG_OTA_RT1020 300 // IMXRT1020
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@ -2,7 +2,7 @@
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#include "log.h"
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#include "ota.h"
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#if MG_OTA == MG_OTA_STM32H7
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#if MG_OTA == MG_OTA_STM32H7 || MG_OTA == MG_OTA_STM32H7_DUAL_CORE
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// - H723/735 RM 4.3.3: Note: The application can simultaneously request a read
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// and a write operation through the AXI interface.
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@ -35,7 +35,15 @@ static struct mg_flash s_mg_flash_stm32h7 = {
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#define FLASH_OPTSR_PRG 0x20
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#define FLASH_SIZE_REG 0x1ff1e880
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#define IS_DUALCORE() (MG_OTA == MG_OTA_STM32H7_DUAL_CORE)
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MG_IRAM static bool is_dualbank(void) {
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if (IS_DUALCORE()) {
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// H745/H755 and H747/H757 are running on dual core.
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// Using only the 1st bank (mapped to CM7), in order not to interfere
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// with the 2nd bank (CM4), possibly causing CM4 to boot unexpectedly.
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return false;
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}
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return (s_mg_flash_stm32h7.size < 2 * 1024 * 1024) ? false : true;
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}
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@ -172,6 +180,10 @@ MG_IRAM static void single_bank_swap(char *p1, char *p2, size_t s, size_t ss) {
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bool mg_ota_begin(size_t new_firmware_size) {
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s_mg_flash_stm32h7.size = MG_REG(FLASH_SIZE_REG) * 1024;
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if (IS_DUALCORE()) {
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// Using only the 1st bank (mapped to CM7)
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s_mg_flash_stm32h7.size /= 2;
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}
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return mg_ota_flash_begin(new_firmware_size, &s_mg_flash_stm32h7);
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}
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