mirror of
https://github.com/cesanta/mongoose.git
synced 2024-12-25 22:20:49 +08:00
move to Wizard
This commit is contained in:
Sergio R. Caprile
parent
b6dc830bcb
commit
851b3a7cfb
@ -1,38 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configCPU_CLOCK_HZ SYS_FREQUENCY
|
||||
#define configTICK_RATE_HZ 1000
|
||||
#define configMAX_PRIORITIES 5
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TIMERS 0
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configUSE_MALLOC_FAILED_HOOK 0
|
||||
#define configMINIMAL_STACK_SIZE 128
|
||||
#define configTOTAL_HEAP_SIZE (1024 * 32)
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_xTaskGetSchedulerState 1 // trying
|
||||
|
||||
#ifdef __NVIC_PRIO_BITS
|
||||
#define configPRIO_BITS __NVIC_PRIO_BITS
|
||||
#else
|
||||
#define configPRIO_BITS 4
|
||||
#endif
|
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
|
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
|
||||
#define configKERNEL_INTERRUPT_PRIORITY \
|
||||
(configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
|
||||
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY \
|
||||
(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
|
||||
|
||||
#define configASSERT(expr) \
|
||||
if (!(expr)) printf("FAILURE %s:%d: %s\n", __FILE__, __LINE__, #expr)
|
||||
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
#define xPortSysTickHandler SysTick_Handler
|
||||
@ -1,84 +1,29 @@
|
||||
CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
|
||||
CFLAGS += -Wformat-truncation -fno-common # -Wconversion is not SDK-friendly
|
||||
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
|
||||
CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MIMXRT1021
|
||||
CFLAGS += -Icmsis_mcu/devices/MIMXRT1021/drivers -DCPU_MIMXRT1021DAG5A
|
||||
CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
|
||||
LDSCRIPT = link.ld
|
||||
LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
|
||||
BOARD = rt1020
|
||||
IDE = GCC+make
|
||||
RTOS = FreeRTOS
|
||||
WIZARD_URL ?= http://mongoose.ws/wizard
|
||||
|
||||
SOURCES = main.c syscalls.c sysinit.c
|
||||
SOURCES += cmsis_mcu/devices/MIMXRT1021/gcc/startup_MIMXRT1021.S # NXP startup file. Compiler-dependent!
|
||||
CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS # Make startup code work as expected
|
||||
|
||||
# FreeRTOS. RT1020 has a Cortex-M7 r1p2 core, FreeRTOS recommends using CM4F port for non-r0p1 CM7 micros
|
||||
SOURCES += FreeRTOS-Kernel/portable/MemMang/heap_4.c
|
||||
SOURCES += FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c
|
||||
CFLAGS += -IFreeRTOS-Kernel/include
|
||||
CFLAGS += -IFreeRTOS-Kernel/portable/GCC/ARM_CM4F -Wno-conversion
|
||||
|
||||
# Mongoose options are defined in mongoose_config.h
|
||||
SOURCES += mongoose.c net.c packed_fs.c
|
||||
|
||||
# Example specific build options. See README.md
|
||||
CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\"
|
||||
|
||||
ifeq ($(OS),Windows_NT)
|
||||
RM = cmd /C del /Q /F /S
|
||||
else
|
||||
RM = rm -rf
|
||||
endif
|
||||
|
||||
all build example update: SOURCES += flash_image.c
|
||||
all build example: firmware.bin
|
||||
|
||||
ram: LDSCRIPT = link_ram.ld
|
||||
ram: firmware.bin
|
||||
firmware.bin: wizard
|
||||
make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
|
||||
|
||||
firmware.bin: firmware.elf
|
||||
arm-none-eabi-objcopy -O binary $< $@
|
||||
wizard:
|
||||
hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
|
||||
&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
|
||||
unzip wizard.zip
|
||||
cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h
|
||||
|
||||
firmware.elf: FreeRTOS-Kernel cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld link.ld mongoose_config.h
|
||||
arm-none-eabi-gcc $(SOURCES) $(wildcard FreeRTOS-Kernel/*.c) $(CFLAGS) $(LDFLAGS) -o $@
|
||||
|
||||
flash: firmware.bin
|
||||
# flash
|
||||
|
||||
cmsis_core: # ARM CMSIS core headers
|
||||
git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
|
||||
cmsis_mcu:
|
||||
curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1021_DFP.17.0.0.pack -o $@.zip
|
||||
mkdir $@ && cd $@ && unzip -q ../$@.zip
|
||||
FreeRTOS-Kernel: # FreeRTOS sources
|
||||
git clone --depth 1 -b V10.5.0 https://github.com/FreeRTOS/FreeRTOS-Kernel $@
|
||||
|
||||
# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
|
||||
DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/4
|
||||
update: firmware.bin
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
|
||||
|
||||
update updateram: CFLAGS += -DUART_DEBUG=LPUART2
|
||||
|
||||
test update: CFLAGS_EXTRA ="-DUART_DEBUG=LPUART2"
|
||||
test: update
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt
|
||||
grep 'READY, IP:' /tmp/output.txt # Check for network init
|
||||
|
||||
|
||||
updateram: ram
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @firmware.bin
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}'
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1 wm,e000ed0c,5fa0004"}'
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}'
|
||||
PC=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,4"}' | jq -r .resp[5:]` && \
|
||||
SP=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,0"}' | jq -r .resp[5:]` && \
|
||||
REQ="wm,e000ed08,0 wr,d,$$SP wr,f,$$PC" && \
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"'"$$REQ"'"}'
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0001"}'
|
||||
|
||||
testram: updateram
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
|
||||
grep 'READY, IP:' /tmp/output.txt # Check for network init
|
||||
|
||||
|
||||
clean:
|
||||
$(RM) firmware.* *.su cmsis_core cmsis_mcu FreeRTOS-Kernel *.zip
|
||||
rm -rf firmware.* wizard*
|
||||
|
||||
1
examples/nxp/rt1020-evk-make-freertos-builtin/README.md
Normal file
1
examples/nxp/rt1020-evk-make-freertos-builtin/README.md
Normal file
@ -0,0 +1 @@
|
||||
See [Wizard](https://mongoose.ws/wizard/#/output?board=rt1020&ide=GCC+make&rtos=FreeRTOS&file=README.md)
|
||||
@ -1,91 +0,0 @@
|
||||
/*
|
||||
* Copyright 2020-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define __DCD_DATA \
|
||||
0xD2, 0x03, 0xE0, 0x41, 0xCC, 0x03, 0x5C, 0x04, 0x40, 0x0F, 0xC0, 0x68, \
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, \
|
||||
0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x74, \
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, \
|
||||
0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x80, \
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, \
|
||||
0x40, 0x0D, 0x81, 0x00, 0x10, 0x18, 0x10, 0x1B, 0x40, 0x0F, 0xC0, 0x14, \
|
||||
0x00, 0x0A, 0x83, 0x40, 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x1C, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x28, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x34, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x40, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x4C, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x58, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x64, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x70, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x7C, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x10, 0x40, 0x1F, 0x80, 0x88, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x94, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA0, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xAC, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x81, 0x88, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0x8C, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0x90, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x81, 0x94, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0x98, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0x9C, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x81, 0xA0, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xA4, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xA8, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x81, 0xAC, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xB0, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xB4, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x81, 0xB8, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xBC, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xC0, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x81, 0xC4, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xC8, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xCC, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x81, 0xD0, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xD4, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xD8, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x81, 0xDC, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xE0, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xE4, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x81, 0xE8, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xEC, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xF0, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x81, 0xF4, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xF8, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xFC, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x82, 0x00, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x04, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x10, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x1C, \
|
||||
0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xE1, \
|
||||
0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x2F, 0x00, 0x00, \
|
||||
0x10, 0x00, 0x00, 0x04, 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, \
|
||||
0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, 0x40, 0x2F, 0x00, 0x10, \
|
||||
0x80, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, \
|
||||
0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x04, \
|
||||
0x00, 0x00, 0x79, 0x88, 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07, \
|
||||
0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, 0x40, 0x2F, 0x00, 0x48, \
|
||||
0x00, 0x01, 0x09, 0x20, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, \
|
||||
0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x84, \
|
||||
0x00, 0x88, 0x88, 0x88, 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, \
|
||||
0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x90, \
|
||||
0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, \
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, \
|
||||
0xCC, 0x00, 0x14, 0x04, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, 0xCF, 0x00, 0x0C, 0x1C, \
|
||||
0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, \
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, \
|
||||
0xA5, 0x5A, 0x00, 0x0C, 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, \
|
||||
0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x1C, 0x04, 0x40, 0x2F, 0x00, 0xA0, \
|
||||
0x00, 0x00, 0x00, 0x30, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, 0xCF, 0x00, 0x0C, 0x1C, \
|
||||
0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x0C, 0x04, \
|
||||
0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
|
||||
@ -1,61 +0,0 @@
|
||||
#include "dcd.h" // pin settings for MIMXRT1020-EVK board
|
||||
#include "fsl_flexspi.h" // peripheral structures
|
||||
#include "fsl_romapi.h" // peripheral structures
|
||||
#include "hal.h"
|
||||
|
||||
extern uint32_t __isr_vector[];
|
||||
|
||||
// RM 9.7.2
|
||||
__attribute__((section(".dcd"), used))
|
||||
const uint8_t __ivt_dcd_data[] = {__DCD_DATA};
|
||||
|
||||
// RM 9.7.1
|
||||
__attribute__((section(".dat"), used)) const uint32_t __ivt_boot_data[] = {
|
||||
FlexSPI_AMBA_BASE, // boot start location
|
||||
8 * 1024 * 1024, // size
|
||||
0, // Plugin flag
|
||||
0Xffffffff // empty - extra data word
|
||||
};
|
||||
|
||||
__attribute__((section(".ivt"), used)) const uint32_t __ivt[8] = {
|
||||
0x412000d1, // header: 41 - version, 2000 size, d1 tag
|
||||
(uint32_t) __isr_vector, // entry
|
||||
0, // reserved
|
||||
(uint32_t) __ivt_dcd_data, // dcd
|
||||
(uint32_t) __ivt_boot_data, // boot data
|
||||
(uint32_t) __ivt, // this is us - ivt absolute address
|
||||
0, // csf absolute address
|
||||
0, // reserved for HAB
|
||||
};
|
||||
|
||||
#define __FLEXSPI_QSPI_LUT { \
|
||||
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), \
|
||||
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),\
|
||||
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),\
|
||||
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),\
|
||||
[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),\
|
||||
[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),\
|
||||
[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),\
|
||||
[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),\
|
||||
[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),\
|
||||
}
|
||||
|
||||
// MIMXRT1060-EVKB flash chip config: S25LP064A-JBLE
|
||||
__attribute__((section(".cfg"), used))
|
||||
const flexspi_nor_config_t __qspi_flash_cfg = {
|
||||
.memConfig = {.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = 1, // ReadSampleClk_LoopbackFromDqsPad
|
||||
.csHoldTime = 3,
|
||||
.csSetupTime = 3,
|
||||
.controllerMiscOption = BIT(4),
|
||||
.deviceType = 1, // serial NOR
|
||||
.sflashPadType = 4,
|
||||
.serialClkFreq = 7, // 133MHz
|
||||
.sflashA1Size = 8 * 1024 * 1024,
|
||||
.lookupTable = __FLEXSPI_QSPI_LUT},
|
||||
.pageSize = 256,
|
||||
.sectorSize = 4 * 1024,
|
||||
.ipcmdSerialClkFreq = 1,
|
||||
.blockSize = 64 * 1024,
|
||||
.isUniformBlockSize = false};
|
||||
@ -1,337 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
// https://www.nxp.com/webapp/Download?colCode=IMXRT1020RM
|
||||
// https://cache.nxp.com/secured/assets/documents/en/user-guide/MIMXRT1020EVKHUG.pdf
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "MIMXRT1021.h"
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
|
||||
#define PIN(bank, num) ((((bank) - '0') << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
// Use LED for blinking, GPIO_AD_B0_05. GPIO1.5 (schematics)
|
||||
#define LED PIN('1', 5)
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG LPUART1
|
||||
#endif
|
||||
|
||||
// No settable constants, see sysinit.c
|
||||
#define SYS_FREQUENCY 500000000UL
|
||||
|
||||
static inline void spin(volatile uint32_t count) {
|
||||
while (count--) (void) 0;
|
||||
}
|
||||
|
||||
enum { CLOCK_OFF = 0U, CLOCK_ON_RUN = 1U, CLOCK_ON_RUN_WAIT = 3U };
|
||||
static inline void clock_periph(uint32_t index, uint32_t shift, uint32_t val) {
|
||||
volatile uint32_t *r = &CCM->CCGR0;
|
||||
SETBITS(r[index], 3UL << shift, val << shift);
|
||||
}
|
||||
|
||||
// which peripheral feeds the pin
|
||||
static inline void gpio_mux_config(uint16_t index, uint8_t af) {
|
||||
IOMUXC->SW_MUX_CTL_PAD[index] = af;
|
||||
}
|
||||
|
||||
// which pin feeds the peripheral (2nd stage)
|
||||
static inline void periph_mux_config(uint16_t index, uint8_t in) {
|
||||
IOMUXC->SELECT_INPUT[index] = in;
|
||||
}
|
||||
|
||||
enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT };
|
||||
enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_MEDIUM_, GPIO_SPEED_HIGH };
|
||||
enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP };
|
||||
static inline GPIO_Type *gpio_bank(uint16_t pin) {
|
||||
static const GPIO_Type *g[] = {NULL, GPIO1, GPIO2, GPIO3, NULL, GPIO5};
|
||||
return (GPIO_Type *) g[PINBANK(pin)];
|
||||
}
|
||||
|
||||
// pin driver/pull-up/down configuration (ignore "keeper")
|
||||
static inline void gpio_pad_config(uint16_t index, uint8_t type, uint8_t speed,
|
||||
uint8_t pull) {
|
||||
bool dopull = pull > 0;
|
||||
if (dopull) --pull;
|
||||
IOMUXC->SW_PAD_CTL_PAD[index] =
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_ODE(type) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PKE(dopull) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PUS(pull) | IOMUXC_SW_PAD_CTL_PAD_DSE(7);
|
||||
}
|
||||
|
||||
static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint8_t bit = (uint8_t) PINNO(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
|
||||
clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s
|
||||
switch (PINBANK(pin)) {
|
||||
case 1:
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 + bit, type, speed,
|
||||
pull);
|
||||
clock_periph(1, CCM_CCGR1_CG13_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
break;
|
||||
case 2:
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 + bit, type, speed,
|
||||
pull);
|
||||
clock_periph(0, CCM_CCGR0_CG15_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
break;
|
||||
case 3:
|
||||
gpio_mux_config(bit < 13
|
||||
? kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 + bit
|
||||
: kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 + bit - 13,
|
||||
5);
|
||||
gpio_pad_config(bit < 13
|
||||
? kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 + bit
|
||||
: kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 + bit - 13,
|
||||
type, speed, pull);
|
||||
clock_periph(2, CCM_CCGR2_CG13_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
break;
|
||||
case 5:
|
||||
// TODO(): support sw_mux
|
||||
clock_periph(1, CCM_CCGR1_CG15_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
gpio->IMR &= ~mask;
|
||||
if (mode == GPIO_MODE_INPUT) {
|
||||
gpio->GDIR &= ~mask;
|
||||
} else {
|
||||
gpio->GDIR |= mask;
|
||||
}
|
||||
}
|
||||
static inline void gpio_input(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_NONE);
|
||||
}
|
||||
static inline void gpio_output(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
static inline bool gpio_read(uint16_t pin) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
return gpio->DR & mask;
|
||||
}
|
||||
static inline void gpio_write(uint16_t pin, bool value) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
if (value) {
|
||||
gpio->DR |= mask;
|
||||
} else {
|
||||
gpio->DR &= ~mask;
|
||||
}
|
||||
}
|
||||
static inline void gpio_toggle(uint16_t pin) {
|
||||
gpio_write(pin, !gpio_read(pin));
|
||||
}
|
||||
|
||||
// 14.5 Table 14-4: uart_clk_root
|
||||
// see sysinit.c for clocks, (14.7.9: defaults to PLL3/6/1 = 80MHz)
|
||||
static inline void uart_init(LPUART_Type *uart, unsigned long baud) {
|
||||
uint8_t af = 2; // Alternate function
|
||||
uint16_t mr = 0, pr = 0, mt = 0, pt = 0; // pins
|
||||
uint32_t freq = 80000000; // uart_clk_root frequency
|
||||
if (uart == LPUART1)
|
||||
mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06,
|
||||
pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06,
|
||||
mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07,
|
||||
pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07;
|
||||
if (uart == LPUART2)
|
||||
mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08,
|
||||
pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08,
|
||||
mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09,
|
||||
pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09;
|
||||
|
||||
if (uart == LPUART1) clock_periph(5, CCM_CCGR5_CG12_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
if (uart == LPUART2) clock_periph(0, CCM_CCGR0_CG14_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s
|
||||
gpio_mux_config(mt, af);
|
||||
gpio_pad_config(pt, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
gpio_mux_config(mr, af);
|
||||
gpio_pad_config(pr, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
|
||||
uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
|
||||
uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
|
||||
SETBITS(uart->BAUD,
|
||||
LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK,
|
||||
LPUART_BAUD_OSR(16 - 1) |
|
||||
LPUART_BAUD_SBR(freq / (16 * baud))); // Rx sample at 16x
|
||||
SETBITS(uart->CTRL,
|
||||
LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
|
||||
LPUART_CTRL_IDLECFG_MASK,
|
||||
LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) |
|
||||
LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit
|
||||
uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
|
||||
}
|
||||
|
||||
static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
|
||||
uart->DATA = byte;
|
||||
while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1);
|
||||
}
|
||||
static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int uart_read_ready(LPUART_Type *uart) {
|
||||
(void) uart;
|
||||
return uart->STAT & LPUART_STAT_RDRF_MASK;
|
||||
}
|
||||
static inline uint8_t uart_read_byte(LPUART_Type *uart) {
|
||||
return (uint8_t) (uart->DATA & 255);
|
||||
}
|
||||
|
||||
static inline void rng_init(void) {
|
||||
clock_periph(6, CCM_CCGR6_CG6_SHIFT, CLOCK_ON_RUN_WAIT); // trng_clk
|
||||
SETBITS(TRNG->MCTL,
|
||||
TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK | TRNG_MCTL_RST_DEF_MASK,
|
||||
TRNG_MCTL_PRGM(1) | TRNG_MCTL_ERR(1) |
|
||||
TRNG_MCTL_RST_DEF(1)); // reset to default values
|
||||
SETBITS(TRNG->MCTL, TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK,
|
||||
TRNG_MCTL_PRGM(0)); // set to run mode
|
||||
(void) TRNG->ENT[TRNG_ENT_COUNT - 1]; // start new entropy generation
|
||||
(void) TRNG->ENT[0]; // defect workaround
|
||||
}
|
||||
static inline uint32_t rng_read(void) {
|
||||
static uint8_t idx = 0;
|
||||
while ((TRNG->MCTL & TRNG_MCTL_ENT_VAL_MASK) == 0) (void) 0;
|
||||
uint32_t data = TRNG->ENT[idx++]; // read data
|
||||
idx %= TRNG_ENT_COUNT; // stay within array limits
|
||||
if (idx == 0) // we've just read TRNG_ENT_COUNT - 1
|
||||
(void) TRNG->ENT[0]; // defect workaround
|
||||
return data;
|
||||
}
|
||||
|
||||
// - PHY has no xtal, XI driven from ENET_REF_CLK1 (labeled as ENET_TX_CLK
|
||||
// (GPIO_AD_B0_08)), generated by the MCU
|
||||
// - PHY RST connected to GPIO1.4 (GPIO_AD_B0_04); INTRP/NAND_TREE connected to
|
||||
// GPIO1.22 (GPIO_AD_B1_06)
|
||||
// - 37.4 REF_CLK1 is RMII mode reference clock for Rx, Tx, and SMI; it is I/O
|
||||
// - 11.4.2 IOMUXC_GPR_GPR1 bit 17: ENET_REF_CLK_DIR --> 1 ENET_REF_CLK is
|
||||
// output driven by ref_enetpll0
|
||||
// - 14.6.1.3.4 Ethernet PLL (PLL6)
|
||||
static inline void ethernet_init(void) {
|
||||
gpio_init(PIN('1', 4), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM, GPIO_PULL_UP); // set GPIO1.4 as GPIO (PHY \RST)
|
||||
gpio_write(PIN('1', 4), 0); // reset PHY
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08,
|
||||
4); // set for ENET_REF_CLK1
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08] |=
|
||||
IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_ENET_RMII_SELECT_INPUT,
|
||||
1); // drive peripheral from B0_08, so RMII clock is taken
|
||||
// from ENET_REF_CLK1
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09, 0); // set for RXDATA1
|
||||
periph_mux_config(kIOMUXC_ENET_RX_DATA1_SELECT_INPUT,
|
||||
1); // drive peripheral from B0_09
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10, 0); // set for RXDATA0
|
||||
periph_mux_config(kIOMUXC_ENET_RX_DATA0_SELECT_INPUT,
|
||||
1); // drive peripheral from B0_10
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11, 0); // set for CRS
|
||||
periph_mux_config(kIOMUXC_ENET_RX_EN_SELECT_INPUT,
|
||||
1); // drive peripheral from B0_11
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12, 0); // set for RXERR
|
||||
periph_mux_config(kIOMUXC_ENET_RX_ERR_SELECT_INPUT,
|
||||
1); // drive peripheral from B0_12
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13, 0); // set for TXEN
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14, 0); // set for TXDATA0
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15, 0); // set for TXDATA1
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, 4); // set for MDIO
|
||||
periph_mux_config(kIOMUXC_ENET_MDIO_SELECT_INPUT,
|
||||
2); // drive peripheral from EMC_40
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, 4); // set for MDC
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
|
||||
gpio_init(PIN('1', 22), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_UP); // set GPIO1.22 as GPIO (PHY INTRP/NAND_TREE)
|
||||
gpio_write(PIN('1', 22), 1); // prevent NAND_TREE
|
||||
// 14.8.9 Use 500MHz reference and generate 50MHz. This is done at sysinit.c,
|
||||
// as we use this source to clock the core
|
||||
spin(10000); // keep PHY RST low for a while
|
||||
gpio_write(PIN('1', 4), 1); // deassert RST
|
||||
gpio_init(PIN('1', 22), GPIO_MODE_INPUT, 0, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_UP); // setup IRQ (pulled-up)(not used)
|
||||
|
||||
IOMUXC_GPR->GPR1 |=
|
||||
IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR(1); // Set ENET_REF_CLK1 as output
|
||||
clock_periph(1, CCM_CCGR1_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enet_ipg_clk
|
||||
NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler
|
||||
}
|
||||
|
||||
// Helper macro for MAC generation, byte reads not allowed
|
||||
#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
|
||||
{ \
|
||||
2, OCOTP->CFG0 & 255, (OCOTP->CFG0 >> 10) & 255, \
|
||||
((OCOTP->CFG0 >> 19) ^ (OCOTP->CFG1 >> 19)) & 255, \
|
||||
(OCOTP->CFG1 >> 10) & 255, OCOTP->CFG1 & 255 \
|
||||
}
|
||||
|
||||
static inline void flash_init(void) { // QSPI in FlexSPI
|
||||
// set pins
|
||||
clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05, 1); // set for DQS
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11, 1); // set for SS
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07, 1); // set for SCLK
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_FLEXSPI_A_SCLK_SELECT_INPUT, 0); // drive peripheral from B1_07
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08, 1); // set for DATA0
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT, 0); // drive peripheral from B1_08
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10, 1); // set for DATA1
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT, 0); // drive peripheral from B1_10
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09, 1); // set for DATA2
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT, 0); // drive peripheral from B1_09
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06, 1); // set for DATA3
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT, 0); // drive peripheral from B1_06
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
// set FlexSPI clock
|
||||
SETBITS(CCM->CSCMR1, CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK | CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_CSCMR1_FLEXSPI_CLK_SEL(3) | CCM_CSCMR1_FLEXSPI_PODF(3)); // select PLL3 PFD0 /4
|
||||
clock_periph(6, CCM_CCGR6_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enable
|
||||
}
|
||||
@ -1,22 +0,0 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash_hdr(rx) : ORIGIN = 0x60000000, LENGTH = 8k
|
||||
flash_irq(rx) : ORIGIN = 0x60002000, LENGTH = 1k
|
||||
flash_code(rx) : ORIGIN = 0x60002400, LENGTH = 8183k
|
||||
|
||||
itcram(rx) : ORIGIN = 0x00000000, LENGTH = 64k
|
||||
dtcram(rw) : ORIGIN = 0x20000000, LENGTH = 64k
|
||||
ocram(rw) : ORIGIN = 0x20200000, LENGTH = 128k
|
||||
}
|
||||
__StackTop = ORIGIN(dtcram) + LENGTH(dtcram);
|
||||
|
||||
SECTIONS {
|
||||
.hdr : { FILL(0xff) ; KEEP(*(.cfg)) . = 0x1000 ; KEEP(*(.ivt)) . = 0x1020 ;
|
||||
KEEP(*(.dat)) . = 0x1030 ; KEEP(*(.dcd)) . = 0x2000 ;} >flash_hdr
|
||||
.irq : { KEEP(*(.isr_vector)) } > flash_irq
|
||||
.text : { *(.text* .text.*) *(.rodata*) ; } > flash_code
|
||||
.data : { __data_start__ = .; *(.data SORT(.data.*)) __data_end__ = .; } > dtcram AT > flash_code
|
||||
__etext = LOADADDR(.data);
|
||||
.bss : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > dtcram
|
||||
_end = .;
|
||||
}
|
||||
@ -1,75 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
#include "mongoose.h"
|
||||
#include "net.h"
|
||||
|
||||
#define BLINK_PERIOD_MS 1000 // LED blinking period in millis
|
||||
|
||||
bool mg_random(void *buf, size_t len) { // Use on-board RNG
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void timer_fn(void *arg) {
|
||||
struct mg_tcpip_if *ifp = arg; // And show
|
||||
const char *names[] = {"down", "up", "req", "ready"}; // network stats
|
||||
MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u",
|
||||
names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent,
|
||||
ifp->ndrop, ifp->nerr));
|
||||
}
|
||||
|
||||
static void server(void *args) {
|
||||
struct mg_mgr mgr; // Initialise Mongoose event manager
|
||||
mg_mgr_init(&mgr); // and attach it to the interface
|
||||
mg_log_set(MG_LL_DEBUG); // Set log level
|
||||
|
||||
// Initialise Mongoose network stack
|
||||
ethernet_init();
|
||||
struct mg_tcpip_driver_imxrt_data driver_data = {.mdc_cr = 24, .phy_addr = 2};
|
||||
struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
|
||||
// Uncomment below for static configuration:
|
||||
// .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
|
||||
// .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
|
||||
// .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
|
||||
.driver = &mg_tcpip_driver_imxrt,
|
||||
.driver_data = &driver_data};
|
||||
mg_tcpip_init(&mgr, &mif);
|
||||
mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
|
||||
|
||||
MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac));
|
||||
while (mif.state != MG_TCPIP_STATE_READY) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
MG_INFO(("Initialising application..."));
|
||||
web_init(&mgr);
|
||||
|
||||
MG_INFO(("Starting event loop"));
|
||||
for (;;) mg_mgr_poll(&mgr, 1); // Infinite event loop
|
||||
(void) args;
|
||||
}
|
||||
|
||||
static void blinker(void *args) {
|
||||
gpio_output(LED); // Setup blue LED
|
||||
for (;;) {
|
||||
gpio_toggle(LED);
|
||||
vTaskDelay(pdMS_TO_TICKS(BLINK_PERIOD_MS));
|
||||
}
|
||||
(void) args;
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
uart_init(UART_DEBUG, 115200); // Initialise UART
|
||||
|
||||
// Start tasks. NOTE: stack sizes are in 32-bit words
|
||||
xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL);
|
||||
xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL);
|
||||
|
||||
vTaskStartScheduler(); // This blocks
|
||||
return 0;
|
||||
}
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.c
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.h
|
||||
@ -1,13 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
#include <errno.h> // we are not using lwIP
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_FREERTOS
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_DRIVER_IMXRT 1
|
||||
#define MG_IO_SIZE 256
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.c
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.h
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/packed_fs.c
|
||||
@ -1,85 +0,0 @@
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
int _fstat(int fd, struct stat *st) {
|
||||
if (fd < 0) return -1;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
extern char _end;
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
if (heap == NULL) heap = (unsigned char *) &_end;
|
||||
prev_heap = heap;
|
||||
heap += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int mkdir(const char *path, mode_t mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _init(void) {}
|
||||
@ -1,82 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// This file contains essentials required by the CMSIS:
|
||||
// uint32_t SystemCoreClock - holds the system core clock value
|
||||
// SystemInit() - initialises the system, e.g. sets up clocks
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
uint32_t SystemCoreClock = SYS_FREQUENCY;
|
||||
|
||||
// - 14.4, Figure 14-2: clock tree
|
||||
// - 14.7.4: ARM_PODF defaults to /1
|
||||
// - 14.7.5: AHB_PODF defaults to /1; PERIPH_CLK_SEL defaults to derive clock
|
||||
// from pre_periph_clk_sel
|
||||
// - 14.7.6: PRE_PERIPH_CLK_SEL defaults to derive clock from PLL2 PFD3.
|
||||
// - (For 528MHz operation, we need to set it to derive clock from PLL2, but
|
||||
// this chip max is 500 MHz).
|
||||
// - 14.6.1.3.1 System PLL (PLL2); 13.3.2.2 PLLs; 14.6.1.4 Phase Fractional
|
||||
// Dividers (PFD)
|
||||
// - 14.8.2: PLL2 is powered off and bypassed to 24MHz
|
||||
// - 14.8.11: PFD defaults to 18/16 but Figure 14-2 shows half the value
|
||||
// ("divider")
|
||||
// - For 500MHz operation, we need to set PRE_PERIPH_CLK_SEL to derive clock
|
||||
// from divided PLL6
|
||||
// - 14.8.9: configure PLL6 to generate a 500MHz clock
|
||||
// - Datasheet 4.1.3: System frequency/Bus frequency max 500/125MHz respectively
|
||||
// (AHB/IPG)
|
||||
// - MCUXpresso: IPG_CLK_ROOT <= 125MHz; PERCLK_CLK_ROOT <= 62.5MHz
|
||||
// - Datasheet 4.8.4.1.1/2: the processor clock frequency must exceed twice the
|
||||
// ENET_RX_CLK/ENET_TX_CLK frequency.
|
||||
// - Datasheet 4.8.4.2: no details for RMII (above is for MII), assumed 50MHz
|
||||
// min processor clock
|
||||
// - Datasheet 4.1.3, Table 11: "Overdrive" run mode requires 1.25V core voltage
|
||||
// minimum
|
||||
void SystemInit(void) { // Called automatically by startup code (ints masked)
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
asm("DSB");
|
||||
asm("ISB");
|
||||
// 53.4.2: Disable watchdog after reset (unlocked)
|
||||
RTWDOG->CS &= ~RTWDOG_CS_EN_MASK;
|
||||
RTWDOG->TOVAL = 0xFFFF;
|
||||
while (RTWDOG->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock
|
||||
while ((RTWDOG->CS & RTWDOG_CS_RCS_MASK) == 0)
|
||||
spin(1); // wait for new config
|
||||
// Set VDD_SOC to 1.25V
|
||||
SETBITS(DCDC->REG3, DCDC_REG3_TRG_MASK, DCDC_REG3_TRG(0x12));
|
||||
while ((DCDC->REG0 & DCDC_REG0_STS_DC_OK_MASK) == 0)
|
||||
spin(1); // Wait for DCDC_STS_DC_OK
|
||||
// 14.8.9 Init 500MHz reference, clock the M7 core with it, generate 50MHz for
|
||||
// ENET and RMII.
|
||||
SETBITS(CCM_ANALOG->PLL_ENET, CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK,
|
||||
CCM_ANALOG_PLL_ENET_BYPASS_MASK |
|
||||
CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(0)); // bypass to 24MHz osc
|
||||
SETBITS(
|
||||
CCM_ANALOG->PLL_ENET,
|
||||
CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK,
|
||||
CCM_ANALOG_PLL_ENET_DIV_SELECT(1) | CCM_ANALOG_PLL_ENET_ENABLE_MASK |
|
||||
CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK); // setup PLL
|
||||
while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
|
||||
spin(1); // wait until it is stable
|
||||
CCM_ANALOG->PLL_ENET &=
|
||||
~CCM_ANALOG_PLL_ENET_BYPASS_MASK; // Disable Bypass (switch to PLL)
|
||||
SETBITS(CCM->CBCDR, CCM_CBCDR_IPG_PODF_MASK,
|
||||
CCM_CBCDR_IPG_PODF(3)); // Set IPG divider /4 (125MHz)
|
||||
SETBITS(CCM->CSCMR1, CCM_CSCMR1_PERCLK_PODF_MASK,
|
||||
CCM_CSCMR1_PERCLK_PODF(1)); // Set PERCLK divider /2 (62.5MHz)
|
||||
SETBITS(CCM->CBCMR, CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
|
||||
CCM_CBCMR_PRE_PERIPH_CLK_SEL(3)); // run from 500MHz clock
|
||||
// 14.5 Table 14-4: uart_clk_root
|
||||
// 14.4: uart_clk_root = PLL3/6 or OSC; CCM_CSCDR1 (14.7.9) defaults to
|
||||
// PLL3/6/1; but ROM boot code fiddles with the divider (9.5.3 Table 9-7)
|
||||
CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_POWER_MASK; // Power PLL on
|
||||
while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0)
|
||||
spin(1); // wait until it is stable
|
||||
CCM_ANALOG->PLL_USB1 &=
|
||||
~CCM_ANALOG_PLL_USB1_BYPASS_MASK; // Disable Bypass (switch to PLL)
|
||||
CCM->CSCDR1 &= ~(CCM_CSCDR1_UART_CLK_SEL_MASK | CCM_CSCDR1_UART_CLK_PODF_MASK);
|
||||
rng_init(); // Initialise random number generator
|
||||
// NXP startup code calls SystemInit BEFORE initializing RAM...
|
||||
SysTick_Config(SYS_FREQUENCY / 1000); // Sys tick every 1ms
|
||||
}
|
||||
@ -1,38 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configCPU_CLOCK_HZ SYS_FREQUENCY
|
||||
#define configTICK_RATE_HZ 1000
|
||||
#define configMAX_PRIORITIES 5
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TIMERS 0
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configUSE_MALLOC_FAILED_HOOK 0
|
||||
#define configMINIMAL_STACK_SIZE 128
|
||||
#define configTOTAL_HEAP_SIZE (1024 * 32)
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_xTaskGetSchedulerState 1 // trying
|
||||
|
||||
#ifdef __NVIC_PRIO_BITS
|
||||
#define configPRIO_BITS __NVIC_PRIO_BITS
|
||||
#else
|
||||
#define configPRIO_BITS 4
|
||||
#endif
|
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
|
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
|
||||
#define configKERNEL_INTERRUPT_PRIORITY \
|
||||
(configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
|
||||
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY \
|
||||
(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
|
||||
|
||||
#define configASSERT(expr) \
|
||||
if (!(expr)) printf("FAILURE %s:%d: %s\n", __FILE__, __LINE__, #expr)
|
||||
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
//#define xPortSysTickHandler SysTick_Handler
|
||||
@ -1,84 +1,29 @@
|
||||
CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
|
||||
CFLAGS += -Wformat-truncation -fno-common # -Wconversion is not SDK-friendly
|
||||
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
|
||||
CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MIMXRT1062
|
||||
CFLAGS += -Icmsis_mcu/devices/MIMXRT1062/drivers -DCPU_MIMXRT1062DVL6B
|
||||
CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
|
||||
LDSCRIPT = link.ld
|
||||
LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
|
||||
BOARD = rt1060
|
||||
IDE = GCC+make
|
||||
RTOS = FreeRTOS
|
||||
WIZARD_URL ?= http://mongoose.ws/wizard
|
||||
|
||||
SOURCES = main.c syscalls.c sysinit.c
|
||||
SOURCES += cmsis_mcu/devices/MIMXRT1062/gcc/startup_MIMXRT1062.S # NXP startup file. Compiler-dependent!
|
||||
CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS # Make startup code work as expected
|
||||
|
||||
# FreeRTOS. RT1060 has a Cortex-M7 r1p2 core, FreeRTOS recommends using CM4F port for non-r0p1 CM7 micros
|
||||
SOURCES += FreeRTOS-Kernel/portable/MemMang/heap_4.c
|
||||
SOURCES += FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c
|
||||
CFLAGS += -IFreeRTOS-Kernel/include
|
||||
CFLAGS += -IFreeRTOS-Kernel/portable/GCC/ARM_CM4F -Wno-conversion
|
||||
|
||||
# Mongoose options are defined in mongoose_config.h
|
||||
SOURCES += mongoose.c net.c packed_fs.c
|
||||
|
||||
# Example specific build options. See README.md
|
||||
CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\"
|
||||
|
||||
ifeq ($(OS),Windows_NT)
|
||||
RM = cmd /C del /Q /F /S
|
||||
else
|
||||
RM = rm -rf
|
||||
endif
|
||||
|
||||
all build example update: SOURCES += flash_image.c
|
||||
all build example: firmware.bin
|
||||
|
||||
ram: LDSCRIPT = link_ram.ld
|
||||
ram: firmware.bin
|
||||
firmware.bin: wizard
|
||||
make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
|
||||
|
||||
firmware.bin: firmware.elf
|
||||
arm-none-eabi-objcopy -O binary $< $@
|
||||
wizard:
|
||||
hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
|
||||
&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
|
||||
unzip wizard.zip
|
||||
cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h
|
||||
|
||||
firmware.elf: FreeRTOS-Kernel cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld link.ld mongoose_config.h
|
||||
arm-none-eabi-gcc $(SOURCES) $(wildcard FreeRTOS-Kernel/*.c) $(CFLAGS) $(LDFLAGS) -o $@
|
||||
|
||||
flash: firmware.bin
|
||||
# flash
|
||||
|
||||
cmsis_core: # ARM CMSIS core headers
|
||||
git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
|
||||
cmsis_mcu:
|
||||
curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1062_DFP.17.1.0.pack -o $@.zip
|
||||
mkdir $@ && cd $@ && unzip -q ../$@.zip
|
||||
FreeRTOS-Kernel: # FreeRTOS sources
|
||||
git clone --depth 1 -b V10.5.0 https://github.com/FreeRTOS/FreeRTOS-Kernel $@
|
||||
|
||||
# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
|
||||
DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/13
|
||||
update: firmware.bin
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
|
||||
|
||||
update updateram: CFLAGS += -DUART_DEBUG=LPUART3
|
||||
|
||||
test update: CFLAGS_EXTRA ="-DUART_DEBUG=LPUART3"
|
||||
test: update
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt
|
||||
grep 'READY, IP:' /tmp/output.txt # Check for network init
|
||||
|
||||
|
||||
updateram: ram
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @firmware.bin
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}'
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1 wm,e000ed0c,5fa0004"}'
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}'
|
||||
PC=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,4"}' | jq -r .resp[5:]` && \
|
||||
SP=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,0"}' | jq -r .resp[5:]` && \
|
||||
REQ="wm,e000ed08,0 wr,d,$$SP wr,f,$$PC" && \
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"'"$$REQ"'"}'
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0001"}'
|
||||
|
||||
testram: updateram
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
|
||||
grep 'READY, IP:' /tmp/output.txt # Check for network init
|
||||
|
||||
|
||||
clean:
|
||||
$(RM) firmware.* *.su cmsis_core cmsis_mcu FreeRTOS-Kernel *.zip
|
||||
rm -rf firmware.* wizard*
|
||||
|
||||
1
examples/nxp/rt1060-evk-make-freertos-builtin/README.md
Normal file
1
examples/nxp/rt1060-evk-make-freertos-builtin/README.md
Normal file
@ -0,0 +1 @@
|
||||
See [Wizard](https://mongoose.ws/wizard/#/output?board=rt1060&ide=GCC+make&rtos=FreeRTOS&file=README.md)
|
||||
@ -1,95 +0,0 @@
|
||||
/*
|
||||
* Copyright 2020-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define __DCD_DATA \
|
||||
0xD2, 0x04, 0x10, 0x41, 0xCC, 0x03, 0x8C, 0x04, 0x40, 0x0F, 0xC0, 0x68, \
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, \
|
||||
0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x74, \
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, \
|
||||
0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x80, \
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, \
|
||||
0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, 0x40, 0x0F, 0xC0, 0x14, \
|
||||
0x00, 0x01, 0x0D, 0x40, 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x1C, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x28, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x34, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x40, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x4C, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x58, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x64, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x70, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x7C, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x88, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x94, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA0, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xAC, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, \
|
||||
0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x08, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x14, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x20, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x2C, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x38, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x44, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x50, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x5C, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x68, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x74, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x80, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x8C, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x98, \
|
||||
0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, \
|
||||
0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x2F, 0x00, 0x00, \
|
||||
0x10, 0x00, 0x00, 0x04, 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, \
|
||||
0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, 0x40, 0x2F, 0x00, 0x10, \
|
||||
0x80, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, \
|
||||
0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x1C, \
|
||||
0x86, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, \
|
||||
0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, 0x40, 0x2F, 0x00, 0x28, \
|
||||
0xA8, 0x00, 0x00, 0x17, 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, \
|
||||
0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x04, \
|
||||
0x00, 0x00, 0x79, 0xA8, 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, \
|
||||
0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, 0x40, 0x2F, 0x00, 0x48, \
|
||||
0x00, 0x01, 0x09, 0x20, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, \
|
||||
0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x84, \
|
||||
0x00, 0x88, 0x88, 0x88, 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, \
|
||||
0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x90, \
|
||||
0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, \
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, \
|
||||
0xCC, 0x00, 0x14, 0x04, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, 0xCF, 0x00, 0x0C, 0x1C, \
|
||||
0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, \
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, \
|
||||
0xA5, 0x5A, 0x00, 0x0C, 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, \
|
||||
0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x1C, 0x04, 0x40, 0x2F, 0x00, 0xA0, \
|
||||
0x00, 0x00, 0x00, 0x33, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, \
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, 0xCF, 0x00, 0x0C, 0x1C, \
|
||||
0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x0C, 0x04, \
|
||||
0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
|
||||
@ -1,61 +0,0 @@
|
||||
#include "dcd.h" // pin settings for MIMXRT1060-EVKB board
|
||||
#include "fsl_flexspi.h" // peripheral structures
|
||||
#include "fsl_romapi.h" // peripheral structures
|
||||
#include "hal.h"
|
||||
|
||||
extern uint32_t __isr_vector[];
|
||||
|
||||
// RM 9.7.2
|
||||
__attribute__((section(".dcd"), used))
|
||||
const uint8_t __ivt_dcd_data[] = {__DCD_DATA};
|
||||
|
||||
// RM 9.7.1
|
||||
__attribute__((section(".dat"), used)) const uint32_t __ivt_boot_data[] = {
|
||||
FlexSPI_AMBA_BASE, // boot start location
|
||||
8 * 1024 * 1024, // size
|
||||
0, // Plugin flag
|
||||
0Xffffffff // empty - extra data word
|
||||
};
|
||||
|
||||
__attribute__((section(".ivt"), used)) const uint32_t __ivt[8] = {
|
||||
0x412000d1, // header: 41 - version, 2000 size, d1 tag
|
||||
(uint32_t) __isr_vector, // entry
|
||||
0, // reserved
|
||||
(uint32_t) __ivt_dcd_data, // dcd
|
||||
(uint32_t) __ivt_boot_data, // boot data
|
||||
(uint32_t) __ivt, // this is us - ivt absolute address
|
||||
0, // csf absolute address
|
||||
0, // reserved for HAB
|
||||
};
|
||||
|
||||
#define __FLEXSPI_QSPI_LUT { \
|
||||
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), \
|
||||
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),\
|
||||
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),\
|
||||
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),\
|
||||
[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),\
|
||||
[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),\
|
||||
[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),\
|
||||
[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),\
|
||||
[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),\
|
||||
}
|
||||
|
||||
// MIMXRT1060-EVKB flash chip config: IS25WP064AJBLE
|
||||
__attribute__((section(".cfg"), used))
|
||||
const flexspi_nor_config_t __qspi_flash_cfg = {
|
||||
.memConfig = {.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = 1, // ReadSampleClk_LoopbackFromDqsPad
|
||||
.csHoldTime = 3,
|
||||
.csSetupTime = 3,
|
||||
.controllerMiscOption = BIT(4),
|
||||
.deviceType = 1, // serial NOR
|
||||
.sflashPadType = 4,
|
||||
.serialClkFreq = 7, // 120MHz
|
||||
.sflashA1Size = 8 * 1024 * 1024,
|
||||
.lookupTable = __FLEXSPI_QSPI_LUT},
|
||||
.pageSize = 256,
|
||||
.sectorSize = 4 * 1024,
|
||||
.ipcmdSerialClkFreq = 1,
|
||||
.blockSize = 64 * 1024,
|
||||
.isUniformBlockSize = false};
|
||||
@ -1,356 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
// https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMXRT1060XRM.pdf
|
||||
// https://cache.nxp.com/secured/assets/documents/en/user-guide/MIMXRT1060EVKBUM.pdf
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "MIMXRT1062.h"
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
|
||||
#define PIN(bank, num) ((((bank) - '0') << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
// Use LED for blinking, D8: GPIO_AD_B0_08. GPIO1.8 (schematics, RM)
|
||||
#define LED PIN('1', 8)
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG LPUART1
|
||||
#endif
|
||||
|
||||
// No settable constants, see sysinit.c
|
||||
#define SYS_FREQUENCY 600000000UL
|
||||
|
||||
static inline void spin(volatile uint32_t count) {
|
||||
while (count--) (void) 0;
|
||||
}
|
||||
|
||||
enum { CLOCK_OFF = 0U, CLOCK_ON_RUN = 1U, CLOCK_ON_RUN_WAIT = 3U };
|
||||
static inline void clock_periph(uint32_t index, uint32_t shift, uint32_t val) {
|
||||
volatile uint32_t *r = &CCM->CCGR0;
|
||||
SETBITS(r[index], 3UL << shift, val << shift);
|
||||
}
|
||||
|
||||
// which peripheral feeds the pin
|
||||
static inline void gpio_mux_config(uint16_t index, uint8_t af) {
|
||||
IOMUXC->SW_MUX_CTL_PAD[index] = af;
|
||||
}
|
||||
|
||||
// which pin feeds the peripheral (2nd stage)
|
||||
static inline void periph_mux_config(uint16_t index, uint8_t in) {
|
||||
IOMUXC->SELECT_INPUT[index] = in;
|
||||
}
|
||||
|
||||
enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT };
|
||||
enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_MEDIUM_, GPIO_SPEED_HIGH };
|
||||
enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP };
|
||||
static inline GPIO_Type *gpio_bank(uint16_t pin) {
|
||||
static const GPIO_Type *g[] = {NULL, GPIO1, GPIO2, GPIO3, NULL, GPIO5};
|
||||
return (GPIO_Type *) g[PINBANK(pin)];
|
||||
}
|
||||
|
||||
// pin driver/pull-up/down configuration (ignore "keeper")
|
||||
static inline void gpio_pad_config(uint16_t index, uint8_t type, uint8_t speed,
|
||||
uint8_t pull) {
|
||||
bool dopull = pull > 0;
|
||||
if (dopull) --pull;
|
||||
IOMUXC->SW_PAD_CTL_PAD[index] =
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_ODE(type) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PKE(dopull) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PUS(pull) | IOMUXC_SW_PAD_CTL_PAD_DSE(7);
|
||||
}
|
||||
|
||||
static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint8_t bit = (uint8_t) PINNO(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
|
||||
clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s
|
||||
switch (PINBANK(pin)) {
|
||||
case 1:
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 + bit, type, speed,
|
||||
pull);
|
||||
clock_periph(1, CCM_CCGR1_CG13_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
break;
|
||||
case 2:
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 + bit, type, speed,
|
||||
pull);
|
||||
clock_periph(0, CCM_CCGR0_CG15_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
break;
|
||||
case 3:
|
||||
gpio_mux_config(bit < 12 ? kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 + bit
|
||||
: bit < 18
|
||||
? kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 + bit - 12
|
||||
: kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 + bit - 18,
|
||||
5);
|
||||
gpio_pad_config(bit < 12 ? kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 + bit
|
||||
: bit < 18
|
||||
? kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 + bit - 12
|
||||
: kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 + bit - 18,
|
||||
type, speed, pull);
|
||||
clock_periph(2, CCM_CCGR2_CG13_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
break;
|
||||
case 5:
|
||||
// TODO(): support sw_mux
|
||||
clock_periph(1, CCM_CCGR1_CG15_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
gpio->IMR &= ~mask;
|
||||
if (mode == GPIO_MODE_INPUT) {
|
||||
gpio->GDIR &= ~mask;
|
||||
} else {
|
||||
gpio->GDIR |= mask;
|
||||
}
|
||||
}
|
||||
static inline void gpio_input(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_NONE);
|
||||
}
|
||||
static inline void gpio_output(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
static inline bool gpio_read(uint16_t pin) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
return gpio->DR & mask;
|
||||
}
|
||||
static inline void gpio_write(uint16_t pin, bool value) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
if (value) {
|
||||
gpio->DR |= mask;
|
||||
} else {
|
||||
gpio->DR &= ~mask;
|
||||
}
|
||||
}
|
||||
static inline void gpio_toggle(uint16_t pin) {
|
||||
gpio_write(pin, !gpio_read(pin));
|
||||
}
|
||||
|
||||
// 14.5 Table 14-4: uart_clk_root
|
||||
// see sysinit.c for clocks, (14.7.9: defaults to pll3_80m = PLL3/6/1 = 80MHz)
|
||||
static inline void uart_init(LPUART_Type *uart, unsigned long baud) {
|
||||
uint8_t af = 2; // Alternate function
|
||||
uint16_t mr = 0, pr = 0, mt = 0, pt = 0; // pins
|
||||
uint32_t freq = 80000000; // uart_clk_root frequency
|
||||
if (uart == LPUART1)
|
||||
mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12,
|
||||
pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12,
|
||||
mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13,
|
||||
pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13;
|
||||
if (uart == LPUART3)
|
||||
mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06,
|
||||
pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06,
|
||||
mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07,
|
||||
pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07;
|
||||
|
||||
if (uart == LPUART1) clock_periph(5, CCM_CCGR5_CG12_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
if (uart == LPUART3) clock_periph(0, CCM_CCGR0_CG6_SHIFT, CLOCK_ON_RUN_WAIT);
|
||||
clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s
|
||||
gpio_mux_config(mt, af);
|
||||
gpio_pad_config(pt, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
gpio_mux_config(mr, af);
|
||||
gpio_pad_config(pr, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
|
||||
uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
|
||||
uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
|
||||
SETBITS(uart->BAUD,
|
||||
LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK,
|
||||
LPUART_BAUD_OSR(16 - 1) |
|
||||
LPUART_BAUD_SBR(freq / (16 * baud))); // Rx sample at 16x
|
||||
SETBITS(uart->CTRL,
|
||||
LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
|
||||
LPUART_CTRL_IDLECFG_MASK,
|
||||
LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) |
|
||||
LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit
|
||||
uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
|
||||
}
|
||||
|
||||
static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
|
||||
uart->DATA = byte;
|
||||
while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1);
|
||||
}
|
||||
static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int uart_read_ready(LPUART_Type *uart) {
|
||||
(void) uart;
|
||||
return uart->STAT & LPUART_STAT_RDRF_MASK;
|
||||
}
|
||||
static inline uint8_t uart_read_byte(LPUART_Type *uart) {
|
||||
return (uint8_t) (uart->DATA & 255);
|
||||
}
|
||||
|
||||
static inline void rng_init(void) {
|
||||
clock_periph(6, CCM_CCGR6_CG6_SHIFT, CLOCK_ON_RUN_WAIT); // trng_clk
|
||||
SETBITS(TRNG->MCTL,
|
||||
TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK | TRNG_MCTL_RST_DEF_MASK,
|
||||
TRNG_MCTL_PRGM(1) | TRNG_MCTL_ERR(1) |
|
||||
TRNG_MCTL_RST_DEF(1)); // reset to default values
|
||||
SETBITS(TRNG->MCTL, TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK,
|
||||
TRNG_MCTL_PRGM(0)); // set to run mode
|
||||
(void) TRNG->ENT[TRNG_ENT_COUNT - 1]; // start new entropy generation
|
||||
(void) TRNG->ENT[0]; // defect workaround
|
||||
}
|
||||
static inline uint32_t rng_read(void) {
|
||||
static uint8_t idx = 0;
|
||||
while ((TRNG->MCTL & TRNG_MCTL_ENT_VAL_MASK) == 0) (void) 0;
|
||||
uint32_t data = TRNG->ENT[idx++]; // read data
|
||||
idx %= TRNG_ENT_COUNT; // stay within array limits
|
||||
if (idx == 0) // we've just read TRNG_ENT_COUNT - 1
|
||||
(void) TRNG->ENT[0]; // defect workaround
|
||||
return data;
|
||||
}
|
||||
|
||||
// - PHY has no xtal, XI driven from ENET_REF_CLK1 (labeled as ENET_TX_REF_CLK
|
||||
// (GPIO_AD_B1_10)), generated by the MCU
|
||||
// - PHY RST connected to GPIO1.9 (GPIO_AD_B0_09); INTRP/NAND_TREE connected to
|
||||
// GPIO1.10 (GPIO_AD_B0_10)
|
||||
// - 41.4 REF_CLK1 is RMII mode reference clock for Rx, Tx, and SMI; it is I/O
|
||||
// - 11.3.2 IOMUXC_GPR_GPR1
|
||||
// - bit 13: ENET1_CLK_SEL --> 0 ENET1 TX reference clock driven by
|
||||
// ref_enetpll and output via ENET_REF_CLK1 (labeled as ENET_REF_CLK
|
||||
// elsewhere)
|
||||
// - bit 17: ENET1_TX_CLK_DIR --> 1 ENET1_TX_CLK output driver enabled
|
||||
// - 14.6.1.3.6 Ethernet PLL (PLL6)
|
||||
// - 14.8.14: configure PLL6 to generate 50MHz clocks for ENET and RMII.
|
||||
static inline void ethernet_init(void) {
|
||||
// setup PLL and clock ENET from it
|
||||
SETBITS(CCM_ANALOG->PLL_ENET, CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK,
|
||||
CCM_ANALOG_PLL_ENET_BYPASS_MASK |
|
||||
CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(0)); // bypass to 24MHz osc
|
||||
SETBITS(
|
||||
CCM_ANALOG->PLL_ENET,
|
||||
CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK,
|
||||
CCM_ANALOG_PLL_ENET_DIV_SELECT(1) | CCM_ANALOG_PLL_ENET_ENABLE_MASK);
|
||||
while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
|
||||
spin(1); // wait until it is stable
|
||||
CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK;
|
||||
|
||||
gpio_init(PIN('1', 9), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM, GPIO_PULL_UP); // set GPIO1.9 as GPIO (PHY \RST)
|
||||
gpio_write(PIN('1', 9), 0); // reset PHY
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10,
|
||||
6); // set for ENET_REF_CLK
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10] |=
|
||||
IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT,
|
||||
1); // drive peripheral from B1_10, so RMII clock is taken
|
||||
// from ENET_REF_CLK
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
IOMUXC_GPR->GPR1 |=
|
||||
IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(1); // Set ENET_TX_CLK as output
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04, 3); // set for RXDATA0
|
||||
periph_mux_config(kIOMUXC_ENET0_RXDATA_SELECT_INPUT,
|
||||
1); // drive peripheral from B1_04
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05, 3); // set for RXDATA1
|
||||
periph_mux_config(kIOMUXC_ENET1_RXDATA_SELECT_INPUT,
|
||||
1); // drive peripheral from B1_05
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06, 3); // set for CRS
|
||||
periph_mux_config(kIOMUXC_ENET_RXEN_SELECT_INPUT,
|
||||
1); // drive peripheral from B1_06
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07, 3); // set for TXDATA0
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08, 3); // set for TXDATA1
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09, 3); // set for TXEN
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11, 3); // set for RXERR
|
||||
periph_mux_config(kIOMUXC_ENET_RXERR_SELECT_INPUT,
|
||||
1); // drive peripheral from B1_11
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, 4); // set for MDC
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, 4); // set for MDIO
|
||||
periph_mux_config(kIOMUXC_ENET_MDIO_SELECT_INPUT,
|
||||
1); // drive peripheral from EMC_41
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
|
||||
gpio_init(PIN('1', 10), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_UP); // set GPIO1.10 as GPIO (PHY INTRP/NAND_TREE)
|
||||
gpio_write(PIN('1', 10), 1); // prevent NAND_TREE
|
||||
spin(10000); // keep PHY RST low for a while
|
||||
gpio_write(PIN('1', 9), 1); // deassert RST
|
||||
gpio_init(PIN('1', 10), GPIO_MODE_INPUT, 0, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_UP); // setup IRQ (pulled-up)(not used)
|
||||
|
||||
clock_periph(1, CCM_CCGR1_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enet_ipg_clk
|
||||
NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler
|
||||
}
|
||||
|
||||
// Helper macro for MAC generation, byte reads not allowed
|
||||
#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
|
||||
{ \
|
||||
2, OCOTP->CFG0 & 255, (OCOTP->CFG0 >> 10) & 255, \
|
||||
((OCOTP->CFG0 >> 19) ^ (OCOTP->CFG1 >> 19)) & 255, \
|
||||
(OCOTP->CFG1 >> 10) & 255, OCOTP->CFG1 & 255 \
|
||||
}
|
||||
// NOTE: You can fuse your own MAC and read it from OCOTP->MAC0, OCOTP->MAC1,
|
||||
// OCOTP->MAC2
|
||||
|
||||
static inline void flash_init(void) { // QSPI in FlexSPI
|
||||
// set pins
|
||||
clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05, 1); // set for DQS
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT, 0); // drive peripheral from B1_05
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06, 1); // set for SS
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07, 1); // set for SCLK
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT, 0); // drive peripheral from B1_07
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08, 1); // set for DATA0
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT, 0); // drive peripheral from B1_08
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09, 1); // set for DATA1
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT, 0); // drive peripheral from B1_09
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10, 1); // set for DATA2
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT, 0); // drive peripheral from B1_10
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11, 1); // set for DATA3
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT, 0); // drive peripheral from B1_11
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
// set FlexSPI clock
|
||||
SETBITS(CCM->CSCMR1, CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK | CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_CSCMR1_FLEXSPI_CLK_SEL(3) | CCM_CSCMR1_FLEXSPI_PODF(7)); // select PLL3 PFD0 /8
|
||||
clock_periph(6, CCM_CCGR6_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enable
|
||||
}
|
||||
@ -1,22 +0,0 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash_hdr(rx) : ORIGIN = 0x60000000, LENGTH = 8k
|
||||
flash_irq(rx) : ORIGIN = 0x60002000, LENGTH = 1k
|
||||
flash_code(rx) : ORIGIN = 0x60002400, LENGTH = 8183k
|
||||
|
||||
itcram(rx) : ORIGIN = 0x00000000, LENGTH = 128k
|
||||
dtcram(rw) : ORIGIN = 0x20000000, LENGTH = 128k
|
||||
ocram(rw) : ORIGIN = 0x20200000, LENGTH = 256k /* Is this cached ? */
|
||||
}
|
||||
__StackTop = ORIGIN(dtcram) + LENGTH(dtcram);
|
||||
|
||||
SECTIONS {
|
||||
.hdr : { FILL(0xff) ; KEEP(*(.cfg)) . = 0x1000 ; KEEP(*(.ivt)) . = 0x1020 ;
|
||||
KEEP(*(.dat)) . = 0x1030 ; KEEP(*(.dcd)) . = 0x2000 ;} >flash_hdr
|
||||
.irq : { KEEP(*(.isr_vector)) } > flash_irq
|
||||
.text : { *(.text* .text.*) *(.rodata*) ; } > flash_code
|
||||
.data : { __data_start__ = .; *(.data SORT(.data.*)) __data_end__ = .; } > dtcram AT > flash_code
|
||||
__etext = LOADADDR(.data);
|
||||
.bss : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > dtcram
|
||||
_end = .;
|
||||
}
|
||||
@ -1,83 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
#include "mongoose.h"
|
||||
#include "net.h"
|
||||
|
||||
#define BLINK_PERIOD_MS 1000 // LED blinking period in millis
|
||||
|
||||
// workaround optimizer somehow causing SysTick to fire before FreeRTOS has
|
||||
// fully initialized
|
||||
extern void xPortSysTickHandler(void);
|
||||
void SysTick_Handler(void) {
|
||||
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
|
||||
xPortSysTickHandler();
|
||||
}
|
||||
|
||||
bool mg_random(void *buf, size_t len) { // Use on-board RNG
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void timer_fn(void *arg) {
|
||||
struct mg_tcpip_if *ifp = arg; // And show
|
||||
const char *names[] = {"down", "up", "req", "ready"}; // network stats
|
||||
MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u",
|
||||
names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent,
|
||||
ifp->ndrop, ifp->nerr));
|
||||
}
|
||||
|
||||
static void server(void *args) {
|
||||
struct mg_mgr mgr; // Initialise Mongoose event manager
|
||||
mg_mgr_init(&mgr); // and attach it to the interface
|
||||
mg_log_set(MG_LL_DEBUG); // Set log level
|
||||
|
||||
// Initialise Mongoose network stack
|
||||
ethernet_init();
|
||||
struct mg_tcpip_driver_imxrt_data driver_data = {.mdc_cr = 24, .phy_addr = 2};
|
||||
struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
|
||||
// Uncomment below for static configuration:
|
||||
// .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
|
||||
// .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
|
||||
// .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
|
||||
.driver = &mg_tcpip_driver_imxrt,
|
||||
.driver_data = &driver_data};
|
||||
mg_tcpip_init(&mgr, &mif);
|
||||
mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
|
||||
|
||||
MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac));
|
||||
while (mif.state != MG_TCPIP_STATE_READY) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
MG_INFO(("Initialising application..."));
|
||||
web_init(&mgr);
|
||||
|
||||
MG_INFO(("Starting event loop"));
|
||||
for (;;) mg_mgr_poll(&mgr, 1); // Infinite event loop
|
||||
(void) args;
|
||||
}
|
||||
|
||||
static void blinker(void *args) {
|
||||
gpio_output(LED); // Setup blue LED
|
||||
for (;;) {
|
||||
gpio_toggle(LED);
|
||||
vTaskDelay(pdMS_TO_TICKS(BLINK_PERIOD_MS));
|
||||
}
|
||||
(void) args;
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
uart_init(UART_DEBUG, 115200); // Initialise UART
|
||||
|
||||
// Start tasks. NOTE: stack sizes are in 32-bit words
|
||||
xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL);
|
||||
xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL);
|
||||
|
||||
vTaskStartScheduler(); // This blocks
|
||||
return 0;
|
||||
}
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.c
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.h
|
||||
@ -1,13 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
#include <errno.h> // we are not using lwIP
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_FREERTOS
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_DRIVER_IMXRT 1
|
||||
#define MG_IO_SIZE 256
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.c
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.h
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/packed_fs.c
|
||||
@ -1,85 +0,0 @@
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
int _fstat(int fd, struct stat *st) {
|
||||
if (fd < 0) return -1;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
extern char _end;
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
if (heap == NULL) heap = (unsigned char *) &_end;
|
||||
prev_heap = heap;
|
||||
heap += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int mkdir(const char *path, mode_t mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _init(void) {}
|
||||
@ -1,79 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// This file contains essentials required by the CMSIS:
|
||||
// uint32_t SystemCoreClock - holds the system core clock value
|
||||
// SystemInit() - initialises the system, e.g. sets up clocks
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
uint32_t SystemCoreClock = SYS_FREQUENCY;
|
||||
|
||||
// - 14.4, Figure 14-2: clock tree
|
||||
// - 14.7.4: ARM_PODF defaults to /2; 9.5.3 Table 9-7: ROM agrees
|
||||
// - 14.7.5: AHB_PODF defaults to /1; IPG_PODF defaults to /4; PERIPH_CLK_SEL
|
||||
// defaults to derive clock from pre_periph_clk_sel
|
||||
// - 9.5.3 Table 9-7: ROM changes IPG_PODF to /3
|
||||
// - 14.7.6: PRE_PERIPH_CLK_SEL defaults to derive clock from divided
|
||||
// PLL1; 9.5.3 Table 9-7: ROM agrees
|
||||
// - (For 528MHz operation, we need to set it to derive clock from PLL2)
|
||||
// - 14.7.7: PER_CLK defaults to IPG/1; 9.5.3 Table 9-7: ROM changes it to IPG/2
|
||||
// - 14.6.1.3.1 ARM PLL (PLL1); 13.3.2.2 PLLs
|
||||
// - 14.8.1: PLL1 is powered off and bypassed to 24MHz. Fout = 24MHz *
|
||||
// div_select/2
|
||||
// - 9.5.3 Table 9-7: ROM enables this PLL and sets it up
|
||||
// - For 600MHz operation, we need to set PLL1 on
|
||||
// - Datasheet 4.1.3: System frequency/Bus frequency max 600/150MHz respectively
|
||||
// (AHB/IPG)
|
||||
// - MCUXpresso: IPG_CLK_ROOT <= 150MHz; PERCLK_CLK_ROOT <= 75MHz
|
||||
// - Datasheet 4.9.4.1.1/2: the processor clock frequency must exceed twice the
|
||||
// ENET_RX_CLK/ENET_TX_CLK frequency.
|
||||
// - Datasheet 4.9.4.2: no details for RMII (above is for MII), assumed 50MHz
|
||||
// min processor clock
|
||||
// - Datasheet 4.1.3, Table 10: "Overdrive" run mode requires 1.25V core voltage
|
||||
// minimum; 528 MHz does not.
|
||||
void SystemInit(void) { // Called automatically by startup code (ints masked)
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
asm("DSB");
|
||||
asm("ISB");
|
||||
// 58.4.2: Disable watchdog after reset (unlocked)
|
||||
RTWDOG->CS &= ~RTWDOG_CS_EN_MASK;
|
||||
RTWDOG->TOVAL = 0xFFFF;
|
||||
while (RTWDOG->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock
|
||||
while ((RTWDOG->CS & RTWDOG_CS_RCS_MASK) == 0)
|
||||
spin(1); // wait for new config
|
||||
// Set VDD_SOC to 1.25V
|
||||
SETBITS(DCDC->REG3, DCDC_REG3_TRG_MASK, DCDC_REG3_TRG(0x12));
|
||||
while ((DCDC->REG0 & DCDC_REG0_STS_DC_OK_MASK) == 0)
|
||||
spin(1); // Wait for DCDC_STS_DC_OK
|
||||
// ROM fiddles with AHB divider, wait and then keep bits at 0 (expected)
|
||||
while (CCM->CDHIPR & CCM_CDHIPR_AHB_PODF_BUSY_MASK) spin(1);
|
||||
SETBITS(CCM->CBCDR, CCM_CBCDR_IPG_PODF_MASK | CCM_CBCDR_AHB_PODF_MASK,
|
||||
CCM_CBCDR_IPG_PODF(3)); // keep AHB, set IPG divider /4 (150MHz)
|
||||
SETBITS(CCM->CSCMR1, CCM_CSCMR1_PERCLK_PODF_MASK,
|
||||
CCM_CSCMR1_PERCLK_PODF(1)); // Set PERCLK divider /2 (75MHz)
|
||||
// Set clock to 600 MHz. Power PLL on and configure divider (ROM boot code
|
||||
// fiddles with the PLL, bypass first)
|
||||
CCM_ANALOG->PLL_ARM |= CCM_ANALOG_PLL_ARM_BYPASS_MASK;
|
||||
SETBITS(CCM_ANALOG->PLL_ARM,
|
||||
CCM_ANALOG_PLL_ARM_POWERDOWN_MASK |
|
||||
CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK,
|
||||
CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(100));
|
||||
while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0)
|
||||
spin(1); // wait until it is stable
|
||||
CCM_ANALOG->PLL_ARM &=
|
||||
~CCM_ANALOG_PLL_ARM_BYPASS_MASK; // Disable Bypass (switch to PLL)
|
||||
// 14.5 Table 14-4: uart_clk_root
|
||||
// 14.4: uart_clk_root = PLL3/6 or OSC; CCM_CSCDR1 (14.7.9) defaults to
|
||||
// PLL3/6/1; but ROM boot code fiddles with the divider (9.5.3 Table 9-7)
|
||||
CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_POWER_MASK; // Power PLL on
|
||||
while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0)
|
||||
spin(1); // wait until it is stable
|
||||
CCM_ANALOG->PLL_USB1 &=
|
||||
~CCM_ANALOG_PLL_USB1_BYPASS_MASK; // Disable Bypass (switch to PLL)
|
||||
CCM->CSCDR1 &=
|
||||
~(CCM_CSCDR1_UART_CLK_SEL_MASK | CCM_CSCDR1_UART_CLK_PODF_MASK);
|
||||
rng_init(); // Initialise random number generator
|
||||
// NXP startup code calls SystemInit BEFORE initializing RAM...
|
||||
SysTick_Config(SYS_FREQUENCY / 1000); // Sys tick every 1ms
|
||||
}
|
||||
@ -1,38 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configCPU_CLOCK_HZ SYS_FREQUENCY
|
||||
#define configTICK_RATE_HZ 1000
|
||||
#define configMAX_PRIORITIES 5
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TIMERS 0
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configUSE_MALLOC_FAILED_HOOK 0
|
||||
#define configMINIMAL_STACK_SIZE 128
|
||||
#define configTOTAL_HEAP_SIZE (1024 * 32)
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_xTaskGetSchedulerState 1 // trying
|
||||
|
||||
#ifdef __NVIC_PRIO_BITS
|
||||
#define configPRIO_BITS __NVIC_PRIO_BITS
|
||||
#else
|
||||
#define configPRIO_BITS 4
|
||||
#endif
|
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
|
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
|
||||
#define configKERNEL_INTERRUPT_PRIORITY \
|
||||
(configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
|
||||
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY \
|
||||
(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
|
||||
|
||||
#define configASSERT(expr) \
|
||||
if (!(expr)) printf("FAILURE %s:%d: %s\n", __FILE__, __LINE__, #expr)
|
||||
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
//#define xPortSysTickHandler SysTick_Handler
|
||||
@ -1,86 +1,29 @@
|
||||
CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
|
||||
CFLAGS += -Wformat-truncation -fno-common -Wconversion
|
||||
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
|
||||
CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MIMXRT1176
|
||||
CFLAGS += -Icmsis_mcu/devices/MIMXRT1176/drivers -DCPU_MIMXRT1176DVMAA_cm7
|
||||
CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
|
||||
CFLAGS += -Wno-conversion -Wno-unused-parameter # due to NXP FSL code
|
||||
LDSCRIPT = link.ld
|
||||
LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
|
||||
BOARD = rt1170
|
||||
IDE = GCC+make
|
||||
RTOS = FreeRTOS
|
||||
WIZARD_URL ?= http://mongoose.ws/wizard
|
||||
|
||||
SOURCES = main.c syscalls.c sysinit.c
|
||||
SOURCES += cmsis_mcu/devices/MIMXRT1176/gcc/startup_MIMXRT1176_cm7.S # NXP startup file. Compiler-dependent!
|
||||
SOURCES += cmsis_mcu/devices/MIMXRT1176/drivers/fsl_clock.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_anatop_ai.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_pmu.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_dcdc.c cmsis_mcu/devices/MIMXRT1176/drivers/fsl_common_arm.c # NXP support files
|
||||
CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS # Make startup code work as expected
|
||||
|
||||
# FreeRTOS. RT1170 has a Cortex-M7 r1p2 core, FreeRTOS recommends using CM4F port for non-r0p1 CM7 micros
|
||||
SOURCES += FreeRTOS-Kernel/portable/MemMang/heap_4.c
|
||||
SOURCES += FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c
|
||||
CFLAGS += -IFreeRTOS-Kernel/include
|
||||
CFLAGS += -IFreeRTOS-Kernel/portable/GCC/ARM_CM4F -Wno-conversion
|
||||
|
||||
# Mongoose options are defined in mongoose_config.h
|
||||
SOURCES += mongoose.c net.c packed_fs.c
|
||||
|
||||
# Example specific build options. See README.md
|
||||
CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\"
|
||||
|
||||
ifeq ($(OS),Windows_NT)
|
||||
RM = cmd /C del /Q /F /S
|
||||
else
|
||||
RM = rm -rf
|
||||
endif
|
||||
|
||||
all build example update: SOURCES += flash_image.c
|
||||
all build example: firmware.bin
|
||||
|
||||
ram: LDSCRIPT = link_ram.ld
|
||||
ram: firmware.bin
|
||||
firmware.bin: wizard
|
||||
make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./
|
||||
|
||||
firmware.bin: firmware.elf
|
||||
arm-none-eabi-objcopy -O binary $< $@
|
||||
wizard:
|
||||
hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
|
||||
&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
|
||||
unzip wizard.zip
|
||||
cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h
|
||||
|
||||
firmware.elf: FreeRTOS-Kernel cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld link.ld Makefile mongoose_config.h
|
||||
arm-none-eabi-gcc $(SOURCES) $(wildcard FreeRTOS-Kernel/*.c) $(CFLAGS) $(LDFLAGS) -o $@
|
||||
arm-none-eabi-size $@
|
||||
|
||||
flash: firmware.bin
|
||||
# flash
|
||||
|
||||
cmsis_core: # ARM CMSIS core headers
|
||||
git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
|
||||
cmsis_mcu:
|
||||
curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1176_DFP.18.0.0.pack -o $@.zip
|
||||
mkdir $@ && cd $@ && unzip -q ../$@.zip
|
||||
FreeRTOS-Kernel: # FreeRTOS sources
|
||||
git clone --depth 1 -b V10.5.0 https://github.com/FreeRTOS/FreeRTOS-Kernel $@
|
||||
|
||||
# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
|
||||
DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/15
|
||||
update: firmware.bin
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
|
||||
|
||||
update updateram: CFLAGS += -DUART_DEBUG=LPUART2
|
||||
|
||||
test update: CFLAGS_EXTRA ="-DUART_DEBUG=LPUART2"
|
||||
test: update
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt
|
||||
grep 'READY, IP:' /tmp/output.txt # Check for network init
|
||||
|
||||
|
||||
updateram: ram
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @firmware.bin
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}'
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1"}'
|
||||
PC=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,4"}' | jq -r .resp[5:]` && \
|
||||
SP=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,0"}' | jq -r .resp[5:]` && \
|
||||
REQ="wm,e000ed08,0 wr,d,$$SP wr,f,$$PC" && \
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"'"$$REQ"'"}'
|
||||
curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0001"}'
|
||||
|
||||
testram: updateram
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
|
||||
grep 'READY, IP:' /tmp/output.txt # Check for network init
|
||||
|
||||
|
||||
clean:
|
||||
$(RM) firmware.* *.su cmsis_core cmsis_mcu FreeRTOS-Kernel *.zip
|
||||
rm -rf firmware.* wizard*
|
||||
|
||||
1
examples/nxp/rt1170-evk-make-freertos-builtin/README.md
Normal file
1
examples/nxp/rt1170-evk-make-freertos-builtin/README.md
Normal file
@ -0,0 +1 @@
|
||||
See [Wizard](https://mongoose.ws/wizard/#/output?board=rt1020&ide=GCC+make&rtos=FreeRTOSbaremetal&file=README.md)
|
||||
@ -1 +0,0 @@
|
||||
../rt1170-evk-make-baremetal-builtin/dcd.h
|
||||
@ -1 +0,0 @@
|
||||
../rt1170-evk-make-baremetal-builtin/flash_image.c
|
||||
@ -1,337 +0,0 @@
|
||||
// Copyright (c) 2024 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
// https://www.nxp.com/webapp/Download?colCode=IMXRT1170RM
|
||||
// https://www.nxp.com/webapp/Download?colCode=MIMXRT1170EVKBHUG
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "MIMXRT1176_cm7.h"
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
|
||||
#define PIN(bank, num) ((((bank) - '0') << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
// Use LED for blinking, D6: GPIO_AD_04. GPIO3.3 (schematics, RM)
|
||||
#define LED PIN('3', 3)
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG LPUART1
|
||||
#endif
|
||||
|
||||
// No settable constants, see sysinit.c
|
||||
#define SYS_FREQUENCY 996000000UL
|
||||
|
||||
static inline void spin(volatile uint32_t count) {
|
||||
while (count--) (void) 0;
|
||||
}
|
||||
|
||||
// Use "Unassigned/Domain Mode"
|
||||
static inline void clock_periph(uint32_t index, bool val) {
|
||||
CCM->LPCG[index].DIRECT = val ? 1 : 0; // (15.9.1.25)
|
||||
}
|
||||
|
||||
// which peripheral feeds the pin
|
||||
static inline void gpio_mux_config(uint16_t index, uint8_t af) {
|
||||
IOMUXC->SW_MUX_CTL_PAD[index] = af;
|
||||
}
|
||||
|
||||
// which pin feeds the peripheral (2nd stage)
|
||||
static inline void periph_mux_config(uint16_t index, uint8_t in) {
|
||||
IOMUXC->SELECT_INPUT[index] = in;
|
||||
}
|
||||
|
||||
// CM7_GPIOx not supported
|
||||
enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT };
|
||||
enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_MEDIUM_, GPIO_SPEED_HIGH };
|
||||
enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
|
||||
static inline GPIO_Type *gpio_bank(uint16_t pin) {
|
||||
static const GPIO_Type *g[] = {NULL, GPIO1, GPIO2, GPIO3, GPIO4,
|
||||
GPIO5, GPIO6, GPIO7, GPIO8, GPIO9,
|
||||
GPIO10, GPIO11, GPIO12, GPIO13};
|
||||
return (GPIO_Type *) g[PINBANK(pin)];
|
||||
}
|
||||
|
||||
// pin driver/pull-up/down configuration (allow both cores)
|
||||
static inline void gpio_pad_config(uint16_t index, uint8_t type, uint8_t speed,
|
||||
uint8_t pull) {
|
||||
if (index < kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 ||
|
||||
(index >= kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 &&
|
||||
index < kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00)) {
|
||||
IOMUXC->SW_PAD_CTL_PAD[index] =
|
||||
IOMUXC_SW_PAD_CTL_PAD_PDRV(speed == GPIO_SPEED_LOW) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_ODE(type) | IOMUXC_SW_PAD_CTL_PAD_PULL(pull);
|
||||
} else {
|
||||
bool dopull = pull > 0;
|
||||
if (dopull) pull = (pull == GPIO_PULL_UP);
|
||||
IOMUXC->SW_PAD_CTL_PAD[index] =
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(speed != GPIO_SPEED_LOW) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_ODE(type) | IOMUXC_SW_PAD_CTL_PAD_PUE(dopull) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PUS(pull) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint8_t bit = (uint8_t) PINNO(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
|
||||
clock_periph(51, 1); // clk_enable_gpio (15.5.4 Table 15-5)
|
||||
clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
|
||||
switch (PINBANK(pin)) { // (11.1.1 Table 11-1)
|
||||
case 1:
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 + bit, type, speed,
|
||||
pull);
|
||||
break;
|
||||
case 2:
|
||||
IOMUXC_GPR->GPR40 = 0; // select GPIO2
|
||||
IOMUXC_GPR->GPR41 = 0; // select GPIO2
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 + bit, type, speed,
|
||||
pull);
|
||||
break;
|
||||
case 3:
|
||||
IOMUXC_GPR->GPR42 = 0; // select GPIO3
|
||||
IOMUXC_GPR->GPR43 = 0; // select GPIO3
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 + bit, type, speed,
|
||||
pull);
|
||||
break;
|
||||
case 4:
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 + bit, 5);
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 + bit, type, speed,
|
||||
pull);
|
||||
break;
|
||||
default:
|
||||
// TODO(): support GPIO5-13, 10-15 requires redefinition of PIN() macro
|
||||
break;
|
||||
}
|
||||
|
||||
gpio->IMR &= ~mask;
|
||||
if (mode == GPIO_MODE_INPUT) {
|
||||
gpio->GDIR &= ~mask;
|
||||
} else {
|
||||
gpio->GDIR |= mask;
|
||||
}
|
||||
}
|
||||
static inline void gpio_input(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_NONE);
|
||||
}
|
||||
static inline void gpio_output(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
static inline bool gpio_read(uint16_t pin) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
return gpio->DR & mask;
|
||||
}
|
||||
static inline void gpio_write(uint16_t pin, bool value) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
if (value) {
|
||||
gpio->DR |= mask;
|
||||
} else {
|
||||
gpio->DR &= ~mask;
|
||||
}
|
||||
}
|
||||
static inline void gpio_toggle(uint16_t pin) {
|
||||
gpio_write(pin, !gpio_read(pin));
|
||||
}
|
||||
|
||||
// 15.3 Table 15-2: uart_clk_root
|
||||
// 15.4: lpuart*_clk_root 15.5.3 Table 15-4; 15.9.1.2; select OSC_24M
|
||||
static inline void uart_init(LPUART_Type *uart, unsigned long baud) {
|
||||
uint8_t af = 0; // Alternate function
|
||||
uint16_t mr = 0, pr = 0, mt = 0, pt = 0; // pins
|
||||
uint32_t freq = 24000000; // uart_clk_root frequency
|
||||
if (uart == LPUART1) {
|
||||
af = 0;
|
||||
mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24;
|
||||
pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24;
|
||||
mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25;
|
||||
pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25;
|
||||
// configure clock root source and divisor /1, enable peripheral clock
|
||||
CCM->CLOCK_ROOT[25].CONTROL =
|
||||
CCM_CLOCK_ROOT_CONTROL_MUX(1) | CCM_CLOCK_ROOT_CONTROL_DIV(0);
|
||||
clock_periph(86, 1); // (15.5.4 Table 15-5)
|
||||
periph_mux_config(kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT, 0);
|
||||
periph_mux_config(kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT, 0);
|
||||
} else if (uart == LPUART2) {
|
||||
af = 2;
|
||||
mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10;
|
||||
pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10;
|
||||
mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11;
|
||||
pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11;
|
||||
CCM->CLOCK_ROOT[26].CONTROL =
|
||||
CCM_CLOCK_ROOT_CONTROL_MUX(1) | CCM_CLOCK_ROOT_CONTROL_DIV(0);
|
||||
clock_periph(87, 1); // (15.5.4 Table 15-5)
|
||||
}
|
||||
clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
|
||||
gpio_mux_config(mt, af);
|
||||
gpio_pad_config(pt, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_NONE);
|
||||
gpio_mux_config(mr, af);
|
||||
gpio_pad_config(pr, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
|
||||
uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
|
||||
uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
|
||||
uart->BAUD = LPUART_BAUD_OSR(16 - 1) |
|
||||
LPUART_BAUD_SBR(freq / (16 * baud)); // Rx sample at 16x
|
||||
uart->CTRL = LPUART_CTRL_IDLECFG(1) |
|
||||
LPUART_CTRL_ILT(1); // no parity, idle 2 chars after 1 stop bit
|
||||
uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
|
||||
}
|
||||
|
||||
static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
|
||||
uart->DATA = byte;
|
||||
while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1);
|
||||
}
|
||||
static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int uart_read_ready(LPUART_Type *uart) {
|
||||
(void) uart;
|
||||
return uart->STAT & LPUART_STAT_RDRF_MASK;
|
||||
}
|
||||
static inline uint8_t uart_read_byte(LPUART_Type *uart) {
|
||||
return (uint8_t) (uart->DATA & 255);
|
||||
}
|
||||
|
||||
|
||||
static inline void lpsr_mux_config(uint16_t index, uint8_t af) {
|
||||
IOMUXC_LPSR->SW_MUX_CTL_PAD[index] = af;
|
||||
}
|
||||
|
||||
static inline void lpsr_pad_config(uint16_t index, uint8_t type, uint8_t speed,
|
||||
uint8_t pull) {
|
||||
bool dopull = pull > 0;
|
||||
if (dopull) pull = (pull == GPIO_PULL_UP);
|
||||
IOMUXC_LPSR->SW_PAD_CTL_PAD[index] =
|
||||
IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(speed != GPIO_SPEED_LOW) |
|
||||
IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(type) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PUE(dopull) | IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(pull) |
|
||||
IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH);
|
||||
}
|
||||
|
||||
#include "fsl_clock.h"
|
||||
|
||||
// - 15.4 clock tree
|
||||
// - 15.3 Table 15-2: ENET1_CLK_ROOT <= 50MHz
|
||||
// - PHY has no xtal, XI driven from ENET_REF_CLK (labeled as ENET_TX_REF_CLK
|
||||
// (GPIO_DISP_B2_05)), generated by the MCU
|
||||
// - PHY RST connected to GPIO12.12 (GPIO_LPSR_12);
|
||||
// - 60.4 REF_CLK is RMII mode reference clock for Rx, Tx, and SMI; it is I/O
|
||||
static inline void ethernet_init(void) {
|
||||
const clock_sys_pll1_config_t pll1 = {.pllDiv2En = true};
|
||||
CLOCK_InitSysPll1(&pll1); // setup PLL1 and clock ENET from it
|
||||
// configure clock root source PLL1/2 and divisor /10, enable peripheral clock
|
||||
CCM->CLOCK_ROOT[51].CONTROL =
|
||||
CCM_CLOCK_ROOT_CONTROL_MUX(4) | CCM_CLOCK_ROOT_CONTROL_DIV(10 - 1);
|
||||
clock_periph(112, 1); // clk_enable_enet (15.5.4 Table 15-5)
|
||||
|
||||
clock_periph(51, 1); // clk_enable_gpio (15.5.4 Table 15-5)
|
||||
clock_periph(50, 1); // clk_enable_iomuxc_lpsr (15.5.4 Table 15-5)
|
||||
clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
|
||||
lpsr_mux_config(kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12,
|
||||
10); // set GPIO12.12 as GPIO (PHY \RST)
|
||||
lpsr_pad_config(kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12,
|
||||
GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
GPIO12->IMR &= ~BIT(12);
|
||||
GPIO12->GDIR |= BIT(12);
|
||||
GPIO12->DR &= ~BIT(12); // reset PHY
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05,
|
||||
2); // set for ENET_REF_CLK
|
||||
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05] |=
|
||||
IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin
|
||||
periph_mux_config(kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT,
|
||||
1); // drive peripheral from DISP_B2_05, so RMII clock is
|
||||
// taken from ENET_REF_CLK
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
IOMUXC_GPR->GPR4 |=
|
||||
IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(1); // Set ENET_REF_CLK as output
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06,
|
||||
1); // set for RXDATA0
|
||||
periph_mux_config(kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0,
|
||||
1); // drive peripheral from DISP_B2_06
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07,
|
||||
1); // set for RXDATA1
|
||||
periph_mux_config(kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1,
|
||||
1); // drive peripheral from DISP_B2_07
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08, 1); // set for CRS
|
||||
periph_mux_config(kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT,
|
||||
1); // drive peripheral from DISP_B2_08
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09, 1); // set for RXERR
|
||||
periph_mux_config(kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT,
|
||||
1); // drive peripheral from DISP_B2_09
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_DOWN);
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02,
|
||||
1); // set for TXDATA0
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03,
|
||||
1); // set for TXDATA1
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04, 1); // set for TXEN
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_HIGH, GPIO_PULL_NONE);
|
||||
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32, 3); // set for MDC
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM, GPIO_PULL_NONE);
|
||||
gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33, 3); // set for MDIO
|
||||
periph_mux_config(kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT,
|
||||
1); // drive peripheral from AD_33
|
||||
gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33, GPIO_OTYPE_PUSH_PULL,
|
||||
GPIO_SPEED_MEDIUM, GPIO_PULL_UP);
|
||||
|
||||
IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_ENET_MASK; // ERR050396
|
||||
gpio_init(PIN('3', 11), GPIO_MODE_INPUT, 0, GPIO_SPEED_MEDIUM,
|
||||
GPIO_PULL_UP); // setup IRQ (pulled-up)(not used)
|
||||
spin(10000); // keep PHY RST low for a while
|
||||
GPIO12->DR |= BIT(12); // deassert RST
|
||||
|
||||
clock_periph(112, 1); // clk_enable_enet (15.5.4 Table 15-5)
|
||||
NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler
|
||||
}
|
||||
|
||||
// Helper macro for MAC generation, byte reads not allowed
|
||||
#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
|
||||
{ \
|
||||
2, OCOTP->FUSEN[16].FUSE & 255, (OCOTP->FUSEN[16].FUSE >> 10) & 255, \
|
||||
((OCOTP->FUSEN[16].FUSE >> 19) ^ (OCOTP->FUSEN[17].FUSE >> 19)) & 255, \
|
||||
(OCOTP->FUSEN[17].FUSE >> 10) & 255, OCOTP->FUSEN[17].FUSE & 255 \
|
||||
}
|
||||
|
||||
static inline void flash_init(void) { // QSPI in FlexSPI
|
||||
// set pins
|
||||
clock_periph(49, 1); // clk_enable_iomuxc (15.5.4 Table 15-5)
|
||||
#if 0
|
||||
#endif
|
||||
}
|
||||
@ -1,24 +0,0 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash_hdr(rx) : ORIGIN = 0x30000000, LENGTH = 8k
|
||||
flash_irq(rx) : ORIGIN = 0x30002000, LENGTH = 1k
|
||||
flash_code(rx) : ORIGIN = 0x30002400, LENGTH = 65527k
|
||||
|
||||
itcram(rx) : ORIGIN = 0x00000000, LENGTH = 256k
|
||||
dtcram(rw) : ORIGIN = 0x20000000, LENGTH = 256k
|
||||
ocram(rw) : ORIGIN = 0x20240000, LENGTH = 512k /* Is this cached ? */
|
||||
}
|
||||
__StackTop = ORIGIN(dtcram) + LENGTH(dtcram);
|
||||
|
||||
/* TODO(): separate itcram and go back to using dtcram for data and bss when ota is finished */
|
||||
|
||||
SECTIONS {
|
||||
.hdr : { FILL(0xff) ; . = 0x400 ; KEEP(*(.cfg)) . = 0x1000 ; KEEP(*(.ivt)) . = 0x1020 ;
|
||||
KEEP(*(.dat)) . = 0x1030 ; KEEP(*(.dcd)) . = 0x2000 ;} >flash_hdr
|
||||
.irq : { KEEP(*(.isr_vector)) } > flash_irq
|
||||
.text : { *(.text* .text.*) *(.rodata*) ; } > flash_code
|
||||
.data : { __data_start__ = .; *(.data SORT(.data.*)) *(.iram) __data_end__ = .; } > itcram AT > flash_code
|
||||
__etext = LOADADDR(.data);
|
||||
.bss : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > itcram
|
||||
_end = .;
|
||||
}
|
||||
@ -1,76 +0,0 @@
|
||||
// Copyright (c) 2024 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
#include "mongoose.h"
|
||||
#include "net.h"
|
||||
|
||||
#define BLINK_PERIOD_MS 1000 // LED blinking period in millis
|
||||
|
||||
// workaround optimizer somehow causing SysTick to fire before FreeRTOS has
|
||||
// fully initialized
|
||||
extern void xPortSysTickHandler(void);
|
||||
void SysTick_Handler(void) {
|
||||
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
|
||||
xPortSysTickHandler();
|
||||
}
|
||||
|
||||
static void timer_fn(void *arg) {
|
||||
struct mg_tcpip_if *ifp = arg; // And show
|
||||
const char *names[] = {"down", "up", "req", "ready"}; // network stats
|
||||
MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u",
|
||||
names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent,
|
||||
ifp->ndrop, ifp->nerr));
|
||||
}
|
||||
|
||||
static void server(void *args) {
|
||||
struct mg_mgr mgr; // Initialise Mongoose event manager
|
||||
mg_mgr_init(&mgr); // and attach it to the interface
|
||||
mg_log_set(MG_LL_DEBUG); // Set log level
|
||||
|
||||
// Initialise Mongoose network stack
|
||||
ethernet_init(); // Initialise ethernet pins
|
||||
struct mg_tcpip_driver_imxrt_data driver_data = {.mdc_cr = 24, .phy_addr = 3};
|
||||
struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
|
||||
// Uncomment below for static configuration:
|
||||
// .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
|
||||
// .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
|
||||
// .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
|
||||
.driver = &mg_tcpip_driver_imxrt,
|
||||
.driver_data = &driver_data};
|
||||
mg_tcpip_init(&mgr, &mif);
|
||||
mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
|
||||
|
||||
MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac));
|
||||
while (mif.state != MG_TCPIP_STATE_READY) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
MG_INFO(("Initialising application..."));
|
||||
web_init(&mgr);
|
||||
|
||||
MG_INFO(("Starting event loop"));
|
||||
for (;;) mg_mgr_poll(&mgr, 1); // Infinite event loop
|
||||
(void) args;
|
||||
}
|
||||
|
||||
static void blinker(void *args) {
|
||||
gpio_output(LED); // Setup blue LED
|
||||
for (;;) {
|
||||
gpio_toggle(LED);
|
||||
vTaskDelay(pdMS_TO_TICKS(BLINK_PERIOD_MS));
|
||||
}
|
||||
(void) args;
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
uart_init(UART_DEBUG, 115200); // Initialise UART
|
||||
|
||||
// Start tasks. NOTE: stack sizes are in 32-bit words
|
||||
xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL);
|
||||
xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL);
|
||||
|
||||
vTaskStartScheduler(); // This blocks
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.c
|
||||
@ -1 +0,0 @@
|
||||
../../../mongoose.h
|
||||
@ -1,14 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
#include <errno.h> // we are not using lwIP
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_FREERTOS
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_DRIVER_IMXRT 1
|
||||
#define MG_DRIVER_IMXRT_RT11 1
|
||||
#define MG_ENABLE_TCPIP_DRIVER_INIT 0
|
||||
#define MG_IO_SIZE 256
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
#define MG_ENABLE_TCPIP_PRINT_DEBUG_STATS 1
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.c
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/net.h
|
||||
@ -1 +0,0 @@
|
||||
../../device-dashboard/packed_fs.c
|
||||
@ -1,85 +0,0 @@
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
int _fstat(int fd, struct stat *st) {
|
||||
if (fd < 0) return -1;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
extern char _end;
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
if (heap == NULL) heap = (unsigned char *) &_end;
|
||||
prev_heap = heap;
|
||||
heap += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int mkdir(const char *path, mode_t mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _init(void) {}
|
||||
@ -1,48 +0,0 @@
|
||||
// Copyright (c) 2024 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// This file contains essentials required by the CMSIS:
|
||||
// uint32_t SystemCoreClock - holds the system core clock value
|
||||
// SystemInit() - initialises the system, e.g. sets up clocks
|
||||
|
||||
#include "hal.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "fsl_dcdc.h"
|
||||
#include "fsl_pmu.h"
|
||||
|
||||
uint32_t SystemCoreClock = SYS_FREQUENCY;
|
||||
|
||||
// - 15.4 clock tree
|
||||
// 15.4: M7_CLK_ROOT
|
||||
// 15.5.3 Table 15-4; 15.9.1.2; select PLL_ARM_CLK
|
||||
// 15.8.2 PLL Enable Sequence
|
||||
// - Datasheet 4.1.3, Table 11: "Overdrive" run mode particulars
|
||||
void SystemInit(void) { // Called automatically by startup code (ints masked)
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
asm("DSB");
|
||||
asm("ISB");
|
||||
// 79.5.2: Disable watchdogS after reset (unlocked)
|
||||
RTWDOG3->CS &= ~RTWDOG_CS_EN_MASK;
|
||||
RTWDOG3->TOVAL = 0xFFFF;
|
||||
while (RTWDOG3->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock
|
||||
while ((RTWDOG3->CS & RTWDOG_CS_RCS_MASK) == 0)
|
||||
spin(1); // wait for new config
|
||||
RTWDOG4->CS &= ~RTWDOG_CS_EN_MASK;
|
||||
RTWDOG4->TOVAL = 0xFFFF;
|
||||
while (RTWDOG4->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock
|
||||
while ((RTWDOG4->CS & RTWDOG_CS_RCS_MASK) == 0)
|
||||
spin(1); // wait for new config
|
||||
ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1);
|
||||
while ((ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK) == 0)
|
||||
spin(1); // wait until it is stable
|
||||
DCDC_BootIntoDCM(DCDC); // Enable "overdrive" mode as needed
|
||||
DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
|
||||
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, (OCOTP->FUSEN[7].FUSE & BIT(4)) == 0);
|
||||
const clock_arm_pll_config_t armpll = {.loopDivider = 166, .postDivider = 0};
|
||||
CLOCK_InitArmPll(&armpll); // Set clock to 996MHz
|
||||
CCM->CLOCK_ROOT[0].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(4); // /1
|
||||
|
||||
// rng_init(); // TRNG is part or CAAM and there is no info on that
|
||||
// NXP startup code calls SystemInit BEFORE initializing RAM...
|
||||
SysTick_Config(SYS_FREQUENCY / 1000); // Sys tick every 1ms
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user