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Refactor W5500 driver, add arduino w5500 example

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This commit is contained in:
cpq 2022-09-02 12:58:43 +01:00
parent f7f7319698
commit 567fccd7ee
8 changed files with 233 additions and 112 deletions
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17
mip/driver_enc28j60.c
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@ -1,8 +1,23 @@
#include "mip.h" #include "mip.h"
#if MG_ENABLE_MIP #if MG_ENABLE_MIP
static void mip_driver_enc28j60_init(uint8_t *mac, void *data) {
// Instruction set
enum { OP_RCR, OP_RBM, OP_WCR, OP_WBM, OP_BFS, OP_BFC, OP_SRC };
static uint8_t rd(struct mip_spi *spi, uint8_t op, uint8_t addr) {
spi->begin(spi->spi);
spi->txn(spi->spi, (uint8_t) ((op << 5) | (addr & 0x1f)));
uint8_t value = spi->txn(spi->spi, 255);
if (addr & 0x80) value = spi->txn(spi->spi, 255);
spi->end(spi->spi);
return value;
}
static bool mip_driver_enc28j60_init(uint8_t *mac, void *data) {
(void) mac, (void) data; (void) mac, (void) data;
rd(data, OP_SRC, 0x1f);
return false;
} }
static size_t mip_driver_enc28j60_tx(const void *buf, size_t len, void *data) { static size_t mip_driver_enc28j60_tx(const void *buf, size_t len, void *data) {

3
mip/driver_stm32.c
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@ -50,7 +50,7 @@ static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
while (ETH->MACMIIAR & BIT(0)) spin(1); while (ETH->MACMIIAR & BIT(0)) spin(1);
} }
static void mip_driver_stm32_init(uint8_t *mac, void *userdata) { static bool mip_driver_stm32_init(uint8_t *mac, void *userdata) {
// Init RX descriptors // Init RX descriptors
for (int i = 0; i < ETH_DESC_CNT; i++) { for (int i = 0; i < ETH_DESC_CNT; i++) {
s_rxdesc[i][0] = BIT(31); // Own s_rxdesc[i][0] = BIT(31); // Own
@ -86,6 +86,7 @@ static void mip_driver_stm32_init(uint8_t *mac, void *userdata) {
// TODO(cpq): setup MAC filtering // TODO(cpq): setup MAC filtering
(void) userdata, (void) mac; (void) userdata, (void) mac;
return true;
} }
static void mip_driver_stm32_setrx(void (*rx)(void *, size_t, void *), static void mip_driver_stm32_setrx(void (*rx)(void *, size_t, void *),

123
mip/driver_w5500.c
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@ -1,99 +1,86 @@
// Copyright (c) 2022 Cesanta Software Limited #include "mip.h"
// All rights reserved
//
// This software is dual-licensed: you can redistribute it and/or modify
// it under the terms of the GNU Affero General Public License version 3 as
// published by the Free Software Foundation. For the terms of this
// license, see http://www.fsf.org/licensing/licenses/agpl-3.0.html
//
// You are free to use this software under the terms of the GNU General
// Public License, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// Alternatively, you can license this software under a commercial
// license, please contact us at https://cesanta.com/contact.html
#pragma once #if MG_ENABLE_MIP
struct w5500 {
uint8_t mac[6]; // MAC address
void *spi; // Opaque SPI bus descriptor
uint8_t (*txn)(void *, uint8_t); // SPI transaction
void (*begin)(void *); // SPI begin
void (*end)(void *); // SPI end
};
enum { W5500_CR = 0, W5500_S0 = 1, W5500_TX0 = 2, W5500_RX0 = 3 }; enum { W5500_CR = 0, W5500_S0 = 1, W5500_TX0 = 2, W5500_RX0 = 3 };
static inline void w5500_txn(struct w5500 *w, uint8_t block, uint16_t addr, static void w5500_txn(struct mip_spi *s, uint8_t block, uint16_t addr, bool wr,
bool wr, void *buf, size_t len) { void *buf, size_t len) {
uint8_t *p = buf, cmd[] = {(uint8_t) (addr >> 8), (uint8_t) (addr & 255), uint8_t *p = buf, cmd[] = {(uint8_t) (addr >> 8), (uint8_t) (addr & 255),
(uint8_t) ((block << 3) | (wr ? 4 : 0))}; (uint8_t) ((block << 3) | (wr ? 4 : 0))};
w->begin(w->spi); s->begin(s->spi);
for (size_t i = 0; i < sizeof(cmd); i++) w->txn(w->spi, cmd[i]); for (size_t i = 0; i < sizeof(cmd); i++) s->txn(s->spi, cmd[i]);
for (size_t i = 0; i < len; i++) { for (size_t i = 0; i < len; i++) {
uint8_t r = w->txn(w->spi, p[i]); uint8_t r = s->txn(s->spi, p[i]);
if (!wr) p[i] = r; if (!wr) p[i] = r;
} }
w->end(w->spi); s->end(s->spi);
} }
// clang-format off // clang-format off
static inline void w5500_wn(struct w5500 *w, uint8_t block, uint16_t addr, void *buf, size_t len) { w5500_txn(w, block, addr, true, buf, len); } static void w5500_wn(struct mip_spi *s, uint8_t block, uint16_t addr, void *buf, size_t len) { w5500_txn(s, block, addr, true, buf, len); }
static inline void w5500_w1(struct w5500 *w, uint8_t block, uint16_t addr, uint8_t val) { w5500_wn(w, block, addr, &val, 1); } static void w5500_w1(struct mip_spi *s, uint8_t block, uint16_t addr, uint8_t val) { w5500_wn(s, block, addr, &val, 1); }
static inline void w5500_w2(struct w5500 *w, uint8_t block, uint16_t addr, uint16_t val) { uint8_t buf[2] = {(uint8_t) (val >> 8), (uint8_t) (val & 255)}; w5500_wn(w, block, addr, buf, sizeof(buf)); } static void w5500_w2(struct mip_spi *s, uint8_t block, uint16_t addr, uint16_t val) { uint8_t buf[2] = {(uint8_t) (val >> 8), (uint8_t) (val & 255)}; w5500_wn(s, block, addr, buf, sizeof(buf)); }
static inline void w5500_rn(struct w5500 *w, uint8_t block, uint16_t addr, void *buf, size_t len) { w5500_txn(w, block, addr, false, buf, len); } static void w5500_rn(struct mip_spi *s, uint8_t block, uint16_t addr, void *buf, size_t len) { w5500_txn(s, block, addr, false, buf, len); }
static inline uint8_t w5500_r1(struct w5500 *w, uint8_t block, uint16_t addr) { uint8_t r = 0; w5500_rn(w, block, addr, &r, 1); return r; } static uint8_t w5500_r1(struct mip_spi *s, uint8_t block, uint16_t addr) { uint8_t r = 0; w5500_rn(s, block, addr, &r, 1); return r; }
static inline uint16_t w5500_r2(struct w5500 *w, uint8_t block, uint16_t addr) { uint8_t buf[2] = {0, 0}; w5500_rn(w, block, addr, buf, sizeof(buf)); return (uint16_t) ((buf[0] << 8) | buf[1]); } static uint16_t w5500_r2(struct mip_spi *s, uint8_t block, uint16_t addr) { uint8_t buf[2] = {0, 0}; w5500_rn(s, block, addr, buf, sizeof(buf)); return (uint16_t) ((buf[0] << 8) | buf[1]); }
// clang-format on // clang-format on
static inline uint8_t w5500_status(struct w5500 *w) { static size_t w5500_rx(void *buf, size_t buflen, void *data) {
return w5500_r1(w, W5500_CR, 0x2e); struct mip_spi *s = (struct mip_spi *) data;
} uint16_t r = 0, n = 0, len = (uint16_t) buflen, n2; // Read recv len
while ((n2 = w5500_r2(s, W5500_S0, 0x26)) > n) n = n2; // Until it is stable
static inline uint16_t w5500_rx(struct w5500 *w, uint8_t *buf, uint16_t len) {
uint16_t r = 0, n = 0, n2; // Read recv len
while ((n2 = w5500_r2(w, W5500_S0, 0x26)) > n) n = n2; // Until it is stable
// printf("RSR: %d\n", (int) n); // printf("RSR: %d\n", (int) n);
if (n > 0) { if (n > 0) {
uint16_t ptr = w5500_r2(w, W5500_S0, 0x28); // Get read pointer uint16_t ptr = w5500_r2(s, W5500_S0, 0x28); // Get read pointer
n = w5500_r2(w, W5500_RX0, ptr); // Read frame length n = w5500_r2(s, W5500_RX0, ptr); // Read frame length
if (n <= len + 2) r = n - 2, w5500_rn(w, W5500_RX0, ptr + 2, buf, r); if (n <= len + 2) r = n - 2, w5500_rn(s, W5500_RX0, ptr + 2, buf, r);
w5500_w2(w, W5500_S0, 0x28, ptr + n); // Advance read pointer w5500_w2(s, W5500_S0, 0x28, ptr + n); // Advance read pointer
w5500_w1(w, W5500_S0, 1, 0x40); // Sock0 CR -> RECV w5500_w1(s, W5500_S0, 1, 0x40); // Sock0 CR -> RECV
// printf(" RX_RD: tot=%u n=%u r=%u\n", n2, n, r); // printf(" RX_RD: tot=%u n=%u r=%u\n", n2, n, r);
} }
return r; return r;
} }
static inline uint16_t w5500_tx(struct w5500 *w, void *buf, uint16_t len) { static size_t w5500_tx(const void *buf, size_t buflen, void *data) {
uint16_t n = 0; struct mip_spi *s = (struct mip_spi *) data;
while (n < len) n = w5500_r2(w, W5500_S0, 0x20); // Wait for space uint16_t n = 0, len = (uint16_t) buflen;
uint16_t ptr = w5500_r2(w, W5500_S0, 0x24); // Get write pointer while (n < len) n = w5500_r2(s, W5500_S0, 0x20); // Wait for space
w5500_wn(w, W5500_TX0, ptr, buf, len); // Write data uint16_t ptr = w5500_r2(s, W5500_S0, 0x24); // Get write pointer
w5500_w2(w, W5500_S0, 0x24, ptr + len); // Advance write pointer w5500_wn(s, W5500_TX0, ptr, (void *) buf, len); // Write data
w5500_w1(w, W5500_S0, 1, 0x20); // Sock0 CR -> SEND w5500_w2(s, W5500_S0, 0x24, ptr + len); // Advance write pointer
w5500_w1(s, W5500_S0, 1, 0x20); // Sock0 CR -> SEND
for (int i = 0; i < 40; i++) { for (int i = 0; i < 40; i++) {
uint8_t ir = w5500_r1(w, W5500_S0, 2); // Read S0 IR uint8_t ir = w5500_r1(s, W5500_S0, 2); // Read S0 IR
if (ir == 0) continue; if (ir == 0) continue;
// printf("IR %d, len=%d, free=%d, ptr %d\n", ir, (int) len, (int) n, ptr); // printf("IR %d, len=%d, free=%d, ptr %d\n", ir, (int) len, (int) n, ptr);
w5500_w1(w, W5500_S0, 2, ir); // Write S0 IR: clear it! w5500_w1(s, W5500_S0, 2, ir); // Write S0 IR: clear it!
if (ir & 8) len = 0; // Timeout. Report error if (ir & 8) len = 0; // Timeout. Report error
if (ir & (16 | 8)) break; // Stop on SEND_OK or timeout if (ir & (16 | 8)) break; // Stop on SEND_OK or timeout
} }
return len; return len;
} }
static inline bool w5500_init(struct w5500 *w) { static bool w5500_init(uint8_t *mac, void *data) {
w->end(w->spi); struct mip_spi *s = (struct mip_spi *) data;
w5500_w1(w, W5500_CR, 0, 0x80); // Reset chip: CR -> 0x80 s->end(s->spi);
w5500_w1(w, W5500_CR, 0x2e, 0); // CR PHYCFGR -> reset w5500_w1(s, W5500_CR, 0, 0x80); // Reset chip: CR -> 0x80
w5500_w1(w, W5500_CR, 0x2e, 0xf8); // CR PHYCFGR -> set w5500_w1(s, W5500_CR, 0x2e, 0); // CR PHYCFGR -> reset
// w5500_wn(w, W5500_CR, 9, w->mac, 6); // Set source MAC w5500_w1(s, W5500_CR, 0x2e, 0xf8); // CR PHYCFGR -> set
w5500_w1(w, W5500_S0, 0x1e, 16); // Sock0 RX buf size // w5500_wn(s, W5500_CR, 9, s->mac, 6); // Set source MAC
w5500_w1(w, W5500_S0, 0x1f, 16); // Sock0 TX buf size w5500_w1(s, W5500_S0, 0x1e, 16); // Sock0 RX buf size
w5500_w1(w, W5500_S0, 0, 4); // Sock0 MR -> MACRAW w5500_w1(s, W5500_S0, 0x1f, 16); // Sock0 TX buf size
w5500_w1(w, W5500_S0, 1, 1); // Sock0 CR -> OPEN w5500_w1(s, W5500_S0, 0, 4); // Sock0 MR -> MACRAW
return w5500_r1(w, W5500_S0, 3) == 0x42; // Sock0 SR == MACRAW w5500_w1(s, W5500_S0, 1, 1); // Sock0 CR -> OPEN
return w5500_r1(s, W5500_S0, 3) == 0x42; // Sock0 SR == MACRAW
(void) mac;
} }
static bool w5500_up(void *data) {
uint8_t phycfgr = w5500_r1((struct mip_spi *) data, W5500_CR, 0x2e);
return phycfgr & 1; // Bit 0 of PHYCFGR is LNK (0 - down, 1 - up)
}
struct mip_driver mip_driver_w5500 = {
.init = w5500_init, .tx = w5500_tx, .rx = w5500_rx, .up = w5500_up};
#endif

39
mip/mip.c
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@ -2,7 +2,7 @@
#if MG_ENABLE_MIP #if MG_ENABLE_MIP
#if defined(_MSC_VER) #if defined(_MSC_VER) || defined(ARDUINO)
#define _Atomic #define _Atomic
#else #else
#include <stdatomic.h> #include <stdatomic.h>
@ -713,23 +713,26 @@ static void on_rx(void *buf, size_t len, void *userdata) {
void mip_init(struct mg_mgr *mgr, struct mip_cfg *ipcfg, void mip_init(struct mg_mgr *mgr, struct mip_cfg *ipcfg,
struct mip_driver *driver, void *driver_data) { struct mip_driver *driver, void *driver_data) {
size_t maxpktsize = 1500, qlen = driver->setrx ? 1024 * 16 : 0; if (driver->init && !driver->init(ipcfg->mac, driver_data)) {
struct mip_if *ifp = MG_ERROR(("driver init failed"));
(struct mip_if *) calloc(1, sizeof(*ifp) + 2 * maxpktsize + qlen); } else {
memcpy(ifp->mac, ipcfg->mac, sizeof(ifp->mac)); size_t maxpktsize = 1500, qlen = driver->setrx ? 1024 * 16 : 0;
ifp->use_dhcp = ipcfg->ip == 0; struct mip_if *ifp =
ifp->ip = ipcfg->ip, ifp->mask = ipcfg->mask, ifp->gw = ipcfg->gw; (struct mip_if *) calloc(1, sizeof(*ifp) + 2 * maxpktsize + qlen);
ifp->rx.buf = (uint8_t *) (ifp + 1), ifp->rx.len = maxpktsize; memcpy(ifp->mac, ipcfg->mac, sizeof(ifp->mac));
ifp->tx.buf = ifp->rx.buf + maxpktsize, ifp->tx.len = maxpktsize; ifp->use_dhcp = ipcfg->ip == 0;
ifp->driver = driver; ifp->ip = ipcfg->ip, ifp->mask = ipcfg->mask, ifp->gw = ipcfg->gw;
ifp->driver_data = driver_data; ifp->rx.buf = (uint8_t *) (ifp + 1), ifp->rx.len = maxpktsize;
ifp->mgr = mgr; ifp->tx.buf = ifp->rx.buf + maxpktsize, ifp->tx.len = maxpktsize;
ifp->queue.buf = ifp->tx.buf + maxpktsize; ifp->driver = driver;
ifp->queue.len = qlen; ifp->driver_data = driver_data;
if (driver->init) driver->init(ipcfg->mac, driver_data); ifp->mgr = mgr;
if (driver->setrx) driver->setrx(on_rx, ifp); ifp->queue.buf = ifp->tx.buf + maxpktsize;
mgr->priv = ifp; ifp->queue.len = qlen;
mgr->extraconnsize = sizeof(struct tcpstate); if (driver->setrx) driver->setrx(on_rx, ifp);
mgr->priv = ifp;
mgr->extraconnsize = sizeof(struct tcpstate);
}
} }
int mg_mkpipe(struct mg_mgr *m, mg_event_handler_t fn, void *d, bool udp) { int mg_mkpipe(struct mg_mgr *m, mg_event_handler_t fn, void *d, bool udp) {

5
mip/mip.h
View File

@ -4,7 +4,7 @@
#include "net.h" #include "net.h"
struct mip_driver { struct mip_driver {
void (*init)(uint8_t *mac, void *data); // Initialise driver bool (*init)(uint8_t *mac, void *data); // Initialise driver
size_t (*tx)(const void *, size_t, void *data); // Transmit frame size_t (*tx)(const void *, size_t, void *data); // Transmit frame
size_t (*rx)(void *buf, size_t len, void *data); // Receive frame (polling) size_t (*rx)(void *buf, size_t len, void *data); // Receive frame (polling)
bool (*up)(void *data); // Up/down status bool (*up)(void *data); // Up/down status
@ -21,11 +21,12 @@ void mip_init(struct mg_mgr *, struct mip_cfg *, struct mip_driver *, void *);
extern struct mip_driver mip_driver_stm32; extern struct mip_driver mip_driver_stm32;
extern struct mip_driver mip_driver_enc28j60; extern struct mip_driver mip_driver_enc28j60;
extern struct mip_driver mip_driver_w5500;
// Drivers that require SPI, can use this SPI abstraction // Drivers that require SPI, can use this SPI abstraction
struct mip_spi { struct mip_spi {
void *spi; // Opaque SPI bus descriptor void *spi; // Opaque SPI bus descriptor
uint8_t (*txn)(void *, uint8_t); // SPI transaction: write 1 byte, read reply
void (*begin)(void *); // SPI begin: slave select low void (*begin)(void *); // SPI begin: slave select low
void (*end)(void *); // SPI end: slave select high void (*end)(void *); // SPI end: slave select high
uint8_t (*txn)(void *, uint8_t); // SPI transaction: write 1 byte, read reply
}; };

151
mongoose.c
View File

@ -5622,6 +5622,8 @@ uint64_t mg_millis(void) {
clock_gettime(CLOCK_REALTIME, &ts); clock_gettime(CLOCK_REALTIME, &ts);
#endif #endif
return ((uint64_t) ts.tv_sec * 1000 + (uint64_t) ts.tv_nsec / 1000000); return ((uint64_t) ts.tv_sec * 1000 + (uint64_t) ts.tv_nsec / 1000000);
#elif defined(ARDUINO)
return (uint64_t) millis();
#else #else
return (uint64_t) (time(NULL) * 1000); return (uint64_t) (time(NULL) * 1000);
#endif #endif
@ -5932,8 +5934,23 @@ size_t mg_ws_wrap(struct mg_connection *c, size_t len, int op) {
#if MG_ENABLE_MIP #if MG_ENABLE_MIP
static void mip_driver_enc28j60_init(uint8_t *mac, void *data) {
// Instruction set
enum { OP_RCR, OP_RBM, OP_WCR, OP_WBM, OP_BFS, OP_BFC, OP_SRC };
static uint8_t rd(struct mip_spi *spi, uint8_t op, uint8_t addr) {
spi->begin(spi->spi);
spi->txn(spi->spi, (uint8_t) ((op << 5) | (addr & 0x1f)));
uint8_t value = spi->txn(spi->spi, 255);
if (addr & 0x80) value = spi->txn(spi->spi, 255);
spi->end(spi->spi);
return value;
}
static bool mip_driver_enc28j60_init(uint8_t *mac, void *data) {
(void) mac, (void) data; (void) mac, (void) data;
rd(data, OP_SRC, 0x1f);
return false;
} }
static size_t mip_driver_enc28j60_tx(const void *buf, size_t len, void *data) { static size_t mip_driver_enc28j60_tx(const void *buf, size_t len, void *data) {
@ -6012,7 +6029,7 @@ static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
while (ETH->MACMIIAR & BIT(0)) spin(1); while (ETH->MACMIIAR & BIT(0)) spin(1);
} }
static void mip_driver_stm32_init(uint8_t *mac, void *userdata) { static bool mip_driver_stm32_init(uint8_t *mac, void *userdata) {
// Init RX descriptors // Init RX descriptors
for (int i = 0; i < ETH_DESC_CNT; i++) { for (int i = 0; i < ETH_DESC_CNT; i++) {
s_rxdesc[i][0] = BIT(31); // Own s_rxdesc[i][0] = BIT(31); // Own
@ -6048,6 +6065,7 @@ static void mip_driver_stm32_init(uint8_t *mac, void *userdata) {
// TODO(cpq): setup MAC filtering // TODO(cpq): setup MAC filtering
(void) userdata, (void) mac; (void) userdata, (void) mac;
return true;
} }
static void mip_driver_stm32_setrx(void (*rx)(void *, size_t, void *), static void mip_driver_stm32_setrx(void (*rx)(void *, size_t, void *),
@ -6107,6 +6125,96 @@ struct mip_driver mip_driver_stm32 = {.init = mip_driver_stm32_init,
.up = mip_driver_stm32_up}; .up = mip_driver_stm32_up};
#endif // MG_ENABLE_MIP #endif // MG_ENABLE_MIP
#ifdef MG_ENABLE_LINES
#line 1 "mip/driver_w5500.c"
#endif
#if MG_ENABLE_MIP
enum { W5500_CR = 0, W5500_S0 = 1, W5500_TX0 = 2, W5500_RX0 = 3 };
static void w5500_txn(struct mip_spi *s, uint8_t block, uint16_t addr, bool wr,
void *buf, size_t len) {
uint8_t *p = buf, cmd[] = {(uint8_t) (addr >> 8), (uint8_t) (addr & 255),
(uint8_t) ((block << 3) | (wr ? 4 : 0))};
s->begin(s->spi);
for (size_t i = 0; i < sizeof(cmd); i++) s->txn(s->spi, cmd[i]);
for (size_t i = 0; i < len; i++) {
uint8_t r = s->txn(s->spi, p[i]);
if (!wr) p[i] = r;
}
s->end(s->spi);
}
// clang-format off
static void w5500_wn(struct mip_spi *s, uint8_t block, uint16_t addr, void *buf, size_t len) { w5500_txn(s, block, addr, true, buf, len); }
static void w5500_w1(struct mip_spi *s, uint8_t block, uint16_t addr, uint8_t val) { w5500_wn(s, block, addr, &val, 1); }
static void w5500_w2(struct mip_spi *s, uint8_t block, uint16_t addr, uint16_t val) { uint8_t buf[2] = {(uint8_t) (val >> 8), (uint8_t) (val & 255)}; w5500_wn(s, block, addr, buf, sizeof(buf)); }
static void w5500_rn(struct mip_spi *s, uint8_t block, uint16_t addr, void *buf, size_t len) { w5500_txn(s, block, addr, false, buf, len); }
static uint8_t w5500_r1(struct mip_spi *s, uint8_t block, uint16_t addr) { uint8_t r = 0; w5500_rn(s, block, addr, &r, 1); return r; }
static uint16_t w5500_r2(struct mip_spi *s, uint8_t block, uint16_t addr) { uint8_t buf[2] = {0, 0}; w5500_rn(s, block, addr, buf, sizeof(buf)); return (uint16_t) ((buf[0] << 8) | buf[1]); }
// clang-format on
static size_t w5500_rx(void *buf, size_t buflen, void *data) {
struct mip_spi *s = (struct mip_spi *) data;
uint16_t r = 0, n = 0, len = (uint16_t) buflen, n2; // Read recv len
while ((n2 = w5500_r2(s, W5500_S0, 0x26)) > n) n = n2; // Until it is stable
// printf("RSR: %d\n", (int) n);
if (n > 0) {
uint16_t ptr = w5500_r2(s, W5500_S0, 0x28); // Get read pointer
n = w5500_r2(s, W5500_RX0, ptr); // Read frame length
if (n <= len + 2) r = n - 2, w5500_rn(s, W5500_RX0, ptr + 2, buf, r);
w5500_w2(s, W5500_S0, 0x28, ptr + n); // Advance read pointer
w5500_w1(s, W5500_S0, 1, 0x40); // Sock0 CR -> RECV
// printf(" RX_RD: tot=%u n=%u r=%u\n", n2, n, r);
}
return r;
}
static size_t w5500_tx(const void *buf, size_t buflen, void *data) {
struct mip_spi *s = (struct mip_spi *) data;
uint16_t n = 0, len = (uint16_t) buflen;
while (n < len) n = w5500_r2(s, W5500_S0, 0x20); // Wait for space
uint16_t ptr = w5500_r2(s, W5500_S0, 0x24); // Get write pointer
w5500_wn(s, W5500_TX0, ptr, (void *) buf, len); // Write data
w5500_w2(s, W5500_S0, 0x24, ptr + len); // Advance write pointer
w5500_w1(s, W5500_S0, 1, 0x20); // Sock0 CR -> SEND
for (int i = 0; i < 40; i++) {
uint8_t ir = w5500_r1(s, W5500_S0, 2); // Read S0 IR
if (ir == 0) continue;
// printf("IR %d, len=%d, free=%d, ptr %d\n", ir, (int) len, (int) n, ptr);
w5500_w1(s, W5500_S0, 2, ir); // Write S0 IR: clear it!
if (ir & 8) len = 0; // Timeout. Report error
if (ir & (16 | 8)) break; // Stop on SEND_OK or timeout
}
return len;
}
static bool w5500_init(uint8_t *mac, void *data) {
struct mip_spi *s = (struct mip_spi *) data;
s->end(s->spi);
w5500_w1(s, W5500_CR, 0, 0x80); // Reset chip: CR -> 0x80
w5500_w1(s, W5500_CR, 0x2e, 0); // CR PHYCFGR -> reset
w5500_w1(s, W5500_CR, 0x2e, 0xf8); // CR PHYCFGR -> set
// w5500_wn(s, W5500_CR, 9, s->mac, 6); // Set source MAC
w5500_w1(s, W5500_S0, 0x1e, 16); // Sock0 RX buf size
w5500_w1(s, W5500_S0, 0x1f, 16); // Sock0 TX buf size
w5500_w1(s, W5500_S0, 0, 4); // Sock0 MR -> MACRAW
w5500_w1(s, W5500_S0, 1, 1); // Sock0 CR -> OPEN
return w5500_r1(s, W5500_S0, 3) == 0x42; // Sock0 SR == MACRAW
(void) mac;
}
static bool w5500_up(void *data) {
uint8_t phycfgr = w5500_r1((struct mip_spi *) data, W5500_CR, 0x2e);
return phycfgr & 1; // Bit 0 of PHYCFGR is LNK (0 - down, 1 - up)
}
struct mip_driver mip_driver_w5500 = {
.init = w5500_init, .tx = w5500_tx, .rx = w5500_rx, .up = w5500_up};
#endif
#ifdef MG_ENABLE_LINES #ifdef MG_ENABLE_LINES
#line 1 "mip/mip.c" #line 1 "mip/mip.c"
#endif #endif
@ -6114,7 +6222,7 @@ struct mip_driver mip_driver_stm32 = {.init = mip_driver_stm32_init,
#if MG_ENABLE_MIP #if MG_ENABLE_MIP
#if defined(_MSC_VER) #if defined(_MSC_VER) || defined(ARDUINO)
#define _Atomic #define _Atomic
#else #else
#include <stdatomic.h> #include <stdatomic.h>
@ -6825,23 +6933,26 @@ static void on_rx(void *buf, size_t len, void *userdata) {
void mip_init(struct mg_mgr *mgr, struct mip_cfg *ipcfg, void mip_init(struct mg_mgr *mgr, struct mip_cfg *ipcfg,
struct mip_driver *driver, void *driver_data) { struct mip_driver *driver, void *driver_data) {
size_t maxpktsize = 1500, qlen = driver->setrx ? 1024 * 16 : 0; if (driver->init && !driver->init(ipcfg->mac, driver_data)) {
struct mip_if *ifp = MG_ERROR(("ERROR intialising driver"));
(struct mip_if *) calloc(1, sizeof(*ifp) + 2 * maxpktsize + qlen); } else {
memcpy(ifp->mac, ipcfg->mac, sizeof(ifp->mac)); size_t maxpktsize = 1500, qlen = driver->setrx ? 1024 * 16 : 0;
ifp->use_dhcp = ipcfg->ip == 0; struct mip_if *ifp =
ifp->ip = ipcfg->ip, ifp->mask = ipcfg->mask, ifp->gw = ipcfg->gw; (struct mip_if *) calloc(1, sizeof(*ifp) + 2 * maxpktsize + qlen);
ifp->rx.buf = (uint8_t *) (ifp + 1), ifp->rx.len = maxpktsize; memcpy(ifp->mac, ipcfg->mac, sizeof(ifp->mac));
ifp->tx.buf = ifp->rx.buf + maxpktsize, ifp->tx.len = maxpktsize; ifp->use_dhcp = ipcfg->ip == 0;
ifp->driver = driver; ifp->ip = ipcfg->ip, ifp->mask = ipcfg->mask, ifp->gw = ipcfg->gw;
ifp->driver_data = driver_data; ifp->rx.buf = (uint8_t *) (ifp + 1), ifp->rx.len = maxpktsize;
ifp->mgr = mgr; ifp->tx.buf = ifp->rx.buf + maxpktsize, ifp->tx.len = maxpktsize;
ifp->queue.buf = ifp->tx.buf + maxpktsize; ifp->driver = driver;
ifp->queue.len = qlen; ifp->driver_data = driver_data;
if (driver->init) driver->init(ipcfg->mac, driver_data); ifp->mgr = mgr;
if (driver->setrx) driver->setrx(on_rx, ifp); ifp->queue.buf = ifp->tx.buf + maxpktsize;
mgr->priv = ifp; ifp->queue.len = qlen;
mgr->extraconnsize = sizeof(struct tcpstate); if (driver->setrx) driver->setrx(on_rx, ifp);
mgr->priv = ifp;
mgr->extraconnsize = sizeof(struct tcpstate);
}
} }
int mg_mkpipe(struct mg_mgr *m, mg_event_handler_t fn, void *d, bool udp) { int mg_mkpipe(struct mg_mgr *m, mg_event_handler_t fn, void *d, bool udp) {

5
mongoose.h
View File

@ -1423,7 +1423,7 @@ void mg_rpc_list(struct mg_rpc_req *r);
struct mip_driver { struct mip_driver {
void (*init)(uint8_t *mac, void *data); // Initialise driver bool (*init)(uint8_t *mac, void *data); // Initialise driver
size_t (*tx)(const void *, size_t, void *data); // Transmit frame size_t (*tx)(const void *, size_t, void *data); // Transmit frame
size_t (*rx)(void *buf, size_t len, void *data); // Receive frame (polling) size_t (*rx)(void *buf, size_t len, void *data); // Receive frame (polling)
bool (*up)(void *data); // Up/down status bool (*up)(void *data); // Up/down status
@ -1440,13 +1440,14 @@ void mip_init(struct mg_mgr *, struct mip_cfg *, struct mip_driver *, void *);
extern struct mip_driver mip_driver_stm32; extern struct mip_driver mip_driver_stm32;
extern struct mip_driver mip_driver_enc28j60; extern struct mip_driver mip_driver_enc28j60;
extern struct mip_driver mip_driver_w5500;
// Drivers that require SPI, can use this SPI abstraction // Drivers that require SPI, can use this SPI abstraction
struct mip_spi { struct mip_spi {
void *spi; // Opaque SPI bus descriptor void *spi; // Opaque SPI bus descriptor
uint8_t (*txn)(void *, uint8_t); // SPI transaction: write 1 byte, read reply
void (*begin)(void *); // SPI begin: slave select low void (*begin)(void *); // SPI begin: slave select low
void (*end)(void *); // SPI end: slave select high void (*end)(void *); // SPI end: slave select high
uint8_t (*txn)(void *, uint8_t); // SPI transaction: write 1 byte, read reply
}; };
#ifdef __cplusplus #ifdef __cplusplus

2
src/util.c
View File

@ -121,6 +121,8 @@ uint64_t mg_millis(void) {
clock_gettime(CLOCK_REALTIME, &ts); clock_gettime(CLOCK_REALTIME, &ts);
#endif #endif
return ((uint64_t) ts.tv_sec * 1000 + (uint64_t) ts.tv_nsec / 1000000); return ((uint64_t) ts.tv_sec * 1000 + (uint64_t) ts.tv_nsec / 1000000);
#elif defined(ARDUINO)
return (uint64_t) millis();
#else #else
return (uint64_t) (time(NULL) * 1000); return (uint64_t) (time(NULL) * 1000);
#endif #endif