mirror of
https://github.com/cesanta/mongoose.git
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Sergio R. Caprile
GitHub
commit
4389ef1e77
@ -1,727 +0,0 @@
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
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|
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|
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|
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|
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<option id="com.crt.advproject.link.sgstubenable.1965856152" name="Enable generation of Secure Gateway Import Library" superClass="com.crt.advproject.link.sgstubenable"/>
|
||||
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|
||||
<option id="com.crt.advproject.link.inimplib.1977566246" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.inimplib"/>
|
||||
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|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
</inputType>
|
||||
</tool>
|
||||
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|
||||
<option id="com.crt.advproject.miscellaneous.end_of_heap.1396717893" name="Last used address of the heap" superClass="com.crt.advproject.miscellaneous.end_of_heap"/>
|
||||
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|
||||
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|
||||
<option id="com.crt.advproject.debugger.security.nonsecureimageenable.1262271839" name="Enable pre-programming of Non-Secure Image" superClass="com.crt.advproject.debugger.security.nonsecureimageenable"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<sourceEntries>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="component"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="CMSIS"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="source"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="utilities"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="drivers"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="device"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="board"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<boardId>frdmmcxn947</boardId>
|
||||
<package>MCXN947VDF</package>
|
||||
<core>cm33</core>
|
||||
<coreId>cm33_core0_MCXN947</coreId>
|
||||
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|
||||
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|
||||
<projectStorage><?xml version="1.0" encoding="UTF-8"?>
|
||||
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|
||||
<Properties property_3="NXP" property_4="MCXN947" property_count="5" version="100300"/>
|
||||
<infoList vendor="NXP">
|
||||
<info chip="MCXN947" name="MCXN947">
|
||||
<chip>
|
||||
<name>MCXN947</name>
|
||||
<family>MCXN9XX</family>
|
||||
<vendor>NXP</vendor>
|
||||
<memory can_program="true" id="Flash" is_ro="true" size="2048" type="Flash"/>
|
||||
<memory id="RAM" size="512" type="RAM"/>
|
||||
<memoryInstance derived_from="Flash" driver="MCXNxxx.cfx" edited="true" id="PROGRAM_FLASH0" location="0x0" size="0x100000"/>
|
||||
<memoryInstance derived_from="Flash" driver="MCXNxxx.cfx" edited="true" id="PROGRAM_FLASH1" location="0x100000" size="0x100000"/>
|
||||
<memoryInstance derived_from="RAM" edited="true" id="SRAM" location="0x20000000" size="0x60000"/>
|
||||
<memoryInstance derived_from="RAM" edited="true" id="SRAMX" location="0x4000000" size="0x18000"/>
|
||||
<memoryInstance derived_from="RAM" edited="true" id="SRAMH" location="0x20060000" size="0x8000"/>
|
||||
<memoryInstance derived_from="RAM" edited="true" id="USB_RAM" location="0x400ba000" size="0x1000"/>
|
||||
</chip>
|
||||
<processor>
|
||||
<name gcc_name="cortex-m33">Cortex-M33</name>
|
||||
<family>Cortex-M</family>
|
||||
</processor>
|
||||
<processor>
|
||||
<name gcc_name="cortex-m33-nodsp">Cortex-M33 (No DSP)</name>
|
||||
<family>Cortex-M</family>
|
||||
</processor>
|
||||
</info>
|
||||
</infoList>
|
||||
</TargetConfig></projectStorage>
|
||||
</storageModule>
|
||||
<storageModule moduleId="refreshScope"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
<storageModule moduleId="openCmsis"/>
|
||||
</cproject>
|
||||
@ -1,27 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>frdm-mcxn947-xpresso-baremetal-builtin</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>com.nxp.mcuxpresso.core.datamodels.sdkNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
@ -1,25 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="com.crt.advproject.config.exe.debug.1734776104" name="Debug">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="com.crt.advproject.GCCBuildCommandParser" keep-relative-paths="false" name="MCU GCC Build Output Parser" parameter="(arm-none-eabi-gcc)|(arm-none-eabi-[gc]\+\+)|(gcc)|([gc]\+\+)|(clang)" prefer-non-shared="true"/>
|
||||
<provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="883575258906360803" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
<configuration id="com.crt.advproject.config.exe.release.35465113" name="Release">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
|
||||
<provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="889295433132188739" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
@ -1,2 +0,0 @@
|
||||
eclipse.preferences.version=1
|
||||
encoding/<project>=UTF-8
|
||||
@ -1,283 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,39 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.4
|
||||
* @date 23. July 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,352 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.3
|
||||
* @date 03. February 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,70 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
27
examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/Makefile
Normal file
27
examples/nxp/frdm-mcxn947-xpresso-baremetal-builtin/Makefile
Normal file
@ -0,0 +1,27 @@
|
||||
BOARD = mcxn947
|
||||
IDE = MCUXpresso
|
||||
RTOS = baremetal
|
||||
WIZARD_URL ?= http://mongoose.ws/wizard
|
||||
|
||||
TARGET ?= Debug
|
||||
DOCKER = docker run --rm -v $(CURDIR):/root -w /root
|
||||
IMAGE ?= scaprile/xpresso
|
||||
HEADLESS_BUILD = /usr/local/mcuxpressoide/ide/mcuxpressoide --launcher.suppressErrors -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild
|
||||
|
||||
all build example: firmware.axf
|
||||
|
||||
firmware.axf: wizard
|
||||
mkdir -p workspace
|
||||
PROJNAME=`xq -r .projectDescription.name wizard/.project` && \
|
||||
($(DOCKER) $(IMAGE) $(HEADLESS_BUILD) -data workspace -import wizard -cleanBuild $$PROJNAME/$(TARGET) || true) && \
|
||||
cp wizard/$(TARGET)/$$PROJNAME.axf firmware.axf
|
||||
|
||||
wizard:
|
||||
hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
|
||||
&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
|
||||
unzip wizard.zip
|
||||
cd wizard/source ; rm mongoose.[ch] ; cp -rL ../../../../../mongoose.[ch] .
|
||||
|
||||
|
||||
clean:
|
||||
sudo rm -rf firmware.* wizard* workspace mcuxpresso .cache .eclipse .p2
|
||||
@ -0,0 +1 @@
|
||||
See [Wizard](https://mongoose.ws/wizard/#/output?board=f429&ide=CubeIDE&rtos=baremetal&file=README.md)
|
||||
@ -1,245 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_debug_console.h"
|
||||
#include "board.h"
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
#include "fsl_lpi2c.h"
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER
|
||||
#include "fsl_lpflexcomm.h"
|
||||
#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
|
||||
#include "fsl_spc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/* Initialize debug console. */
|
||||
void BOARD_InitDebugConsole(void)
|
||||
{
|
||||
/* attach 12 MHz clock to FLEXCOMM0 (debug console) */
|
||||
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
|
||||
|
||||
RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
|
||||
|
||||
uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
|
||||
|
||||
#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER
|
||||
LP_FLEXCOMM_Init(BOARD_DEBUG_UART_INSTANCE, LP_FLEXCOMM_PERIPH_LPUART);
|
||||
#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
|
||||
}
|
||||
|
||||
void BOARD_InitDebugConsole_Core1(void)
|
||||
{
|
||||
/* attach 12 MHz clock to FLEXCOMM1 (debug console) */
|
||||
// CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH_CORE1);
|
||||
|
||||
RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST_CORE1);
|
||||
|
||||
uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ_CORE1;
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE_CORE1, BOARD_DEBUG_UART_BAUDRATE_CORE1, BOARD_DEBUG_UART_TYPE_CORE1,
|
||||
uartClkSrcFreq);
|
||||
}
|
||||
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
|
||||
{
|
||||
lpi2c_master_config_t lpi2cConfig = {0};
|
||||
|
||||
/*
|
||||
* lpi2cConfig.debugEnable = false;
|
||||
* lpi2cConfig.ignoreAck = false;
|
||||
* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
|
||||
* lpi2cConfig.baudRate_Hz = 100000U;
|
||||
* lpi2cConfig.busIdleTimeout_ns = 0;
|
||||
* lpi2cConfig.pinLowTimeout_ns = 0;
|
||||
* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
|
||||
* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
|
||||
*/
|
||||
LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
|
||||
LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize)
|
||||
{
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Write;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = txBuff;
|
||||
xfer.dataSize = txBuffSize;
|
||||
|
||||
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize)
|
||||
{
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Read;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = rxBuff;
|
||||
xfer.dataSize = rxBuffSize;
|
||||
|
||||
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize)
|
||||
{
|
||||
status_t status;
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Write;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = NULL;
|
||||
xfer.dataSize = 0;
|
||||
|
||||
status = LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
|
||||
if (kStatus_Success == status)
|
||||
{
|
||||
xfer.subaddressSize = 0;
|
||||
xfer.direction = kLPI2C_Read;
|
||||
xfer.data = rxBuff;
|
||||
xfer.dataSize = rxBuffSize;
|
||||
|
||||
status = LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void BOARD_Accel_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
|
||||
{
|
||||
uint8_t data = (uint8_t)txBuff;
|
||||
|
||||
return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
|
||||
void BOARD_Codec_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
|
||||
void BOARD_Camera_I2C_Init(void)
|
||||
{
|
||||
LP_FLEXCOMM_Init(BOARD_CAMERA_I2C_INSTANCE, LP_FLEXCOMM_PERIPH_LPI2C);
|
||||
BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
|
||||
rxBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_SendSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_ReceiveSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
|
||||
rxBuffSize);
|
||||
}
|
||||
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
|
||||
/* Update Active mode voltage for OverDrive mode. */
|
||||
void BOARD_PowerMode_OD(void)
|
||||
{
|
||||
spc_active_mode_dcdc_option_t opt = {
|
||||
.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
|
||||
.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
|
||||
};
|
||||
SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
|
||||
|
||||
spc_sram_voltage_config_t cfg = {
|
||||
.operateVoltage = kSPC_sramOperateAt1P2V,
|
||||
.requestVoltageUpdate = true,
|
||||
};
|
||||
SPC_SetSRAMOperateVoltage(SPC0, &cfg);
|
||||
}
|
||||
@ -1,261 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_gpio.h"
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief The board name */
|
||||
#define BOARD_NAME "FRDM-MCXN947"
|
||||
|
||||
/*! @brief The UART to use for debug messages. */
|
||||
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART4
|
||||
#define BOARD_DEBUG_UART_INSTANCE 4U
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ 12000000U
|
||||
#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM4
|
||||
#define BOARD_DEBUG_UART_RST kFC4_RST_SHIFT_RSTn
|
||||
#define BOARD_DEBUG_UART_CLKSRC kCLOCK_FlexComm4
|
||||
#define BOARD_UART_IRQ_HANDLER LP_FLEXCOMM4_IRQHandler
|
||||
#define BOARD_UART_IRQ LP_FLEXCOMM4_IRQn
|
||||
|
||||
#define BOARD_DEBUG_UART_TYPE_CORE1 kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR_CORE1 (uint32_t) USART1
|
||||
#define BOARD_DEBUG_UART_INSTANCE_CORE1 1U
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ_CORE1 12000000U
|
||||
#define BOARD_DEBUG_UART_CLK_ATTACH_CORE1 kFRO12M_to_FLEXCOMM1
|
||||
#define BOARD_DEBUG_UART_RST_CORE1 kFC1_RST_SHIFT_RSTn
|
||||
#define BOARD_DEBUG_UART_CLKSRC_CORE1 kCLOCK_Flexcomm1
|
||||
#define BOARD_UART_IRQ_HANDLER_CORE1 FLEXCOMM1_IRQHandler
|
||||
#define BOARD_UART_IRQ_CORE1 FLEXCOMM1_IRQn
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE
|
||||
#define BOARD_DEBUG_UART_BAUDRATE 115200U
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE */
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE_CORE1
|
||||
#define BOARD_DEBUG_UART_BAUDRATE_CORE1 115200U
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE_CORE1 */
|
||||
|
||||
/*! @brief The UART to use for Bluetooth M.2 interface. */
|
||||
#define BOARD_BT_UART_INSTANCE 2
|
||||
#define BOARD_BT_UART_BAUDRATE 3000000
|
||||
#define BOARD_BT_UART_CLK_FREQ 12000000U
|
||||
#define BOARD_BT_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM2
|
||||
|
||||
/*! @brief The ENET PHY address. */
|
||||
#define BOARD_ENET0_PHY_ADDRESS (0x00U) /* Phy address of enet port 0. */
|
||||
|
||||
/*! @brief Memory ranges not usable by the ENET DMA. */
|
||||
#ifndef BOARD_ENET_NON_DMA_MEMORY_ARRAY
|
||||
#define BOARD_ENET_NON_DMA_MEMORY_ARRAY \
|
||||
{ \
|
||||
{0x00000000U, 0x0007FFFFU}, {0x10000000U, 0x17FFFFFFU}, {0x80000000U, 0xDFFFFFFFU}, \
|
||||
{0x00000000U, 0x00000000U}, \
|
||||
}
|
||||
#endif /* BOARD_ENET_NON_DMA_MEMORY_ARRAY */
|
||||
|
||||
#define BOARD_ACCEL_I2C_BASEADDR LPI2C2
|
||||
#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
|
||||
|
||||
#define BOARD_CODEC_I2C_BASEADDR LPI2C2
|
||||
#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
|
||||
#define BOARD_CODEC_I2C_INSTANCE 2
|
||||
|
||||
/*! @brief Indexes of the TSI channels for on-board electrodes */
|
||||
#ifndef BOARD_TSI_ELECTRODE_1
|
||||
#define BOARD_TSI_ELECTRODE_1 3U
|
||||
#endif
|
||||
|
||||
/*! @brief Indexes of the TSI mutual channels for FRDM-TOUCH board */
|
||||
#define BOARD_TSI_MUTUAL_TX_ELECTRODE_1 0U
|
||||
#define BOARD_TSI_MUTUAL_RX_ELECTRODE_1 14U
|
||||
|
||||
#ifndef BOARD_LED_RED_GPIO
|
||||
#define BOARD_LED_RED_GPIO GPIO0
|
||||
#endif
|
||||
#ifndef BOARD_LED_RED_GPIO_PIN
|
||||
#define BOARD_LED_RED_GPIO_PIN 10U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_LED_BLUE_GPIO
|
||||
#define BOARD_LED_BLUE_GPIO GPIO1
|
||||
#endif
|
||||
#ifndef BOARD_LED_BLUE_GPIO_PIN
|
||||
#define BOARD_LED_BLUE_GPIO_PIN 2U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_LED_GREEN_GPIO
|
||||
#define BOARD_LED_GREEN_GPIO GPIO0
|
||||
#endif
|
||||
#ifndef BOARD_LED_GREEN_GPIO_PIN
|
||||
#define BOARD_LED_GREEN_GPIO_PIN 27U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_SW2_GPIO
|
||||
#define BOARD_SW2_GPIO GPIO0
|
||||
#endif
|
||||
#ifndef BOARD_SW2_GPIO_PIN
|
||||
#define BOARD_SW2_GPIO_PIN 23U
|
||||
#endif
|
||||
#define BOARD_SW2_NAME "SW2"
|
||||
#define BOARD_SW2_IRQ GPIO00_IRQn
|
||||
#define BOARD_SW2_IRQ_HANDLER GPIO00_IRQHandler
|
||||
|
||||
#ifndef BOARD_SW3_GPIO
|
||||
#define BOARD_SW3_GPIO GPIO0
|
||||
#endif
|
||||
#ifndef BOARD_SW3_GPIO_PIN
|
||||
#define BOARD_SW3_GPIO_PIN 6U
|
||||
#endif
|
||||
#define BOARD_SW3_NAME "SW3"
|
||||
#define BOARD_SW3_IRQ GPIO00_IRQn
|
||||
#define BOARD_SW3_IRQ_HANDLER GPIO00_IRQHandler
|
||||
|
||||
/* USB PHY condfiguration */
|
||||
#define BOARD_USB_PHY_D_CAL (0x04U)
|
||||
#define BOARD_USB_PHY_TXCAL45DP (0x07U)
|
||||
#define BOARD_USB_PHY_TXCAL45DM (0x07U)
|
||||
|
||||
#define BOARD_HAS_NO_CTIMER_OUTPUT_PIN_CONNECTED_TO_LED (1)
|
||||
|
||||
/* Board led color mapping */
|
||||
#define LOGIC_LED_ON 0U
|
||||
#define LOGIC_LED_OFF 1U
|
||||
|
||||
#define LED_RED_INIT(output) \
|
||||
GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \
|
||||
BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */
|
||||
#define LED_RED_ON() GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */
|
||||
#define LED_RED_OFF() GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */
|
||||
#define LED_RED_TOGGLE() GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
|
||||
|
||||
#define LED_BLUE_INIT(output) \
|
||||
GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \
|
||||
BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Enable target LED_BLUE */
|
||||
#define LED_BLUE_ON() GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */
|
||||
#define LED_BLUE_OFF() GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */
|
||||
#define LED_BLUE_TOGGLE() GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
|
||||
|
||||
#define LED_GREEN_INIT(output) \
|
||||
GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \
|
||||
BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */
|
||||
#define LED_GREEN_ON() GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */
|
||||
#define LED_GREEN_OFF() GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */
|
||||
#define LED_GREEN_TOGGLE() GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
|
||||
|
||||
/* Display. */
|
||||
#define BOARD_LCD_DC_GPIO GPIO0
|
||||
#define BOARD_LCD_DC_GPIO_PORT 0U
|
||||
#define BOARD_LCD_DC_GPIO_PIN 10U
|
||||
|
||||
/* Camera */
|
||||
#define BOARD_CAMERA_I2C_BASEADDR LPI2C7
|
||||
#define BOARD_CAMERA_I2C_INSTANCE 7
|
||||
#define BOARD_CAMERA_I2C_CLOCK_FREQ CLOCK_GetLPFlexCommClkFreq(BOARD_CAMERA_I2C_INSTANCE)
|
||||
|
||||
/* Serial MWM WIFI */
|
||||
#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
|
||||
#define BOARD_SERIAL_MWM_PORT USART2
|
||||
#define BOARD_SERIAL_MWM_PORT_IRQn FLEXCOMM2_IRQn
|
||||
#define BOARD_SERIAL_MWM_RST_WRITE(output)
|
||||
|
||||
/*! @brief The EMVSIM SMARTCARD PHY configuration. */
|
||||
#define BOARD_SMARTCARD_MODULE (EMVSIM0) /*!< SMARTCARD communicational module instance */
|
||||
#define BOARD_SMARTCARD_MODULE_IRQ (EMVSIM0_IRQn) /*!< SMARTCARD communicational module IRQ handler */
|
||||
#define BOARD_SMARTCARD_CLOCK_MODULE_CLK_FREQ (CLOCK_GetEmvsimClkFreq(0U))
|
||||
#define BOARD_SMARTCARD_CLOCK_VALUE (4000000U) /*!< SMARTCARD clock frequency */
|
||||
|
||||
/* ERPC LPSPI configuration */
|
||||
#define ERPC_BOARD_LPSPI_SLAVE_READY_USE_GPIO (1)
|
||||
#define ERPC_BOARD_LPSPI_BASEADDR LPSPI3
|
||||
#define ERPC_BOARD_LPSPI_BAUDRATE 500000U
|
||||
#define ERPC_BOARD_LPSPI_CLKSRC kCLOCK_Flexcomm3
|
||||
#define ERPC_BOARD_LPSPI_CLK_FREQ 12000000 // CLOCK_GetFlexCommClkFreq(1)
|
||||
#define ERPC_BOARD_LPSPI_INT_GPIO GPIO0
|
||||
#define ERPC_BOARD_LPSPI_INT_PIN 16U
|
||||
#define ERPC_BOARD_LPSPI_INT_PIN_IRQ PIN_INT0_IRQn
|
||||
#define ERPC_BOARD_LPSPI_INT_PIN_IRQ_HANDLER PIN_INT0_IRQHandler
|
||||
|
||||
/* ERPC LPI2C configuration */
|
||||
#define ERPC_BOARD_LPI2C_BASEADDR LPI2C0_BASE
|
||||
#define ERPC_BOARD_LPI2C_BAUDRATE 100000U
|
||||
#define ERPC_BOARD_LPI2C_CLKSRC kCLOCK_Flexcomm0
|
||||
#define ERPC_BOARD_LPI2C_CLK_FREQ 12000000 // CLOCK_GetFlexCommClkFreq(2)
|
||||
#define ERPC_BOARD_LPI2C_INT_GPIO GPIO1
|
||||
#define ERPC_BOARD_LPI2C_INT_PIN 0U
|
||||
#define ERPC_BOARD_LPI2C_INT_PIN_IRQ PIN_INT1_IRQn
|
||||
#define ERPC_BOARD_LPI2C_INT_PIN_IRQ_HANDLER PIN_INT1_IRQHandler
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
void BOARD_InitDebugConsole(void);
|
||||
void BOARD_InitDebugConsole_Core1(void);
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
|
||||
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
void BOARD_Accel_I2C_Init(void);
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Codec_I2C_Init(void);
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Camera_I2C_Init(void);
|
||||
status_t BOARD_Camera_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Camera_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
|
||||
status_t BOARD_Camera_I2C_SendSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Camera_I2C_ReceiveSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
|
||||
void BOARD_PowerMode_OD(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
@ -1,354 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. Setup clock sources.
|
||||
*
|
||||
* 2. Set up wait states of the flash.
|
||||
*
|
||||
* 3. Set up all dividers.
|
||||
*
|
||||
* 4. Set up all selectors to provide selected clocks.
|
||||
*
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v11.0
|
||||
processor: MCXN947
|
||||
package_id: MCXN947VDF
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.13.10
|
||||
board: FRDM-MCXN947
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_clock.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockPLL150M();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockFRO12M
|
||||
outputs:
|
||||
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
|
||||
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
||||
- {id: MAIN_clock.outFreq, value: 12 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 3 MHz}
|
||||
- {id: System_clock.outFreq, value: 12 MHz}
|
||||
- {id: gdet_clock.outFreq, value: 48 MHz}
|
||||
- {id: trng_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: RunPowerMode, value: OD}
|
||||
- {id: SCGMode, value: SIRC}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
|
||||
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
|
||||
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockFRO12M(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
|
||||
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(12000000U, kOD_Mode); /*!< Set the additional number of flash wait-states */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF48M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockFROHF48M
|
||||
outputs:
|
||||
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
|
||||
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
||||
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
|
||||
- {id: MAIN_clock.outFreq, value: 48 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 12 MHz}
|
||||
- {id: System_clock.outFreq, value: 48 MHz}
|
||||
- {id: gdet_clock.outFreq, value: 48 MHz}
|
||||
- {id: trng_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: RunPowerMode, value: OD}
|
||||
- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
|
||||
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockFROHF48M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockFROHF48M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockFROHF48M(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
|
||||
|
||||
/* FRO OSC setup - begin, enable the FRO for safety switching */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(48000000U, kOD_Mode); /*!< Set the additional number of flash wait-states */
|
||||
|
||||
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF144M ********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockFROHF144M
|
||||
outputs:
|
||||
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
|
||||
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
||||
- {id: FRO_HF_clock.outFreq, value: 144 MHz}
|
||||
- {id: MAIN_clock.outFreq, value: 144 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 36 MHz}
|
||||
- {id: System_clock.outFreq, value: 144 MHz}
|
||||
- {id: gdet_clock.outFreq, value: 48 MHz}
|
||||
- {id: trng_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: RunPowerMode, value: OD}
|
||||
- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
|
||||
- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
|
||||
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
sources:
|
||||
- {id: SCG.FIRC.outFreq, value: 144 MHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockFROHF144M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockFROHF144M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockFROHF144M(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
|
||||
|
||||
/* FRO OSC setup - begin, enable the FRO for safety switching */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(144000000U, kOD_Mode); /*!< Set the additional number of flash wait-states */
|
||||
|
||||
CLOCK_SetupFROHFClocking(144000000U); /*!< Enable FRO HF(144MHz) output */
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL150M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL150M
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
|
||||
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
||||
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
|
||||
- {id: MAIN_clock.outFreq, value: 150 MHz}
|
||||
- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 37.5 MHz}
|
||||
- {id: System_clock.outFreq, value: 150 MHz}
|
||||
- {id: gdet_clock.outFreq, value: 48 MHz}
|
||||
- {id: trng_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: PLL0_Mode, value: Normal}
|
||||
- {id: RunPowerMode, value: OD}
|
||||
- {id: SCGMode, value: PLL0}
|
||||
- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
|
||||
- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
|
||||
- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
|
||||
- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
|
||||
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL150M(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
|
||||
|
||||
/* FRO OSC setup - begin, enable the FRO for safety switching */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(150000000U, kOD_Mode); /*!< Set the additional number of flash wait-states */
|
||||
|
||||
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
|
||||
/*!< Set up PLL0 */
|
||||
const pll_setup_t pll0Setup = {
|
||||
.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
|
||||
.pllndiv = SCG_APLLNDIV_NDIV(8U),
|
||||
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
|
||||
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
|
||||
.pllRate = 150000000U
|
||||
};
|
||||
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
|
||||
CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL100M
|
||||
outputs:
|
||||
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
|
||||
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
- {id: CLK_IN_clock.outFreq, value: 24 MHz}
|
||||
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
||||
- {id: MAIN_clock.outFreq, value: 100 MHz}
|
||||
- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 25 MHz}
|
||||
- {id: System_clock.outFreq, value: 100 MHz}
|
||||
- {id: gdet_clock.outFreq, value: 48 MHz}
|
||||
- {id: trng_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: PLL1_Mode, value: Normal}
|
||||
- {id: RunPowerMode, value: OD}
|
||||
- {id: SCGMode, value: PLL1}
|
||||
- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
|
||||
- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
|
||||
- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
|
||||
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
|
||||
- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
|
||||
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
sources:
|
||||
- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL100M(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
|
||||
|
||||
/* FRO OSC setup - begin, enable the FRO for safety switching */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(100000000U, kOD_Mode); /*!< Set the additional number of flash wait-states */
|
||||
|
||||
CLOCK_SetupExtClocking(24000000U);
|
||||
CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */
|
||||
|
||||
/*!< Set up PLL1 */
|
||||
const pll_setup_t pll1Setup = {
|
||||
.pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
|
||||
.pllndiv = SCG_SPLLNDIV_NDIV(6U),
|
||||
.pllpdiv = SCG_SPLLPDIV_PDIV(2U),
|
||||
.pllmdiv = SCG_SPLLMDIV_MDIV(100U),
|
||||
.pllRate = 100000000U
|
||||
};
|
||||
CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
|
||||
CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
@ -1,177 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
|
||||
#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO12M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF48M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFROHF48M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFROHF48M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFROHF48M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF144M ********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFROHF144M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */
|
||||
#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFROHF144M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFROHF144M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL150M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
|
||||
#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockPLL150M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
|
||||
#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockPLL100M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
@ -1,23 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Peripherals v1.0
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Included files
|
||||
******************************************************************************/
|
||||
#include "peripherals.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* BOARD_InitBootPeripherals function
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootPeripherals(void)
|
||||
{
|
||||
}
|
||||
@ -1,23 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _PERIPHERALS_H_
|
||||
#define _PERIPHERALS_H_
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /*_cplusplus. */
|
||||
/*******************************************************************************
|
||||
* BOARD_InitBootPeripherals function
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootPeripherals(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /*_cplusplus. */
|
||||
|
||||
#endif /* _PERIPHERALS_H_ */
|
||||
@ -1,705 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022-2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v14.0
|
||||
processor: MCXN947
|
||||
package_id: MCXN947VDF
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.14.19
|
||||
board: FRDM-MCXN947
|
||||
expansion_headers:
|
||||
- id: micro_bus
|
||||
name: mikroBUS(TM)
|
||||
connectors:
|
||||
- id: C1
|
||||
name: J6
|
||||
pins:
|
||||
- {id: 1, name: AN, pin_num: T2, pin_signal: ADC1_A0}
|
||||
- {id: 2, name: RST, pin_num: B4, pin_signal: PIO1_3/WUU0_IN7/TRIG_OUT1/FC3_P3/CT1_MAT1/SCT0_IN7/FLEXIO0_D11/ENET0_MDIO/SAI1_RXD0/CAN0_RXD/TSI0_CH3/ADC0_A19/CMP0_IN1}
|
||||
- {id: 3, name: CS, pin_num: M15, pin_signal: PIO3_23/FC6_P3/CT_INP11/PWM1_X3/FLEXIO0_D31/SAI1_TXD1}
|
||||
- {id: 4, name: SCK, pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0}
|
||||
- {id: 5, name: MISO, pin_num: M16, pin_signal: PIO3_22/FC8_P6/FC6_P2/CT_INP10/PWM1_X2/FLEXIO0_D30/SIM0_VCCEN/SAI1_RXD1}
|
||||
- {id: 6, name: MOSI, pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0}
|
||||
- id: C2
|
||||
name: J5
|
||||
pins:
|
||||
- {id: 1, name: PWM, pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS}
|
||||
- {id: 2, name: INT, pin_num: L13, pin_signal: PIO5_7/TRIG_IN11/TAMPER5/ADC1_B15}
|
||||
- {id: 3, name: RX, pin_num: F6, pin_signal: PIO1_16/WUU0_IN14/FC5_P0/FC3_P4/CT_INP12/SCT0_OUT6/FLEXIO0_D24/PLU_OUT4/ENET0_RXD2/I3C1_SDA/ADC1_A16}
|
||||
- {id: 4, name: TX, pin_num: F4, pin_signal: PIO1_17/FC5_P1/FC3_P5/CT_INP13/SCT0_OUT7/FLEXIO0_D25/PLU_OUT5/ENET0_RXD3/I3C1_SCL/ADC1_A17}
|
||||
- {id: 5, name: SCL, pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0}
|
||||
- {id: 6, name: SDA, pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0}
|
||||
- id: frdm_arduino
|
||||
name: LPCXpresso V3 (Arduino compatible)
|
||||
connectors:
|
||||
- id: C1
|
||||
name: J3
|
||||
pins:
|
||||
- {id: 1, pin_num: H2, pin_signal: PIO2_0/TRIG_IN5/FC9_P6/SDHC0_D5/SCT0_IN0/PWM1_A3/FLEXIO0_D8/FLEXSPI0_B_SS1_b/SAI0_RX_BCLK}
|
||||
- {id: 2, pin_num: U2, pin_signal: DAC2_OUT/ADC0_A3/ADC1_A3}
|
||||
- {id: 3, pin_num: L4, pin_signal: PIO1_22/TRIG_IN3/FC5_P6/FC4_P2/CT_INP14/SCT0_OUT4/FLEXIO0_D30/ADC1_A22}
|
||||
- {id: 5, pin_num: J3, pin_signal: PIO2_3/FC9_P1/SDHC0_D0/SCT0_OUT1/PWM1_B2/FLEXIO0_D11/FLEXSPI0_B_SCLK/SINC0_MBIT0/SAI0_RXD0}
|
||||
- {id: 6, pin_num: F3, pin_signal: RESET_B}
|
||||
- {id: 7, pin_num: H3, pin_signal: PIO2_2/WUU0_IN16/CLKOUT/FC9_P3/SDHC0_D1/SCT0_OUT0/PWM1_A2/FLEXIO0_D10/FLEXSPI0_B_SS0_b/SINC0_MCLK0/SAI0_TXD0}
|
||||
- {id: 9, pin_num: K1, pin_signal: PIO2_5/TRIG_OUT3/FC9_P2/SDHC0_CMD/SCT0_OUT3/PWM1_B1/FLEXIO0_D13/FLEXSPI0_B_DATA1/SINC0_MBIT1/SAI0_TXD1}
|
||||
- {id: 11, pin_num: K3, pin_signal: PIO2_4/WUU0_IN17/FC9_P0/SDHC0_CLK/SCT0_OUT2/PWM1_A1/FLEXIO0_D12/FLEXSPI0_B_DATA0/SINC0_MCLK1/SAI0_RXD1}
|
||||
- {id: 13, pin_num: L2, pin_signal: PIO2_7/TRIG_IN5/FC9_P5/SDHC0_D2/SCT0_OUT5/PWM1_B0/FLEXIO0_D15/FLEXSPI0_B_DATA3/SINC0_MBIT2/SAI0_TX_FS}
|
||||
- {id: 15, pin_num: K2, pin_signal: PIO2_6/TRIG_IN4/FC9_P4/SDHC0_D3/SCT0_OUT4/PWM1_A0/FLEXIO0_D14/FLEXSPI0_B_DATA2/SINC0_MCLK2/SAI0_TX_BCLK}
|
||||
- id: C2
|
||||
name: J2
|
||||
pins:
|
||||
- {id: 1, pin_num: T3, pin_signal: ADC1_B0}
|
||||
- {id: 2, pin_num: E8, pin_signal: PIO0_28/FC1_P4/FC0_P4/CT_INP0/ADC0_B20}
|
||||
- {id: 3, pin_num: M10, pin_signal: PIO5_2/VBAT_WAKEUP_b/SPC_LPREQ/TAMPER0/ADC1_B10}
|
||||
- {id: 4, pin_num: B12, pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10}
|
||||
- {id: 5, pin_num: N11, pin_signal: PIO5_3/TRIG_IN11/RTC_CLKOUT/TAMPER1/ADC1_B11}
|
||||
- {id: 6, pin_num: E10, pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19}
|
||||
- {id: 7, pin_num: M12, pin_signal: PIO5_4/TRIG_OUT7/SPC_LPREQ/TAMPER2/ADC1_B12}
|
||||
- {id: 8, pin_num: B6, pin_signal: PIO0_24/FC1_P0/CT0_MAT0/ADC0_B16}
|
||||
- {id: 9, pin_num: B15, pin_signal: PIO0_3/TDI/FC1_P3/CT0_MAT1/UTICK_CAP1/HSCMP0_OUT/CMP1_IN1}
|
||||
- {id: 10, pin_num: F10, pin_signal: PIO0_26/FC1_P2/CT0_MAT2/ADC0_B18}
|
||||
- {id: 11, pin_num: C10, pin_signal: PIO0_18/EWM0_IN/FC0_P2/CT0_MAT2/FLEXIO0_D2/HSCMP0_OUT/PDM0_DATA1/TSI0_CH13/ADC0_A10}
|
||||
- {id: 12, pin_num: A6, pin_signal: PIO0_25/FC1_P1/CT0_MAT1/ADC0_B17}
|
||||
- {id: 13, pin_num: C9, pin_signal: PIO0_19/WUU0_IN3/EWM0_OUT_b/FC0_P3/CT0_MAT3/FLEXIO0_D3/HSCMP1_OUT/TSI0_CH14/ADC0_A11}
|
||||
- {id: 15, pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0}
|
||||
- {id: 17, pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0}
|
||||
- {id: 18, pin_num: P1, pin_signal: PIO4_0/WUU0_IN18/TRIG_IN6/FC2_P0/CT_INP16/PLU_IN0/SINC0_MCLK3}
|
||||
- {id: 20, pin_num: P2, pin_signal: PIO4_1/TRIG_IN7/FC2_P1/CT_INP17/PLU_IN1}
|
||||
- id: C3
|
||||
name: J1
|
||||
pins:
|
||||
- {id: 1, pin_num: J15, pin_signal: PIO3_16/FC8_P2/CT_INP8/PWM1_A2/FLEXIO0_D24/SIM0_CLK/SAI1_TX_BCLK}
|
||||
- {id: 2, pin_num: U1, pin_signal: PIO4_3/WUU0_IN19/TRIG_IN7/FC2_P3/CT_INP13/PLU_IN3/DAC1_OUT/ADC0_B4/ADC1_B4/CMP0_IN5N/CMP1_IN5N/CMP2_IN5N}
|
||||
- {id: 3, pin_num: T7, pin_signal: PIO4_13/TRIG_IN8/FC2_P1/USB1_ID/CT4_MAT1/FLEXIO0_D21/PLU_OUT1/SINC0_MBIT0/CAN0_TXD/OPAMP0_INP1/ADC0_B5/ADC1_B5}
|
||||
- {id: 4, pin_num: T1, pin_signal: PIO4_2/TRIG_IN6/FC2_P2/CT_INP12/PLU_IN2/SINC0_MBIT3/DAC0_OUT/ADC0_A4/ADC1_A4/CMP0_IN4N/CMP1_IN4N/CMP2_IN4N}
|
||||
- {id: 5, pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0}
|
||||
- {id: 6, pin_num: F8, pin_signal: PIO0_29/FC1_P5/FC0_P5/CT_INP1/ADC0_B21}
|
||||
- {id: 7, pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3}
|
||||
- {id: 8, pin_num: M4, pin_signal: PIO1_23/FC4_P3/CT_INP15/SCT0_OUT5/FLEXIO0_D31/ADC1_A23}
|
||||
- {id: 9, pin_num: K16, pin_signal: PIO3_18/FC6_P6/CT2_MAT0/PWM1_X0/FLEXIO0_D26/SAI1_RX_BCLK}
|
||||
- {id: 10, pin_num: E7, pin_signal: PIO0_30/FC1_P6/FC0_P6/CT_INP2/ADC0_B22}
|
||||
- {id: 11, pin_num: K15, pin_signal: PIO3_17/WUU0_IN26/FC8_P3/CT_INP9/PWM1_B2/FLEXIO0_D25/SIM0_IO/SAI1_TX_FS}
|
||||
- {id: 12, pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3}
|
||||
- {id: 13, pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS}
|
||||
- {id: 14, pin_num: C4, pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0}
|
||||
- {id: 15, pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0}
|
||||
- {id: 16, pin_num: D7, pin_signal: PIO0_31/CT_INP3/ADC0_B23}
|
||||
- id: C4
|
||||
name: J4
|
||||
pins:
|
||||
- {id: 1, pin_num: T6, pin_signal: PIO4_12/WUU0_IN20/USB0_VBUS_DET/FC2_P0/CT4_MAT0/FLEXIO0_D20/PLU_OUT0/SINC0_MCLK0/CAN0_RXD/OPAMP0_INP0/ADC0_A5/ADC1_A5}
|
||||
- {id: 2, pin_num: P3, pin_signal: ADC0_A0}
|
||||
- {id: 3, pin_num: U6, pin_signal: OPAMP0_INN}
|
||||
- {id: 4, pin_num: R3, pin_signal: ADC0_B0}
|
||||
- {id: 5, pin_num: R8, pin_signal: PIO4_16/FC2_P2/USB1_OTG_PWR/CT3_MAT0/FLEXIO0_D24/PLU_OUT4/SINC0_MCLK1/CAN1_TXD/OPAMP1_INP0/ADC0_A6}
|
||||
- {id: 6, pin_num: E11, pin_signal: PIO0_14/FC1_P6/FC0_P2/CT_INP2/UTICK_CAP0/FLEXIO0_D6/ADC0_B14}
|
||||
- {id: 7, pin_num: U8, pin_signal: OPAMP1_INN}
|
||||
- {id: 8, pin_num: B8, pin_signal: PIO0_22/EWM0_IN/FC0_P6/FC1_P2/CT_INP2/FLEXIO0_D6/I3C0_PUR/ADC0_A14/CMP1_IN2}
|
||||
- {id: 9, pin_num: T10, pin_signal: PIO4_20/TRIG_IN8/FC2_P4/CT2_MAT0/FLEXIO0_D28/SINC0_MCLK2/OPAMP2_INP0/ADC1_A6}
|
||||
- {id: 10, pin_num: G13, pin_signal: PIO0_15/FC0_P3/CT_INP3/UTICK_CAP1/FLEXIO0_D7/ADC0_B15}
|
||||
- {id: 11, pin_num: U10, pin_signal: OPAMP2_INN}
|
||||
- {id: 12, pin_num: B7, pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2}
|
||||
- {id: frdm_arduino, name: LPCXpressoV2/V3 Expansion Header}
|
||||
- {id: micro_bus, name: mikroBUS Click Header}
|
||||
external_user_signals: {}
|
||||
pin_labels:
|
||||
- {pin_num: A1, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8, label: 'P1_8/J9[32]',
|
||||
identifier: DEBUG_UART_RX}
|
||||
- {pin_num: B1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9, label: 'P1_9/J9[30]', identifier: DEBUG_UART_TX}
|
||||
- {pin_num: D1, pin_signal: PIO1_13/TRIG_IN3/FC4_P5/FC3_P1/CT2_MAT3/SCT0_OUT5/FLEXIO0_D21/PLU_OUT3/ENET0_RXDV/CAN1_TXD/TSI0_CH22/ADC1_A13, label: 'P1_13/J9[27]'}
|
||||
- {pin_num: F1, pin_signal: PIO1_30/TRIG_OUT3/CT_INP16/SCT0_OUT8/SAI0_MCLK/XTAL48M, label: 'P1_30/XTAL/Y1[1]'}
|
||||
- {pin_num: H1, pin_signal: PIO2_1/TRACE_CLK/SDHC0_D4/SCT0_IN1/PWM1_B3/FLEXIO0_D9/FLEXSPI0_B_DQS/SINC0_MCLK_OUT0/SAI0_RX_FS, label: 'P2_1/TP27/J12[9]'}
|
||||
- {pin_num: K1, pin_signal: PIO2_5/TRIG_OUT3/FC9_P2/SDHC0_CMD/SCT0_OUT3/PWM1_B1/FLEXIO0_D13/FLEXSPI0_B_DATA1/SINC0_MBIT1/SAI0_TXD1, label: 'P2_5/TP25/J12[3]/J3[9]/SJ6[3]'}
|
||||
- {pin_num: M1, pin_signal: PIO2_9/TRACE_DATA1/SDHC0_D6/SCT0_IN3/PWM1_X1/FLEXIO0_D17/FLEXSPI0_B_DATA5/SINC0_MBIT3/SAI1_RXD0, label: 'P2_9/J8[14]'}
|
||||
- {pin_num: P1, pin_signal: PIO4_0/WUU0_IN18/TRIG_IN6/FC2_P0/CT_INP16/PLU_IN0/SINC0_MCLK3, label: 'P4_0/J8[4]/SJ14[1]'}
|
||||
- {pin_num: T1, pin_signal: PIO4_2/TRIG_IN6/FC2_P2/CT_INP12/PLU_IN2/SINC0_MBIT3/DAC0_OUT/ADC0_A4/ADC1_A4/CMP0_IN4N/CMP1_IN4N/CMP2_IN4N, label: 'P4_2/J1[4]'}
|
||||
- {pin_num: U1, pin_signal: PIO4_3/WUU0_IN19/TRIG_IN7/FC2_P3/CT_INP13/PLU_IN3/DAC1_OUT/ADC0_B4/ADC1_B4/CMP0_IN5N/CMP1_IN5N/CMP2_IN5N, label: 'P4_3/J1[2]'}
|
||||
- {pin_num: A2, pin_signal: PIO1_7/WUU0_IN9/TRIG_OUT2/FC5_P3/CT_INP7/SCT0_IN1/FLEXIO0_D15/PLU_CLK/ENET0_TXD1/SAI1_RX_FS/CAN1_RXD/TSI0_CH7/ADC0_A23, label: 'P1_7/J9[9]'}
|
||||
- {pin_num: B2, pin_signal: PIO1_6/TRIG_IN2/FC3_P6/FC5_P2/CT_INP6/SCT0_IN0/FLEXIO0_D14/ENET0_TXD0/SAI1_RX_BCLK/CAN1_TXD/TSI0_CH6/ADC0_A22, label: 'P1_6/J9[10]'}
|
||||
- {pin_num: D2, pin_signal: PIO1_12/WUU0_IN12/TRACE_CLK/FC4_P4/FC3_P0/CT2_MAT2/SCT0_OUT4/FLEXIO0_D20/PLU_OUT2/ENET0_RXER/CAN1_RXD/TSI0_CH21/ADC1_A12, label: 'P1_12/J2[11]/J9[28]'}
|
||||
- {pin_num: F2, pin_signal: PIO1_31/TRIG_IN4/CT_INP17/SCT0_OUT9/EXTAL48M, label: 'P1_31/EXTAL/Y1[3]'}
|
||||
- {pin_num: G2, pin_signal: VSS0, label: GND}
|
||||
- {pin_num: H2, pin_signal: PIO2_0/TRIG_IN5/FC9_P6/SDHC0_D5/SCT0_IN0/PWM1_A3/FLEXIO0_D8/FLEXSPI0_B_SS1_b/SAI0_RX_BCLK, label: 'P2_0/J3[1]/SJ8[3]'}
|
||||
- {pin_num: K2, pin_signal: PIO2_6/TRIG_IN4/FC9_P4/SDHC0_D3/SCT0_OUT4/PWM1_A0/FLEXIO0_D14/FLEXSPI0_B_DATA2/SINC0_MCLK2/SAI0_TX_BCLK, label: 'P2_6/TP24/J12[2]/J3[15]/SJ1[3]'}
|
||||
- {pin_num: L2, pin_signal: PIO2_7/TRIG_IN5/FC9_P5/SDHC0_D2/SCT0_OUT5/PWM1_B0/FLEXIO0_D15/FLEXSPI0_B_DATA3/SINC0_MBIT2/SAI0_TX_FS, label: 'P2_7/TP23/J12[1]/J3[13]/SJ3[3]'}
|
||||
- {pin_num: M2, pin_signal: PIO2_8/TRACE_DATA0/SDHC0_D7/SCT0_IN2/PWM1_X0/FLEXIO0_D16/FLEXSPI0_B_DATA4/SINC0_MCLK3/SAI1_TXD0, label: 'P2_8/J8[13]'}
|
||||
- {pin_num: P2, pin_signal: PIO4_1/TRIG_IN7/FC2_P1/CT_INP17/PLU_IN1, label: 'P4_1/J8[3]/SJ15[1]'}
|
||||
- {pin_num: T2, pin_signal: ADC1_A0, label: 'ANA_4/ADC1_A0/J6[1]'}
|
||||
- {pin_num: U2, pin_signal: DAC2_OUT/ADC0_A3/ADC1_A3, label: 'ANA_6/ADC0_A3/J3[2]'}
|
||||
- {pin_num: B3, pin_signal: PIO1_5/FREQME_CLK_IN1/FC3_P5/FC5_P1/CT1_MAT3/SCT0_OUT1/FLEXIO0_D13/ENET0_TXEN/SAI0_RXD1/TSI0_CH5/ADC0_A21/CMP0_IN3, label: 'P1_5/J9[7]'}
|
||||
- {pin_num: C3, pin_signal: PIO1_10/TRACE_DATA2/FC4_P2/FC5_P6/CT2_MAT0/SCT0_IN2/FLEXIO0_D18/PLU_IN0/ENET0_TXER/CAN0_TXD/TSI0_CH19/ADC1_A10, label: 'P1_10/SJ20[3]/SJ16[2]'}
|
||||
- {pin_num: D3, pin_signal: PIO1_11/WUU0_IN11/TRACE_DATA3/FC4_P3/CT2_MAT1/SCT0_IN3/FLEXIO0_D19/PLU_IN1/ENET0_RX_CLK/I3C1_PUR/CAN0_RXD/TSI0_CH20/ADC1_A11, label: 'P1_11/SJ26[2]'}
|
||||
- {pin_num: F3, pin_signal: RESET_B, label: 'RESET_B/J23[10]/D16[1]/SW1[3]/SW1[4]/J3[6]', identifier: SW1}
|
||||
- {pin_num: H3, pin_signal: PIO2_2/WUU0_IN16/CLKOUT/FC9_P3/SDHC0_D1/SCT0_OUT0/PWM1_A2/FLEXIO0_D10/FLEXSPI0_B_SS0_b/SINC0_MCLK0/SAI0_TXD0, label: 'P2_2/TP5/J12[8]/J3[7]/SJ7[3]'}
|
||||
- {pin_num: J3, pin_signal: PIO2_3/FC9_P1/SDHC0_D0/SCT0_OUT1/PWM1_B2/FLEXIO0_D11/FLEXSPI0_B_SCLK/SINC0_MBIT0/SAI0_RXD0, label: 'P2_3/TP4/J12[7]/J3[5]/SJ4[3]'}
|
||||
- {pin_num: K3, pin_signal: PIO2_4/WUU0_IN17/FC9_P0/SDHC0_CLK/SCT0_OUT2/PWM1_A1/FLEXIO0_D12/FLEXSPI0_B_DATA0/SINC0_MCLK1/SAI0_RXD1, label: 'P2_4/TP26/J12[5]/J3[11]/SJ5[3]'}
|
||||
- {pin_num: M3, pin_signal: PIO2_10/TRACE_DATA2/SCT0_IN4/PWM1_X2/FLEXIO0_D18/FLEXSPI0_B_DATA6/SINC0_MCLK4/SAI1_RXD1, label: 'P2_10/J8[15]'}
|
||||
- {pin_num: P3, pin_signal: ADC0_A0, label: 'ADC0_A0/ARD_A0/J4[2]'}
|
||||
- {pin_num: R3, pin_signal: ADC0_B0, label: 'ADC0_B0/ARD_A1/J4[4]'}
|
||||
- {pin_num: T3, pin_signal: ADC1_B0, label: 'ADC1_B0/MC_BEMF_A/J2[1]'}
|
||||
- {pin_num: A4, pin_signal: PIO1_4/WUU0_IN8/FREQME_CLK_IN0/FC3_P4/FC5_P0/CT1_MAT2/SCT0_OUT0/FLEXIO0_D12/ENET0_TX_CLK/SAI0_TXD1/TSI0_CH4/ADC0_A20/CMP0_IN2, label: 'P1_4/SJ27[2]'}
|
||||
- {pin_num: B4, pin_signal: PIO1_3/WUU0_IN7/TRIG_OUT1/FC3_P3/CT1_MAT1/SCT0_IN7/FLEXIO0_D11/ENET0_MDIO/SAI1_RXD0/CAN0_RXD/TSI0_CH3/ADC0_A19/CMP0_IN1, label: 'P1_3/J6[2]'}
|
||||
- {pin_num: C4, pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0, label: 'P1_2/SJ4[1]',
|
||||
identifier: LED_BLUE}
|
||||
- {pin_num: D4, pin_signal: PIO1_14/FC4_P6/FC3_P2/CT_INP10/SCT0_IN4/FLEXIO0_D22/PLU_IN2/ENET0_RXD0/TSI0_CH23/ADC1_A14, label: 'P1_14/J9[2]'}
|
||||
- {pin_num: E4, pin_signal: PIO1_15/WUU0_IN13/FC3_P3/CT_INP11/SCT0_IN5/FLEXIO0_D23/PLU_IN3/ENET0_RXD1/I3C1_PUR/TSI0_CH24/ADC1_A15, label: 'P1_15/J9[1]'}
|
||||
- {pin_num: F4, pin_signal: PIO1_17/FC5_P1/FC3_P5/CT_INP13/SCT0_OUT7/FLEXIO0_D25/PLU_OUT5/ENET0_RXD3/I3C1_SCL/ADC1_A17, label: 'P1_17/SJ15[3]/J5[4]/J9[3]'}
|
||||
- {pin_num: G4, pin_signal: PIO1_18/FREQME_CLK_IN0/FC5_P2/FC3_P6/CT3_MAT0/SCT0_IN6/FLEXIO0_D26/PLU_IN4/ENET0_COL/CAN0_TXD/ADC1_A18, label: 'P1_18/J9[6]'}
|
||||
- {pin_num: J4, pin_signal: VSS1, label: GND}
|
||||
- {pin_num: L4, pin_signal: PIO1_22/TRIG_IN3/FC5_P6/FC4_P2/CT_INP14/SCT0_OUT4/FLEXIO0_D30/ADC1_A22, label: 'P1_22/J9[24]/J3[3]/SJ9[3]'}
|
||||
- {pin_num: M4, pin_signal: PIO1_23/FC4_P3/CT_INP15/SCT0_OUT5/FLEXIO0_D31/ADC1_A23, label: 'P1_23/J9[23]/SJ1[1]'}
|
||||
- {pin_num: N4, pin_signal: PIO2_11/TRACE_DATA3/SCT0_IN5/PWM1_X3/FLEXIO0_D19/FLEXSPI0_B_DATA7/SINC0_MBIT4/SAI1_TXD1, label: 'P2_11/J8[16]'}
|
||||
- {pin_num: P4, pin_signal: VDD_P40, label: VDD_P4}
|
||||
- {pin_num: R4, pin_signal: VDD_ANA, label: 'VDD_ANA/J2[16]'}
|
||||
- {pin_num: T4, pin_signal: PIO4_7/CT_INP19, label: 'P4_7/J8[7]'}
|
||||
- {pin_num: U4, pin_signal: VREFO/ADC0_A7/ADC1_A7, label: VREFO/TP1}
|
||||
- {pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0, label: 'P1_1/J5[5]/J2[15]'}
|
||||
- {pin_num: E5, pin_signal: VSS3, label: GND}
|
||||
- {pin_num: G5, pin_signal: PIO1_19/WUU0_IN15/FREQME_CLK_IN1/FC5_P3/CT3_MAT1/SCT0_IN7/FLEXIO0_D27/PLU_IN5/ENET0_CRS/CAN0_RXD/ADC1_A19, label: 'P1_19/J9[5]'}
|
||||
- {pin_num: H5, pin_signal: VSS2, label: GND}
|
||||
- {pin_num: K5, pin_signal: PIO1_20/TRIG_IN2/FC5_P4/FC4_P0/CT3_MAT2/SCT0_OUT8/FLEXIO0_D28/PLU_OUT6/ENET0_MDC/CAN1_TXD/ADC1_A20/CMP1_IN3, label: P1_20}
|
||||
- {pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3, label: 'P1_21/SJ3[1]/J1[7]'}
|
||||
- {pin_num: N5, pin_signal: VDD_P41, label: VDD_P4}
|
||||
- {pin_num: R5, pin_signal: VREFH, label: VREFH}
|
||||
- {pin_num: A6, pin_signal: PIO0_25/FC1_P1/CT0_MAT1/ADC0_B17, label: 'P0_25/J2[12]'}
|
||||
- {pin_num: B6, pin_signal: PIO0_24/FC1_P0/CT0_MAT0/ADC0_B16, label: 'P0_24/SJ7[1]'}
|
||||
- {pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0, label: 'P1_0/J5[6]/J2[17]'}
|
||||
- {pin_num: N13, pin_signal: VSS4, label: GND}
|
||||
- {pin_num: F6, pin_signal: PIO1_16/WUU0_IN14/FC5_P0/FC3_P4/CT_INP12/SCT0_OUT6/FLEXIO0_D24/PLU_OUT4/ENET0_RXD2/I3C1_SDA/ADC1_A16, label: 'P1_16/SJ14[3]/J5[3]/J9[4]'}
|
||||
- {pin_num: H6, pin_signal: VDD1, label: VDD_P0/1}
|
||||
- {pin_num: K6, pin_signal: VDD_LDO_CORE, label: VDD_LDO_CORE_IN}
|
||||
- {pin_num: M6, pin_signal: PIO4_4/FC2_P4/CT_INP14/PLU_IN4/SINC0_MCLK4, label: 'P4_4/J9[26]'}
|
||||
- {pin_num: P6, pin_signal: VSS_P41, label: GND}
|
||||
- {pin_num: R6, pin_signal: VREFL, label: AGND}
|
||||
- {pin_num: T6, pin_signal: PIO4_12/WUU0_IN20/USB0_VBUS_DET/FC2_P0/CT4_MAT0/FLEXIO0_D20/PLU_OUT0/SINC0_MCLK0/CAN0_RXD/OPAMP0_INP0/ADC0_A5/ADC1_A5, label: 'P4_12/SJ25[1]/J8[17]'}
|
||||
- {pin_num: U6, pin_signal: OPAMP0_INN, label: 'OPAMP0_INN/RSHUNT_CURA_N/SJ24[1]'}
|
||||
- {pin_num: B7, pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, label: 'P0_23/SJ9[1]/SW2[3]/SW2[4]', identifier: SW2}
|
||||
- {pin_num: D7, pin_signal: PIO0_31/CT_INP3/ADC0_B23, label: 'P0_31/J1[16]'}
|
||||
- {pin_num: E7, pin_signal: PIO0_30/FC1_P6/FC0_P6/CT_INP2/ADC0_B22, label: 'P0_30/SJ2[1]'}
|
||||
- {pin_num: G7, pin_signal: VDD0, label: VDD_P0/1}
|
||||
- {pin_num: L7, pin_signal: VDD_P20, label: VDD_P2}
|
||||
- {pin_num: N7, pin_signal: PIO4_6/TRIG_OUT4/FC2_P6/CT_INP18/PLU_CLK, label: 'P4_6/J8[5]'}
|
||||
- {pin_num: P7, pin_signal: VSS_P42, label: GND}
|
||||
- {pin_num: T7, pin_signal: PIO4_13/TRIG_IN8/FC2_P1/USB1_ID/CT4_MAT1/FLEXIO0_D21/PLU_OUT1/SINC0_MBIT0/CAN0_TXD/OPAMP0_INP1/ADC0_B5/ADC1_B5, label: 'P4_13/SJ10[1]/SJ2[3]/J8[18]'}
|
||||
- {pin_num: A8, pin_signal: PIO0_21/FC0_P5/FC1_P1/CT_INP1/FLEXIO0_D5/I3C0_SCL/TSI0_CH16/ADC0_A13, label: 'P0_21/SJ25[3]'}
|
||||
- {pin_num: B8, pin_signal: PIO0_22/EWM0_IN/FC0_P6/FC1_P2/CT_INP2/FLEXIO0_D6/I3C0_PUR/ADC0_A14/CMP1_IN2, label: 'P0_22/J4[8]/SJ18[3]'}
|
||||
- {pin_num: C8, pin_signal: PIO0_20/WUU0_IN4/FC0_P4/FC1_P0/CT_INP0/FLEXIO0_D4/I3C0_SDA/TSI0_CH15/ADC0_A12, label: 'P0_20/SJ24[3]/J7[2]'}
|
||||
- {pin_num: E8, pin_signal: PIO0_28/FC1_P4/FC0_P4/CT_INP0/ADC0_B20, label: 'P0_28/J2[2]'}
|
||||
- {pin_num: F8, pin_signal: PIO0_29/FC1_P5/FC0_P5/CT_INP1/ADC0_B21, label: 'P0_29/J1[6]'}
|
||||
- {pin_num: H8, pin_signal: VDD2, label: VDD_P0/1}
|
||||
- {pin_num: H13, pin_signal: VSS10, label: GND}
|
||||
- {pin_num: K8, pin_signal: VDD_P21, label: VDD_P2}
|
||||
- {pin_num: M8, pin_signal: PIO4_5/FC2_P5/CT_INP15/PLU_IN5/SINC0_MBIT4, label: 'P4_5/SJ11[3]/J8[6]'}
|
||||
- {pin_num: N8, pin_signal: PIO4_14/CT4_MAT2/FLEXIO0_D22/PLU_OUT2, label: 'P4_14/J8[19]'}
|
||||
- {pin_num: R8, pin_signal: PIO4_16/FC2_P2/USB1_OTG_PWR/CT3_MAT0/FLEXIO0_D24/PLU_OUT4/SINC0_MCLK1/CAN1_TXD/OPAMP1_INP0/ADC0_A6, label: 'P4_16/SJ23[1]/J8[21]'}
|
||||
- {pin_num: T8, pin_signal: PIO4_15/WUU0_IN21/TRIG_OUT4/USB1_VBUS_DIG/CT4_MAT3/FLEXIO0_D23/PLU_OUT3/SINC0_MCLK_OUT0/CAN1_RXD/OPAMP0_OUT/ADC0_A1/CMP0_IN4P, label: 'P4_15/J8[20]'}
|
||||
- {pin_num: U8, pin_signal: OPAMP1_INN, label: 'OPAMP1_INN/RSHUNT_CURB_N/SJ22[1]'}
|
||||
- {pin_num: C9, pin_signal: PIO0_19/WUU0_IN3/EWM0_OUT_b/FC0_P3/CT0_MAT3/FLEXIO0_D3/HSCMP1_OUT/TSI0_CH14/ADC0_A11, label: 'P0_19/J2[13]/J7[1]'}
|
||||
- {pin_num: D6, pin_signal: VSS5, label: GND}
|
||||
- {pin_num: E13, pin_signal: VSS8, label: GND}
|
||||
- {pin_num: J14, pin_signal: VSS13, label: GND}
|
||||
- {pin_num: P9, pin_signal: VSS_P40, label: GND}
|
||||
- {pin_num: R9, pin_signal: PIO4_17/TRIG_IN9/FC2_P3/USB1_OTG_OC/CT3_MAT1/FLEXIO0_D25/PLU_OUT5/SINC0_MBIT1/OPAMP1_INP1/ADC0_B6, label: 'P4_17/J8[22]'}
|
||||
- {pin_num: A10, pin_signal: PIO0_17/FC0_P1/CT0_MAT1/UTICK_CAP3/FLEXIO0_D1/PDM0_DATA0/I3C0_SCL/TSI0_CH12/ADC0_A9, label: 'P0_17/J7[7]'}
|
||||
- {pin_num: B10, pin_signal: PIO0_16/WUU0_IN2/FC0_P0/CT0_MAT0/UTICK_CAP2/FLEXIO0_D0/PDM0_CLK/I3C0_SDA/TSI0_CH11/ADC0_A8, label: 'P0_16/J7[3]'}
|
||||
- {pin_num: C10, pin_signal: PIO0_18/EWM0_IN/FC0_P2/CT0_MAT2/FLEXIO0_D2/HSCMP0_OUT/PDM0_DATA1/TSI0_CH13/ADC0_A10, label: 'P0_18/SJ23[3]/J7[5]'}
|
||||
- {pin_num: E10, pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19, label: 'P0_27/SJ6[1]', identifier: LED_GREEN}
|
||||
- {pin_num: F10, pin_signal: PIO0_26/FC1_P2/CT0_MAT2/ADC0_B18, label: 'P0_26/J2[10]'}
|
||||
- {pin_num: H10, pin_signal: VDD_P31, label: VDD_P3}
|
||||
- {pin_num: J8, pin_signal: VSS11, label: GND}
|
||||
- {pin_num: K10, pin_signal: VDD_CORE/VOUT_CORE, label: 'VDD_CORE/L2[2]'}
|
||||
- {pin_num: M10, pin_signal: PIO5_2/VBAT_WAKEUP_b/SPC_LPREQ/TAMPER0/ADC1_B10, label: 'P5_2/SJ19[1]'}
|
||||
- {pin_num: N10, pin_signal: PIO4_18/CT3_MAT2/FLEXIO0_D26/PLU_OUT6, label: 'P4_18/J8[23]'}
|
||||
- {pin_num: R10, pin_signal: PIO4_19/TRIG_OUT5/CT3_MAT3/FLEXIO0_D27/PLU_OUT7/SINC0_MCLK_OUT1/OPAMP1_OUT/ADC0_B1/CMP1_IN4P, label: 'P4_19/J8[24]'}
|
||||
- {pin_num: T10, pin_signal: PIO4_20/TRIG_IN8/FC2_P4/CT2_MAT0/FLEXIO0_D28/SINC0_MCLK2/OPAMP2_INP0/ADC1_A6, label: 'P4_20/SJ21[1]/J8[25]'}
|
||||
- {pin_num: U10, pin_signal: OPAMP2_INN, label: 'OPAMP2_INN/RSHUNT_CURC_N/SJ20[1]'}
|
||||
- {pin_num: B11, pin_signal: PIO0_11/CT0_MAT1/FLEXIO0_D3/HSCMP2_OUT/ADC0_B11, label: 'P0_11/J9[18]'}
|
||||
- {pin_num: D11, pin_signal: PIO0_12/FC1_P4/FC0_P0/CT0_MAT2/FLEXIO0_D4/ADC0_B12, label: 'P0_12/J8[9]'}
|
||||
- {pin_num: E11, pin_signal: PIO0_14/FC1_P6/FC0_P2/CT_INP2/UTICK_CAP0/FLEXIO0_D6/ADC0_B14, label: 'P0_14/J4[6]/SJ19[3]'}
|
||||
- {pin_num: G11, pin_signal: VDD_P30, label: VDD_P3}
|
||||
- {pin_num: L11, pin_signal: VDD_CORE, label: 'VDD_CORE/L2[2]'}
|
||||
- {pin_num: N11, pin_signal: PIO5_3/TRIG_IN11/RTC_CLKOUT/TAMPER1/ADC1_B11, label: 'P5_3/SJ18[1]'}
|
||||
- {pin_num: P11, pin_signal: USB1_ID, label: 'HS_USB_ID/Q1[2]'}
|
||||
- {pin_num: T11, pin_signal: PIO4_21/TRIG_IN9/FC2_P5/CT2_MAT1/FLEXIO0_D29/SINC0_MBIT2/OPAMP2_INP1/ADC1_B6, label: 'P4_21/J8[26]'}
|
||||
- {pin_num: A12, pin_signal: PIO0_9/FC0_P5/CT_INP1/FLEXIO0_D1/ADC0_B9, label: 'P0_9/J8[10]'}
|
||||
- {pin_num: B12, pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10, label: 'P0_10/SJ5[1]', identifier: LED_RED}
|
||||
- {pin_num: C12, pin_signal: PIO0_8/FC0_P4/CT_INP0/FLEXIO0_D0/ADC0_B8, label: 'P0_8/J8[11]'}
|
||||
- {pin_num: D9, pin_signal: VSS6, label: GND}
|
||||
- {pin_num: F12, pin_signal: PIO0_13/FC1_P5/FC0_P1/CT0_MAT3/FLEXIO0_D5/ADC0_B13, label: 'P0_13/J8[12]'}
|
||||
- {pin_num: H12, pin_signal: VDD_P42, label: VDD_P3}
|
||||
- {pin_num: K12, pin_signal: PIO5_5/TRIG_IN10/LPTMR0_ALT2/TAMPER3/ADC1_B13, label: 'P5_5/SJ17[3]'}
|
||||
- {pin_num: M12, pin_signal: PIO5_4/TRIG_OUT7/SPC_LPREQ/TAMPER2/ADC1_B12, label: 'P5_4/J2[7]'}
|
||||
- {pin_num: P14, pin_signal: VDD3, label: GND}
|
||||
- {pin_num: R12, pin_signal: VDD_USB, label: VDD_USB}
|
||||
- {pin_num: T12, pin_signal: PIO4_22/CT2_MAT2/FLEXIO0_D30, label: 'P4_22/J8[27]'}
|
||||
- {pin_num: U12, pin_signal: PIO4_23/TRIG_OUT5/FC2_P6/CT2_MAT3/FLEXIO0_D31/SINC0_MCLK_OUT2/OPAMP2_OUT/ADC0_A2/ADC0_B2/ADC1_B3/CMP2_IN4P, label: 'P4_23/J8[28]'}
|
||||
- {pin_num: C13, pin_signal: PIO0_7/WUU0_IN1/FC0_P3/CT_INP3/CMP2_IN1, label: 'P0_7/J8[8]'}
|
||||
- {pin_num: D12, pin_signal: VSS7, label: GND}
|
||||
- {pin_num: G13, pin_signal: PIO0_15/FC0_P3/CT_INP3/UTICK_CAP1/FLEXIO0_D7/ADC0_B15, label: 'P0_15/SJ8[1]'}
|
||||
- {pin_num: H9, pin_signal: VSS9, label: GND}
|
||||
- {pin_num: K13, pin_signal: PIO5_6/TRIG_OUT6/LPTMR1_ALT2/TAMPER4/ADC1_B14, label: 'P5_6/SJ13[1]'}
|
||||
- {pin_num: L13, pin_signal: PIO5_7/TRIG_IN11/TAMPER5/ADC1_B15, label: 'P5_7/J5[2]'}
|
||||
- {pin_num: R13, pin_signal: USB1_DP, label: 'MCX_USB1_DP/L13[3]'}
|
||||
- {pin_num: A14, pin_signal: PIO0_5/EWM0_OUT_b/FC0_P1/FC1_P5/CT0_MAT3/UTICK_CAP3/PDM0_DATA0/TSI0_CH9, label: 'P0_5/SJ13[3]/J9[15]/SJ21[3]'}
|
||||
- {pin_num: B14, pin_signal: PIO0_4/WUU0_IN0/EWM0_IN/FC0_P0/FC1_P4/CT0_MAT2/UTICK_CAP2/HSCMP1_OUT/PDM0_CLK/TSI0_CH8, label: 'P0_4/SJ12[3]/J9[17]/SJ22[3]'}
|
||||
- {pin_num: C14, pin_signal: PIO0_6/ISPMODE_N/FC0_P2/FC1_P6/CT_INP2/HSCMP2_OUT/PDM0_DATA1/CLKOUT/TSI0_CH10, label: 'P0_6/J23[7]/SW3[3]/SW3[4]', identifier: SW3}
|
||||
- {pin_num: D14, pin_signal: PIO3_7/FC6_P6/FC7_P1/CT4_MAT3/PWM0_B1/FLEXIO0_D15/FLEXSPI0_A_SCLK/SIM0_VCCEN/SAI0_MCLK, label: 'P3_7/TP18/U8[6]/U7[B2]'}
|
||||
- {pin_num: E14, pin_signal: PIO3_8/WUU0_IN23/FC6_P4/FC7_P0/CT_INP4/PWM0_A2/FLEXIO0_D16/FLEXSPI0_A_DATA0/SIM0_PD/SAI0_TX_BCLK, label: 'P3_8/TP16/U8[5]/U7[D3]'}
|
||||
- {pin_num: F14, pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, label: 'P3_4/J9[12]'}
|
||||
- {pin_num: G14, pin_signal: PIO3_5/FC7_P3/CT_INP19/PWM0_X3/FLEXIO0_D13/SIM1_IO, label: 'P3_5/J9[11]'}
|
||||
- {pin_num: J10, pin_signal: VSS12, label: GND}
|
||||
- {pin_num: L14, pin_signal: PIO5_8/TRIG_OUT7/TAMPER6/ADC1_B16, label: 'P5_8/U9[19]/J9[31]'}
|
||||
- {pin_num: M14, pin_signal: PIO5_9/TAMPER7/ADC1_B17, label: 'P5_9/J9[29]'}
|
||||
- {pin_num: N14, pin_signal: VDD_SYS, label: VDD_SYS}
|
||||
- {pin_num: T16, pin_signal: VDD4, label: GND}
|
||||
- {pin_num: R14, pin_signal: USB1_DM, label: 'MCX_USB1_DM/L13[2]'}
|
||||
- {pin_num: T14, pin_signal: USB0_DM/WUU0_IN28, label: TP2}
|
||||
- {pin_num: U14, pin_signal: USB1_VBUS, label: MCX_USB1_VBUS}
|
||||
- {pin_num: B15, pin_signal: PIO0_3/TDI/FC1_P3/CT0_MAT1/UTICK_CAP1/HSCMP0_OUT/CMP1_IN1, label: 'P0_3/J23[8]/D16[3]/SJ17[1]'}
|
||||
- {pin_num: C15, pin_signal: PIO3_1/TRIG_IN1/FC6_P0/FC7_P6/CT_INP17/PWM0_B0/FLEXIO0_D9/FLEXSPI0_A_SS1_b/FREQME_CLK_OUT0, label: P3_1/TP31}
|
||||
- {pin_num: D15, pin_signal: PIO3_2/FC7_P0/CT4_MAT0/PWM0_X0/FLEXIO0_D10/SIM1_PD, label: 'P3_2/J9[20]/J7[8]'}
|
||||
- {pin_num: F15, pin_signal: PIO3_9/FC6_P5/FC7_P2/CT_INP5/PWM0_B2/FLEXIO0_D17/FLEXSPI0_A_DATA1/SIM0_RST/SAI0_TX_FS, label: 'P3_9/TP15/U8[2]/U7[D2]'}
|
||||
- {pin_num: H15, pin_signal: PIO3_15/FC8_P1/CT_INP7/PWM1_B1/FLEXIO0_D23/FLEXSPI0_A_DATA7/SAI0_RX_FS, label: 'P3_15/TP9/U7[E1]'}
|
||||
- {pin_num: J15, pin_signal: PIO3_16/FC8_P2/CT_INP8/PWM1_A2/FLEXIO0_D24/SIM0_CLK/SAI1_TX_BCLK, label: 'P3_16/SJ11[1]'}
|
||||
- {pin_num: K15, pin_signal: PIO3_17/WUU0_IN26/FC8_P3/CT_INP9/PWM1_B2/FLEXIO0_D25/SIM0_IO/SAI1_TX_FS, label: 'P3_17/J1[11]/SJ10[3]'}
|
||||
- {pin_num: M15, pin_signal: PIO3_23/FC6_P3/CT_INP11/PWM1_X3/FLEXIO0_D31/SAI1_TXD1, label: 'P3_23/J6[3]'}
|
||||
- {pin_num: P15, pin_signal: VDD_LDO_SYS/VOUT_SYS, label: VDD_LDO_SYS_IN}
|
||||
- {pin_num: R15, pin_signal: VDD_DCDC, label: VDD_DCDC}
|
||||
- {pin_num: T15, pin_signal: USB0_DP/WUU0_IN29, label: TP3}
|
||||
- {pin_num: A16, pin_signal: PIO0_1/TCLK/SWCLK/FC1_P1/CT_INP1, label: 'P0_1/SWCLK/J23[4]/D16[5]/J22[2]', identifier: DEBUG_SWD_SWDCLK}
|
||||
- {pin_num: B16, pin_signal: PIO0_2/TDO/SWO/FC1_P2/CT0_MAT0/UTICK_CAP0/I3C0_PUR, label: 'P0_2/SWO/J23[6]/D16[4]', identifier: DEBUG_SWD_SWO}
|
||||
- {pin_num: D16, pin_signal: PIO3_3/FC7_P1/CT4_MAT1/PWM0_X1/FLEXIO0_D11/SIM1_RST, label: 'P3_3/J9[19]/SJ12[1]'}
|
||||
- {pin_num: F16, pin_signal: PIO3_11/WUU0_IN24/FC6_P3/FC7_P5/CT1_MAT1/PWM0_B3/FLEXIO0_D19/FLEXSPI0_A_DATA3/SIM0_IO/SAI0_RXD0, label: 'P3_11/TP14/U8[7]/U7[D4]'}
|
||||
- {pin_num: G16, pin_signal: PIO3_12/FC7_P4/FC6_P4/CT1_MAT2/PWM1_A0/FLEXIO0_D20/FLEXSPI0_A_DATA4/SAI0_RXD1, label: 'P3_12/TP17/U7[D5]'}
|
||||
- {pin_num: H16, pin_signal: PIO3_13/FC7_P5/FC6_P5/CT1_MAT3/PWM1_B0/FLEXIO0_D21/FLEXSPI0_A_DATA5/SAI0_TXD1, label: 'P3_13/TP11/U7[E3]'}
|
||||
- {pin_num: K16, pin_signal: PIO3_18/FC6_P6/CT2_MAT0/PWM1_X0/FLEXIO0_D26/SAI1_RX_BCLK, label: 'P3_18/J1[9]'}
|
||||
- {pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0, label: 'P3_21/J6[4]/J1[15]'}
|
||||
- {pin_num: M16, pin_signal: PIO3_22/FC8_P6/FC6_P2/CT_INP10/PWM1_X2/FLEXIO0_D30/SIM0_VCCEN/SAI1_RXD1, label: 'P3_22/J6[5]'}
|
||||
- {pin_num: P16, pin_signal: VSS_DCDC, label: GND}
|
||||
- {pin_num: U16, pin_signal: PIO5_0/TRIG_IN10/LPTMR0_ALT2/EXTAL32K/ADC1_B8, label: 'P5_0/EXTAL32K/Y2[2]'}
|
||||
- {pin_num: A17, pin_signal: PIO0_0/TMS/SWDIO/FC1_P0/CT_INP0, label: 'P0_0/SWDIO/J23[2]/D16[6]', identifier: DEBUG_SWD_SWDIO}
|
||||
- {pin_num: B17, pin_signal: PIO3_0/WUU0_IN22/TRIG_IN0/FC7_P3/CT_INP16/PWM0_A0/FLEXIO0_D8/FLEXSPI0_A_SS0_b, label: 'P3_0/TP12/U8[1]/U7[C2]/U7[A3]'}
|
||||
- {pin_num: D17, pin_signal: PIO3_6/CLKOUT/FC6_P1/CT4_MAT2/PWM0_A1/FLEXIO0_D14/FLEXSPI0_A_DQS/SIM1_VCCEN/SAI1_MCLK/FREQME_CLK_OUT1, label: 'P3_6/TP8/U7[C3]'}
|
||||
- {pin_num: F17, pin_signal: PIO3_10/FC6_P2/FC7_P4/CT1_MAT0/PWM0_A3/FLEXIO0_D18/FLEXSPI0_A_DATA2/SIM0_CLK/SAI0_TXD0, label: 'P3_10/TP13/U8[3]/U7[C4]'}
|
||||
- {pin_num: H17, pin_signal: PIO3_14/WUU0_IN25/FC8_P0/CT_INP6/PWM1_A1/FLEXIO0_D22/FLEXSPI0_A_DATA6/SAI0_RX_BCLK, label: 'P3_14/TP10/U7[E2]'}
|
||||
- {pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS, label: 'P3_19/J5[1]/J1[13]'}
|
||||
- {pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0, label: 'P3_20/J6[6]/J1[5]'}
|
||||
- {pin_num: P17, pin_signal: DCDC_LX, label: DCDC_LX}
|
||||
- {pin_num: T17, pin_signal: VDD_BAT, label: 'VDD_BAT/J27[2]'}
|
||||
- {pin_num: U17, pin_signal: PIO5_1/TRIG_OUT6/LPTMR1_ALT2/XTAL32K/ADC1_B9, label: 'P5_1/XTAL32K/Y2[1]'}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_port.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void)
|
||||
{
|
||||
BOARD_InitDEBUG_UARTPins();
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitDEBUG_UARTPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: A1, peripheral: LP_FLEXCOMM4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
|
||||
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
|
||||
invert_input: normal}
|
||||
- {pin_num: B1, peripheral: LP_FLEXCOMM4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
|
||||
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitDEBUG_UARTPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitDEBUG_UARTPins(void)
|
||||
{
|
||||
/* Enables the clock for PORT1: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port1);
|
||||
|
||||
const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as FC4_P0 */
|
||||
kPORT_MuxAlt2,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT1_8 (pin A1) is configured as FC4_P0 */
|
||||
PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
|
||||
|
||||
const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as FC4_P1 */
|
||||
kPORT_MuxAlt2,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT1_9 (pin B1) is configured as FC4_P1 */
|
||||
PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitSWD_DEBUGPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: A16, peripheral: SWD, signal: SWCLK, pin_signal: PIO0_1/TCLK/SWCLK/FC1_P1/CT_INP1, slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down,
|
||||
pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: A17, peripheral: SWD, signal: SWDIO, pin_signal: PIO0_0/TMS/SWDIO/FC1_P0/CT_INP0, slew_rate: fast, open_drain: disable, drive_strength: high, pull_select: up,
|
||||
pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: B16, peripheral: SWD, signal: SWO, pin_signal: PIO0_2/TDO/SWO/FC1_P2/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable, drive_strength: high,
|
||||
pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitSWD_DEBUGPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitSWD_DEBUGPins(void)
|
||||
{
|
||||
/* Enables the clock for PORT0 controller: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port0);
|
||||
|
||||
const port_pin_config_t DEBUG_SWD_SWDIO = {/* Internal pull-up resistor is enabled */
|
||||
kPORT_PullUp,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* High drive strength is configured */
|
||||
kPORT_HighDriveStrength,
|
||||
/* Pin is configured as SWDIO */
|
||||
kPORT_MuxAlt1,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_0 (pin A17) is configured as SWDIO */
|
||||
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, &DEBUG_SWD_SWDIO);
|
||||
|
||||
const port_pin_config_t DEBUG_SWD_SWDCLK = {/* Internal pull-down resistor is enabled */
|
||||
kPORT_PullDown,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as SWCLK */
|
||||
kPORT_MuxAlt1,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_1 (pin A16) is configured as SWCLK */
|
||||
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, &DEBUG_SWD_SWDCLK);
|
||||
|
||||
const port_pin_config_t DEBUG_SWD_SWO = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* High drive strength is configured */
|
||||
kPORT_HighDriveStrength,
|
||||
/* Pin is configured as SWO */
|
||||
kPORT_MuxAlt1,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_2 (pin B16) is configured as SWO */
|
||||
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, &DEBUG_SWD_SWO);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitLEDsPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: C4, peripheral: GPIO1, signal: 'GPIO, 2', pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0,
|
||||
direction: OUTPUT, slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: B12, peripheral: GPIO0, signal: 'GPIO, 10', pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10, direction: OUTPUT, slew_rate: fast, open_drain: disable,
|
||||
drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: E10, peripheral: GPIO0, signal: 'GPIO, 27', pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19, direction: OUTPUT, slew_rate: fast, open_drain: disable, drive_strength: low,
|
||||
pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitLEDsPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitLEDsPins(void)
|
||||
{
|
||||
/* Enables the clock for GPIO0: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Gpio0);
|
||||
/* Enables the clock for GPIO1: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Gpio1);
|
||||
/* Enables the clock for PORT0 controller: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port0);
|
||||
/* Enables the clock for PORT1: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port1);
|
||||
|
||||
gpio_pin_config_t LED_RED_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_10 (pin B12) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config);
|
||||
|
||||
gpio_pin_config_t LED_GREEN_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_27 (pin E10) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config);
|
||||
|
||||
gpio_pin_config_t LED_BLUE_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO1_2 (pin C4) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config);
|
||||
|
||||
const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as PIO0_10 */
|
||||
kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_10 (pin B12) is configured as PIO0_10 */
|
||||
PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED);
|
||||
|
||||
const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as PIO0_27 */
|
||||
kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_27 (pin E10) is configured as PIO0_27 */
|
||||
PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN);
|
||||
|
||||
const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as PIO1_2 */
|
||||
kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT1_2 (pin C4) is configured as PIO1_2 */
|
||||
PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitBUTTONsPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: C14, peripheral: GPIO0, signal: 'GPIO, 6', pin_signal: PIO0_6/ISPMODE_N/FC0_P2/FC1_P6/CT_INP2/HSCMP2_OUT/PDM0_DATA1/CLKOUT/TSI0_CH10, direction: INPUT,
|
||||
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: B7, peripheral: GPIO0, signal: 'GPIO, 23', pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, direction: INPUT, slew_rate: fast,
|
||||
open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBUTTONsPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBUTTONsPins(void)
|
||||
{
|
||||
/* Enables the clock for GPIO0: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Gpio0);
|
||||
/* Enables the clock for PORT0 controller: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port0);
|
||||
|
||||
gpio_pin_config_t SW3_config = {
|
||||
.pinDirection = kGPIO_DigitalInput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_6 (pin C14) */
|
||||
GPIO_PinInit(BOARD_INITBUTTONSPINS_SW3_GPIO, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3_config);
|
||||
|
||||
gpio_pin_config_t SW2_config = {
|
||||
.pinDirection = kGPIO_DigitalInput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_23 (pin B7) */
|
||||
GPIO_PinInit(BOARD_INITBUTTONSPINS_SW2_GPIO, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2_config);
|
||||
|
||||
const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as PIO0_23 */
|
||||
kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_23 (pin B7) is configured as PIO0_23 */
|
||||
PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW2_PORT, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2);
|
||||
|
||||
const port_pin_config_t SW3 = {/* Internal pull-up resistor is enabled */
|
||||
kPORT_PullUp,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as PIO0_6 */
|
||||
kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_6 (pin C14) is configured as PIO0_6 */
|
||||
PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW3_PORT, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@ -1,184 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022-2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/*! @name PORT1_8 (coord A1), P1_8/J9[32]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT PORT1 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 8U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 8U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT1_9 (coord B1), P1_9/J9[30]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT PORT1 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 9U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 9U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitDEBUG_UARTPins(void);
|
||||
|
||||
/*! @name PORT0_1 (coord A16), P0_1/SWCLK/J23[4]/D16[5]/J22[2]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 1U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 1U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_0 (coord A17), P0_0/SWDIO/J23[2]/D16[6]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 0U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_2 (coord B16), P0_2/SWO/J23[6]/D16[4]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 2U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitSWD_DEBUGPins(void);
|
||||
|
||||
/*! @name PORT1_2 (coord C4), P1_2/SJ4[1]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO1 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN 2U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 2U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_PORT PORT1 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_PIN 2U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_10 (coord B12), P0_10/SJ5[1]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO0 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 10U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 10U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PIN 10U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 10U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_27 (coord E10), P0_27/SJ6[1]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO0 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN 27U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 27U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PIN 27U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 27U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitLEDsPins(void);
|
||||
|
||||
/*! @name PORT0_6 (coord C14), P0_6/J23[7]/SW3[3]/SW3[4]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_GPIO GPIO0 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN 6U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_PIN 6U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_PIN_MASK (1U << 6U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_23 (coord B7), P0_23/SJ9[1]/SW2[3]/SW2[4]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_GPIO GPIO0 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_GPIO_PIN 23U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_GPIO_PIN_MASK (1U << 23U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_PIN 23U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_PIN_MASK (1U << 23U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBUTTONsPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@ -1,499 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018-2019, 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*! *********************************************************************************
|
||||
*************************************************************************************
|
||||
* Include
|
||||
*************************************************************************************
|
||||
********************************************************************************** */
|
||||
#include "fsl_component_generic_list.h"
|
||||
|
||||
#if defined(OSA_USED)
|
||||
#include "fsl_os_abstraction.h"
|
||||
#if (defined(USE_RTOS) && (USE_RTOS > 0U))
|
||||
#define LIST_ENTER_CRITICAL() \
|
||||
OSA_SR_ALLOC(); \
|
||||
OSA_ENTER_CRITICAL()
|
||||
#define LIST_EXIT_CRITICAL() OSA_EXIT_CRITICAL()
|
||||
#else
|
||||
#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ();
|
||||
#define LIST_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask);
|
||||
#endif
|
||||
#else
|
||||
#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ();
|
||||
#define LIST_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask);
|
||||
#endif
|
||||
|
||||
static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement)
|
||||
{
|
||||
list_status_t listStatus = kLIST_Ok;
|
||||
#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U))
|
||||
list_element_handle_t element = list->head;
|
||||
#endif
|
||||
if ((list->max != 0U) && (list->max == list->size))
|
||||
{
|
||||
listStatus = kLIST_Full; /*List is full*/
|
||||
}
|
||||
#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U))
|
||||
else
|
||||
{
|
||||
while (element != NULL) /*Scan list*/
|
||||
{
|
||||
/* Determine if element is duplicated */
|
||||
if (element == newElement)
|
||||
{
|
||||
listStatus = kLIST_DuplicateError;
|
||||
break;
|
||||
}
|
||||
element = element->next;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return listStatus;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
*************************************************************************************
|
||||
* Public functions
|
||||
*************************************************************************************
|
||||
********************************************************************************** */
|
||||
/*! *********************************************************************************
|
||||
* \brief Initializes the list descriptor.
|
||||
*
|
||||
* \param[in] list - LIST_ handle to init.
|
||||
* max - Maximum number of elements in list. 0 for unlimited.
|
||||
*
|
||||
* \return void.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
void LIST_Init(list_handle_t list, uint32_t max)
|
||||
{
|
||||
list->head = NULL;
|
||||
list->tail = NULL;
|
||||
list->max = max;
|
||||
list->size = 0;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets the list that contains the given element.
|
||||
*
|
||||
* \param[in] element - Handle of the element.
|
||||
*
|
||||
* \return NULL if element is orphan.
|
||||
* Handle of the list the element is inserted into.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_handle_t LIST_GetList(list_element_handle_t listElement)
|
||||
{
|
||||
return listElement->list;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Links element to the tail of the list.
|
||||
*
|
||||
* \param[in] list - ID of list to insert into.
|
||||
* element - element to add
|
||||
*
|
||||
* \return kLIST_Full if list is full.
|
||||
* kLIST_Ok if insertion was successful.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement)
|
||||
{
|
||||
LIST_ENTER_CRITICAL();
|
||||
list_status_t listStatus = kLIST_Ok;
|
||||
|
||||
listStatus = LIST_Error_Check(list, listElement);
|
||||
if (listStatus == kLIST_Ok) /* Avoiding list status error */
|
||||
{
|
||||
if (list->size == 0U)
|
||||
{
|
||||
list->head = listElement;
|
||||
}
|
||||
else
|
||||
{
|
||||
list->tail->next = listElement;
|
||||
}
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
#else
|
||||
listElement->prev = list->tail;
|
||||
#endif
|
||||
listElement->list = list;
|
||||
listElement->next = NULL;
|
||||
list->tail = listElement;
|
||||
list->size++;
|
||||
}
|
||||
|
||||
LIST_EXIT_CRITICAL();
|
||||
return listStatus;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Links element to the head of the list.
|
||||
*
|
||||
* \param[in] list - ID of list to insert into.
|
||||
* element - element to add
|
||||
*
|
||||
* \return kLIST_Full if list is full.
|
||||
* kLIST_Ok if insertion was successful.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement)
|
||||
{
|
||||
LIST_ENTER_CRITICAL();
|
||||
list_status_t listStatus = kLIST_Ok;
|
||||
|
||||
listStatus = LIST_Error_Check(list, listElement);
|
||||
if (listStatus == kLIST_Ok) /* Avoiding list status error */
|
||||
{
|
||||
/* Links element to the head of the list */
|
||||
if (list->size == 0U)
|
||||
{
|
||||
list->tail = listElement;
|
||||
}
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
#else
|
||||
else
|
||||
{
|
||||
list->head->prev = listElement;
|
||||
}
|
||||
listElement->prev = NULL;
|
||||
#endif
|
||||
listElement->list = list;
|
||||
listElement->next = list->head;
|
||||
list->head = listElement;
|
||||
list->size++;
|
||||
}
|
||||
|
||||
LIST_EXIT_CRITICAL();
|
||||
return listStatus;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Unlinks element from the head of the list.
|
||||
*
|
||||
* \param[in] list - ID of list to remove from.
|
||||
*
|
||||
* \return NULL if list is empty.
|
||||
* ID of removed element(pointer) if removal was successful.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_element_handle_t LIST_RemoveHead(list_handle_t list)
|
||||
{
|
||||
list_element_handle_t listElement;
|
||||
|
||||
LIST_ENTER_CRITICAL();
|
||||
|
||||
if ((NULL == list) || (list->size == 0U))
|
||||
{
|
||||
listElement = NULL; /*LIST_ is empty*/
|
||||
}
|
||||
else
|
||||
{
|
||||
listElement = list->head;
|
||||
list->size--;
|
||||
if (list->size == 0U)
|
||||
{
|
||||
list->tail = NULL;
|
||||
}
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
#else
|
||||
else
|
||||
{
|
||||
listElement->next->prev = NULL;
|
||||
}
|
||||
#endif
|
||||
listElement->list = NULL;
|
||||
list->head = listElement->next; /*Is NULL if element is head*/
|
||||
}
|
||||
|
||||
LIST_EXIT_CRITICAL();
|
||||
return listElement;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets head element ID.
|
||||
*
|
||||
* \param[in] list - ID of list.
|
||||
*
|
||||
* \return NULL if list is empty.
|
||||
* ID of head element if list is not empty.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_element_handle_t LIST_GetHead(list_handle_t list)
|
||||
{
|
||||
return list->head;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets next element ID.
|
||||
*
|
||||
* \param[in] element - ID of the element.
|
||||
*
|
||||
* \return NULL if element is tail.
|
||||
* ID of next element if exists.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_element_handle_t LIST_GetNext(list_element_handle_t listElement)
|
||||
{
|
||||
return listElement->next;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets previous element ID.
|
||||
*
|
||||
* \param[in] element - ID of the element.
|
||||
*
|
||||
* \return NULL if element is head.
|
||||
* ID of previous element if exists.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_element_handle_t LIST_GetPrev(list_element_handle_t listElement)
|
||||
{
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
return NULL;
|
||||
#else
|
||||
return listElement->prev;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Unlinks an element from its list.
|
||||
*
|
||||
* \param[in] element - ID of the element to remove.
|
||||
*
|
||||
* \return kLIST_OrphanElement if element is not part of any list.
|
||||
* kLIST_Ok if removal was successful.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_status_t LIST_RemoveElement(list_element_handle_t listElement)
|
||||
{
|
||||
list_status_t listStatus = kLIST_Ok;
|
||||
LIST_ENTER_CRITICAL();
|
||||
|
||||
if (listElement->list == NULL)
|
||||
{
|
||||
listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
|
||||
}
|
||||
else
|
||||
{
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
list_element_handle_t element_list = listElement->list->head;
|
||||
list_element_handle_t element_Prev = NULL;
|
||||
while (NULL != element_list)
|
||||
{
|
||||
if (listElement->list->head == listElement)
|
||||
{
|
||||
listElement->list->head = element_list->next;
|
||||
break;
|
||||
}
|
||||
if (element_list->next == listElement)
|
||||
{
|
||||
element_Prev = element_list;
|
||||
element_list->next = listElement->next;
|
||||
break;
|
||||
}
|
||||
element_list = element_list->next;
|
||||
}
|
||||
if (listElement->next == NULL)
|
||||
{
|
||||
listElement->list->tail = element_Prev;
|
||||
}
|
||||
#else
|
||||
if (listElement->prev == NULL) /*Element is head or solo*/
|
||||
{
|
||||
listElement->list->head = listElement->next; /*is null if solo*/
|
||||
}
|
||||
if (listElement->next == NULL) /*Element is tail or solo*/
|
||||
{
|
||||
listElement->list->tail = listElement->prev; /*is null if solo*/
|
||||
}
|
||||
if (listElement->prev != NULL) /*Element is not head*/
|
||||
{
|
||||
listElement->prev->next = listElement->next;
|
||||
}
|
||||
if (listElement->next != NULL) /*Element is not tail*/
|
||||
{
|
||||
listElement->next->prev = listElement->prev;
|
||||
}
|
||||
#endif
|
||||
listElement->list->size--;
|
||||
listElement->list = NULL;
|
||||
}
|
||||
|
||||
LIST_EXIT_CRITICAL();
|
||||
return listStatus;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Links an element in the previous position relative to a given member
|
||||
* of a list.
|
||||
*
|
||||
* \param[in] element - ID of a member of a list.
|
||||
* newElement - new element to insert before the given member.
|
||||
*
|
||||
* \return kLIST_OrphanElement if element is not part of any list.
|
||||
* kLIST_Full if list is full.
|
||||
* kLIST_Ok if insertion was successful.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement)
|
||||
{
|
||||
list_status_t listStatus = kLIST_Ok;
|
||||
LIST_ENTER_CRITICAL();
|
||||
|
||||
if (listElement->list == NULL)
|
||||
{
|
||||
listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
|
||||
}
|
||||
else
|
||||
{
|
||||
listStatus = LIST_Error_Check(listElement->list, newElement);
|
||||
if (listStatus == kLIST_Ok)
|
||||
{
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
list_element_handle_t element_list = listElement->list->head;
|
||||
while (NULL != element_list)
|
||||
{
|
||||
if ((element_list->next == listElement) || (element_list == listElement))
|
||||
{
|
||||
if (element_list == listElement)
|
||||
{
|
||||
listElement->list->head = newElement;
|
||||
}
|
||||
else
|
||||
{
|
||||
element_list->next = newElement;
|
||||
}
|
||||
newElement->list = listElement->list;
|
||||
newElement->next = listElement;
|
||||
listElement->list->size++;
|
||||
break;
|
||||
}
|
||||
element_list = element_list->next;
|
||||
}
|
||||
|
||||
#else
|
||||
if (listElement->prev == NULL) /*Element is list head*/
|
||||
{
|
||||
listElement->list->head = newElement;
|
||||
}
|
||||
else
|
||||
{
|
||||
listElement->prev->next = newElement;
|
||||
}
|
||||
newElement->list = listElement->list;
|
||||
listElement->list->size++;
|
||||
newElement->next = listElement;
|
||||
newElement->prev = listElement->prev;
|
||||
listElement->prev = newElement;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
LIST_EXIT_CRITICAL();
|
||||
return listStatus;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets the current size of a list.
|
||||
*
|
||||
* \param[in] list - ID of the list.
|
||||
*
|
||||
* \return Current size of the list.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
uint32_t LIST_GetSize(list_handle_t list)
|
||||
{
|
||||
return list->size;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets the number of free places in the list.
|
||||
*
|
||||
* \param[in] list - ID of the list.
|
||||
*
|
||||
* \return Available size of the list.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
uint32_t LIST_GetAvailableSize(list_handle_t list)
|
||||
{
|
||||
return (list->max - list->size); /*Gets the number of free places in the list*/
|
||||
}
|
||||
@ -1,219 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018-2020, 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _GENERIC_LIST_H_
|
||||
#define _GENERIC_LIST_H_
|
||||
|
||||
#ifndef SDK_COMPONENT_DEPENDENCY_FSL_COMMON
|
||||
#define SDK_COMPONENT_DEPENDENCY_FSL_COMMON (1U)
|
||||
#endif
|
||||
#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
|
||||
#include "fsl_common.h"
|
||||
#else
|
||||
#endif
|
||||
/*!
|
||||
* @addtogroup GenericList
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**********************************************************************************
|
||||
* Include
|
||||
***********************************************************************************/
|
||||
|
||||
/**********************************************************************************
|
||||
* Public macro definitions
|
||||
***********************************************************************************/
|
||||
/*! @brief Definition to determine whether use list light. */
|
||||
#ifndef GENERIC_LIST_LIGHT
|
||||
#define GENERIC_LIST_LIGHT (1)
|
||||
#endif
|
||||
|
||||
/*! @brief Definition to determine whether enable list duplicated checking. */
|
||||
#ifndef GENERIC_LIST_DUPLICATED_CHECKING
|
||||
#define GENERIC_LIST_DUPLICATED_CHECKING (0)
|
||||
#endif
|
||||
|
||||
/**********************************************************************************
|
||||
* Public type definitions
|
||||
***********************************************************************************/
|
||||
/*! @brief The list status */
|
||||
#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
|
||||
typedef enum _list_status
|
||||
{
|
||||
kLIST_Ok = kStatus_Success, /*!< Success */
|
||||
kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */
|
||||
kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */
|
||||
kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */
|
||||
kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */
|
||||
kLIST_NotSupport = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support */
|
||||
} list_status_t;
|
||||
#else
|
||||
typedef enum _list_status
|
||||
{
|
||||
kLIST_Ok = 0, /*!< Success */
|
||||
kLIST_DuplicateError = 1, /*!< Duplicate Error */
|
||||
kLIST_Full = 2, /*!< FULL */
|
||||
kLIST_Empty = 3, /*!< Empty */
|
||||
kLIST_OrphanElement = 4, /*!< Orphan Element */
|
||||
kLIST_NotSupport = 5, /*!< Not Support */
|
||||
} list_status_t;
|
||||
#endif
|
||||
|
||||
/*! @brief The list structure*/
|
||||
typedef struct list_label
|
||||
{
|
||||
struct list_element_tag *head; /*!< list head */
|
||||
struct list_element_tag *tail; /*!< list tail */
|
||||
uint32_t size; /*!< list size */
|
||||
uint32_t max; /*!< list max number of elements */
|
||||
} list_label_t, *list_handle_t;
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
/*! @brief The list element*/
|
||||
typedef struct list_element_tag
|
||||
{
|
||||
struct list_element_tag *next; /*!< next list element */
|
||||
struct list_label *list; /*!< pointer to the list */
|
||||
} list_element_t, *list_element_handle_t;
|
||||
#else
|
||||
/*! @brief The list element*/
|
||||
typedef struct list_element_tag
|
||||
{
|
||||
struct list_element_tag *next; /*!< next list element */
|
||||
struct list_element_tag *prev; /*!< previous list element */
|
||||
struct list_label *list; /*!< pointer to the list */
|
||||
} list_element_t, *list_element_handle_t;
|
||||
#endif
|
||||
/**********************************************************************************
|
||||
* Public prototypes
|
||||
***********************************************************************************/
|
||||
/**********************************************************************************
|
||||
* API
|
||||
**********************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
/*!
|
||||
* @brief Initialize the list.
|
||||
*
|
||||
* This function initialize the list.
|
||||
*
|
||||
* @param list - List handle to initialize.
|
||||
* @param max - Maximum number of elements in list. 0 for unlimited.
|
||||
*/
|
||||
void LIST_Init(list_handle_t list, uint32_t max);
|
||||
|
||||
/*!
|
||||
* @brief Gets the list that contains the given element.
|
||||
*
|
||||
*
|
||||
* @param listElement - Handle of the element.
|
||||
* @retval NULL if element is orphan, Handle of the list the element is inserted into.
|
||||
*/
|
||||
list_handle_t LIST_GetList(list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Links element to the head of the list.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
* @param listElement - Handle of the element.
|
||||
* @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
|
||||
*/
|
||||
list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Links element to the tail of the list.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
* @param listElement - Handle of the element.
|
||||
* @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
|
||||
*/
|
||||
list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Unlinks element from the head of the list.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
*
|
||||
* @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
|
||||
*/
|
||||
list_element_handle_t LIST_RemoveHead(list_handle_t list);
|
||||
|
||||
/*!
|
||||
* @brief Gets head element handle.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
*
|
||||
* @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
|
||||
*/
|
||||
list_element_handle_t LIST_GetHead(list_handle_t list);
|
||||
|
||||
/*!
|
||||
* @brief Gets next element handle for given element handle.
|
||||
*
|
||||
* @param listElement - Handle of the element.
|
||||
*
|
||||
* @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
|
||||
*/
|
||||
list_element_handle_t LIST_GetNext(list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Gets previous element handle for given element handle.
|
||||
*
|
||||
* @param listElement - Handle of the element.
|
||||
*
|
||||
* @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
|
||||
*/
|
||||
list_element_handle_t LIST_GetPrev(list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Unlinks an element from its list.
|
||||
*
|
||||
* @param listElement - Handle of the element.
|
||||
*
|
||||
* @retval kLIST_OrphanElement if element is not part of any list.
|
||||
* @retval kLIST_Ok if removal was successful.
|
||||
*/
|
||||
list_status_t LIST_RemoveElement(list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Links an element in the previous position relative to a given member of a list.
|
||||
*
|
||||
* @param listElement - Handle of the element.
|
||||
* @param newElement - New element to insert before the given member.
|
||||
*
|
||||
* @retval kLIST_OrphanElement if element is not part of any list.
|
||||
* @retval kLIST_Ok if removal was successful.
|
||||
*/
|
||||
list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement);
|
||||
|
||||
/*!
|
||||
* @brief Gets the current size of a list.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
*
|
||||
* @retval Current size of the list.
|
||||
*/
|
||||
uint32_t LIST_GetSize(list_handle_t list);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of free places in the list.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
*
|
||||
* @retval Available size of the list.
|
||||
*/
|
||||
uint32_t LIST_GetAvailableSize(list_handle_t list);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/*! @}*/
|
||||
#endif /*_GENERIC_LIST_H_*/
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,856 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_MANAGER_H__
|
||||
#define __SERIAL_MANAGER_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup serialmanager
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE == 0U))
|
||||
#error When SERIAL_MANAGER_NON_BLOCKING_MODE=0, DEBUG_CONSOLE_TRANSFER_NON_BLOCKING can not be set.
|
||||
#else
|
||||
#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
|
||||
#endif
|
||||
#else
|
||||
#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
|
||||
#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or ring buffer flow control (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL
|
||||
#define SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_UART
|
||||
#define SERIAL_PORT_TYPE_UART (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable uart dma port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_UART_DMA
|
||||
#define SERIAL_PORT_TYPE_UART_DMA (0U)
|
||||
#endif
|
||||
/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_USBCDC
|
||||
#define SERIAL_PORT_TYPE_USBCDC (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_SWO
|
||||
#define SERIAL_PORT_TYPE_SWO (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_VIRTUAL
|
||||
#define SERIAL_PORT_TYPE_VIRTUAL (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable rPMSG port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_RPMSG
|
||||
#define SERIAL_PORT_TYPE_RPMSG (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable SPI Master port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_SPI_MASTER
|
||||
#define SERIAL_PORT_TYPE_SPI_MASTER (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable SPI Slave port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_SPI_SLAVE
|
||||
#define SERIAL_PORT_TYPE_SPI_SLAVE (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable BLE WU port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_BLE_WU
|
||||
#define SERIAL_PORT_TYPE_BLE_WU (0U)
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE == 1U))
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE == 0U))
|
||||
#warning When SERIAL_PORT_TYPE_SPI_SLAVE=1, SERIAL_MANAGER_NON_BLOCKING_MODE should be set.
|
||||
#undef SERIAL_MANAGER_NON_BLOCKING_MODE
|
||||
#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! @brief Set the default delay time in ms used by SerialManager_WriteTimeDelay(). */
|
||||
#ifndef SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE
|
||||
#define SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE (1U)
|
||||
#endif
|
||||
|
||||
/*! @brief Set the default delay time in ms used by SerialManager_ReadTimeDelay(). */
|
||||
#ifndef SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE
|
||||
#define SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE (1U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable SerialManager_Task() handle RX data available notify */
|
||||
#ifndef SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY
|
||||
#define SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY (0U)
|
||||
#endif
|
||||
#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U))
|
||||
#ifndef OSA_USED
|
||||
#error When SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY=1, OSA_USED must be set.
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! @brief Set serial manager write handle size */
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)
|
||||
#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)
|
||||
#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U)
|
||||
#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE (4U)
|
||||
#else
|
||||
#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)
|
||||
#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)
|
||||
#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U)
|
||||
#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE (4U)
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
|
||||
#include "fsl_component_serial_port_uart.h"
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
#include "fsl_component_serial_port_uart.h"
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
|
||||
#include "fsl_component_serial_port_rpmsg.h"
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
|
||||
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#error The serial manager blocking mode cannot be supported for USB CDC.
|
||||
#endif
|
||||
|
||||
#include "fsl_component_serial_port_usb.h"
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
|
||||
#include "fsl_component_serial_port_swo.h"
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
|
||||
#include "fsl_component_serial_port_spi.h"
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
|
||||
#include "fsl_component_serial_port_spi.h"
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
|
||||
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#error The serial manager blocking mode cannot be supported for USB CDC.
|
||||
#endif
|
||||
|
||||
#include "fsl_component_serial_port_virtual.h"
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
|
||||
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#error The serial manager blocking mode cannot be supported for BLE WU.
|
||||
#endif /* SERIAL_MANAGER_NON_BLOCKING_MODE */
|
||||
|
||||
#include "fsl_component_serial_port_ble_wu.h"
|
||||
#endif /* SERIAL_PORT_TYPE_BLE_WU */
|
||||
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U
|
||||
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
|
||||
|
||||
#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
#if (SERIAL_PORT_UART_DMA_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_DMA_HANDLE_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
|
||||
|
||||
#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
|
||||
|
||||
#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
|
||||
#if (SERIAL_PORT_SPI_MASTER_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SPI_MASTER_HANDLE_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
|
||||
#if (SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
|
||||
|
||||
#if (SERIAL_PORT_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_VIRTUAL_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
|
||||
|
||||
#if (SERIAL_PORT_RPMSG_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_RPMSG_HANDLE_SIZE
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
|
||||
|
||||
#if (SERIAL_PORT_BLE_WU_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_BLE_WU_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */
|
||||
#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))
|
||||
#else
|
||||
#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO, SERIAL_PORT_TYPE_VIRTUAL, and SERIAL_PORT_TYPE_BLE_WU should not be cleared at same time.
|
||||
#endif
|
||||
|
||||
/*! @brief Macro to determine whether use common task. */
|
||||
#ifndef SERIAL_MANAGER_USE_COMMON_TASK
|
||||
#define SERIAL_MANAGER_USE_COMMON_TASK (0U)
|
||||
#endif
|
||||
|
||||
#if defined(OSA_USED)
|
||||
#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
|
||||
#include "fsl_component_common_task.h"
|
||||
#endif
|
||||
/*! @brief Enable or disable SerialManager_Task() handle TX to prevent recursive calling */
|
||||
#ifndef SERIAL_MANAGER_TASK_HANDLE_TX
|
||||
#define SERIAL_MANAGER_TASK_HANDLE_TX (1U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)))
|
||||
#include "fsl_os_abstraction.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! @brief Definition of serial manager handle size. */
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)))
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE \
|
||||
(SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U + OSA_TASK_HANDLE_SIZE + OSA_EVENT_HANDLE_SIZE)
|
||||
#else /*defined(OSA_USED)*/
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U)
|
||||
#endif /*defined(OSA_USED)*/
|
||||
#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 16U)
|
||||
#else
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
|
||||
#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Defines the serial manager handle
|
||||
*
|
||||
* This macro is used to define a 4 byte aligned serial manager handle.
|
||||
* Then use "(serial_handle_t)name" to get the serial manager handle.
|
||||
*
|
||||
* The macro should be global and could be optional. You could also define serial manager handle by yourself.
|
||||
*
|
||||
* This is an example,
|
||||
* @code
|
||||
* SERIAL_MANAGER_HANDLE_DEFINE(serialManagerHandle);
|
||||
* @endcode
|
||||
*
|
||||
* @param name The name string of the serial manager handle.
|
||||
*/
|
||||
#define SERIAL_MANAGER_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
#define SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
/*!
|
||||
* @brief Defines the serial manager write handle
|
||||
*
|
||||
* This macro is used to define a 4 byte aligned serial manager write handle.
|
||||
* Then use "(serial_write_handle_t)name" to get the serial manager write handle.
|
||||
*
|
||||
* The macro should be global and could be optional. You could also define serial manager write handle by yourself.
|
||||
*
|
||||
* This is an example,
|
||||
* @code
|
||||
* SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialManagerwriteHandle);
|
||||
* @endcode
|
||||
*
|
||||
* @param name The name string of the serial manager write handle.
|
||||
*/
|
||||
#define SERIAL_MANAGER_WRITE_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
/*!
|
||||
* @brief Defines the serial manager read handle
|
||||
*
|
||||
* This macro is used to define a 4 byte aligned serial manager read handle.
|
||||
* Then use "(serial_read_handle_t)name" to get the serial manager read handle.
|
||||
*
|
||||
* The macro should be global and could be optional. You could also define serial manager read handle by yourself.
|
||||
*
|
||||
* This is an example,
|
||||
* @code
|
||||
* SERIAL_MANAGER_READ_HANDLE_DEFINE(serialManagerReadHandle);
|
||||
* @endcode
|
||||
*
|
||||
* @param name The name string of the serial manager read handle.
|
||||
*/
|
||||
#define SERIAL_MANAGER_READ_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
#define SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
|
||||
/*! @brief Macro to set serial manager task priority. */
|
||||
#ifndef SERIAL_MANAGER_TASK_PRIORITY
|
||||
#define SERIAL_MANAGER_TASK_PRIORITY (2U)
|
||||
#endif
|
||||
|
||||
/*! @brief Macro to set serial manager task stack size. */
|
||||
#ifndef SERIAL_MANAGER_TASK_STACK_SIZE
|
||||
#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)
|
||||
#endif
|
||||
|
||||
/*! @brief The handle of the serial manager module */
|
||||
typedef void *serial_handle_t;
|
||||
|
||||
/*! @brief The write handle of the serial manager module */
|
||||
typedef void *serial_write_handle_t;
|
||||
|
||||
/*! @brief The read handle of the serial manager module */
|
||||
typedef void *serial_read_handle_t;
|
||||
|
||||
#ifndef _SERIAL_PORT_T_
|
||||
#define _SERIAL_PORT_T_
|
||||
/*! @brief serial port type*/
|
||||
typedef enum _serial_port_type
|
||||
{
|
||||
kSerialPort_None = 0U, /*!< Serial port is none */
|
||||
kSerialPort_Uart = 1U, /*!< Serial port UART */
|
||||
kSerialPort_UsbCdc, /*!< Serial port USB CDC */
|
||||
kSerialPort_Swo, /*!< Serial port SWO */
|
||||
kSerialPort_Virtual, /*!< Serial port Virtual */
|
||||
kSerialPort_Rpmsg, /*!< Serial port RPMSG */
|
||||
kSerialPort_UartDma, /*!< Serial port UART DMA*/
|
||||
kSerialPort_SpiMaster, /*!< Serial port SPIMASTER*/
|
||||
kSerialPort_SpiSlave, /*!< Serial port SPISLAVE*/
|
||||
kSerialPort_BleWu, /*!< Serial port BLE WU */
|
||||
} serial_port_type_t;
|
||||
#endif
|
||||
|
||||
/*! @brief serial manager type*/
|
||||
typedef enum _serial_manager_type
|
||||
{
|
||||
kSerialManager_NonBlocking = 0x0U, /*!< None blocking handle*/
|
||||
kSerialManager_Blocking = 0x8F41U, /*!< Blocking handle*/
|
||||
} serial_manager_type_t;
|
||||
/*! @brief serial manager config structure*/
|
||||
typedef struct _serial_manager_config
|
||||
{
|
||||
#if defined(SERIAL_MANAGER_NON_BLOCKING_MODE)
|
||||
uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware.
|
||||
Besides, the memory space cannot be free during the lifetime of the serial
|
||||
manager module. */
|
||||
uint32_t ringBufferSize; /*!< The size of the ring buffer */
|
||||
#endif
|
||||
serial_port_type_t type; /*!< Serial port type */
|
||||
serial_manager_type_t blockType; /*!< Serial manager port type */
|
||||
void *portConfig; /*!< Serial port configuration */
|
||||
} serial_manager_config_t;
|
||||
|
||||
/*! @brief serial manager error code*/
|
||||
typedef enum _serial_manager_status
|
||||
{
|
||||
kStatus_SerialManager_Success = kStatus_Success, /*!< Success */
|
||||
kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */
|
||||
kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */
|
||||
kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */
|
||||
kStatus_SerialManager_Canceled =
|
||||
MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */
|
||||
kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */
|
||||
kStatus_SerialManager_RingBufferOverflow =
|
||||
MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */
|
||||
kStatus_SerialManager_NotConnected = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 7), /*!< The host is not connected */
|
||||
} serial_manager_status_t;
|
||||
|
||||
/*! @brief Callback message structure */
|
||||
typedef struct _serial_manager_callback_message
|
||||
{
|
||||
uint8_t *buffer; /*!< Transferred buffer */
|
||||
uint32_t length; /*!< Transferred data length */
|
||||
} serial_manager_callback_message_t;
|
||||
|
||||
/*! @brief serial manager callback function */
|
||||
typedef void (*serial_manager_callback_t)(void *callbackParam,
|
||||
serial_manager_callback_message_t *message,
|
||||
serial_manager_status_t status);
|
||||
|
||||
/*! @brief serial manager Lowpower Critical callback function */
|
||||
typedef int32_t (*serial_manager_lowpower_critical_callback_t)(int32_t power_mode);
|
||||
typedef struct _serial_manager_lowpower_critical_CBs_t
|
||||
{
|
||||
serial_manager_lowpower_critical_callback_t serialEnterLowpowerCriticalFunc;
|
||||
serial_manager_lowpower_critical_callback_t serialExitLowpowerCriticalFunc;
|
||||
} serial_manager_lowpower_critical_CBs_t;
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
/*!
|
||||
* @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.
|
||||
*
|
||||
* This function configures the Serial Manager module with user-defined settings.
|
||||
* The user can configure the configuration structure.
|
||||
* The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE
|
||||
* allocated by the caller.
|
||||
* The Serial Manager module supports three types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc), USB
|
||||
* CDC and swo.
|
||||
* Please refer to #serial_port_type_t for serial port setting.
|
||||
* These three types can be set by using #serial_manager_config_t.
|
||||
*
|
||||
* Example below shows how to use this API to configure the Serial Manager.
|
||||
* For UART,
|
||||
* @code
|
||||
* #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
|
||||
* static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle);
|
||||
* static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
|
||||
*
|
||||
* serial_manager_config_t config;
|
||||
* serial_port_uart_config_t uartConfig;
|
||||
* config.type = kSerialPort_Uart;
|
||||
* config.ringBuffer = &s_ringBuffer[0];
|
||||
* config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
|
||||
* uartConfig.instance = 0;
|
||||
* uartConfig.clockRate = 24000000;
|
||||
* uartConfig.baudRate = 115200;
|
||||
* uartConfig.parityMode = kSerialManager_UartParityDisabled;
|
||||
* uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
|
||||
* uartConfig.enableRx = 1;
|
||||
* uartConfig.enableTx = 1;
|
||||
* uartConfig.enableRxRTS = 0;
|
||||
* uartConfig.enableTxCTS = 0;
|
||||
* config.portConfig = &uartConfig;
|
||||
* SerialManager_Init((serial_handle_t)s_serialHandle, &config);
|
||||
* @endcode
|
||||
* For USB CDC,
|
||||
* @code
|
||||
* #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
|
||||
* static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle);
|
||||
* static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
|
||||
*
|
||||
* serial_manager_config_t config;
|
||||
* serial_port_usb_cdc_config_t usbCdcConfig;
|
||||
* config.type = kSerialPort_UsbCdc;
|
||||
* config.ringBuffer = &s_ringBuffer[0];
|
||||
* config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
|
||||
* usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
|
||||
* config.portConfig = &usbCdcConfig;
|
||||
* SerialManager_Init((serial_handle_t)s_serialHandle, &config);
|
||||
* @endcode
|
||||
*
|
||||
* @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* You can define the handle in the following two ways:
|
||||
* #SERIAL_MANAGER_HANDLE_DEFINE(serialHandle);
|
||||
* or
|
||||
* uint32_t serialHandle[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
|
||||
* @param serialConfig Pointer to user-defined configuration structure.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
* @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *serialConfig);
|
||||
|
||||
/*!
|
||||
* @brief De-initializes the serial manager module instance.
|
||||
*
|
||||
* This function de-initializes the serial manager module instance. If the opened writing or
|
||||
* reading handle is not closed, the function will return kStatus_SerialManager_Busy.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.
|
||||
* @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);
|
||||
|
||||
/*!
|
||||
* @brief Opens a writing handle for the serial manager module.
|
||||
*
|
||||
* This function Opens a writing handle for the serial manager module. If the serial manager needs to
|
||||
* be used in different tasks, the task should open a dedicated write handle for itself by calling
|
||||
* #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing
|
||||
* handle at the same time, multiple writing handles need to be opened when the multiple transmission
|
||||
* is needed for a task.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* @param writeHandle The serial manager module writing handle pointer.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* You can define the handle in the following two ways:
|
||||
* #SERIAL_MANAGER_WRITE_HANDLE_DEFINE(writeHandle);
|
||||
* or
|
||||
* uint32_t writeHandle[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
* @retval kStatus_SerialManager_HandleConflict The writing handle was opened.
|
||||
* @retval kStatus_SerialManager_Success The writing handle is opened.
|
||||
*
|
||||
* Example below shows how to use this API to write data.
|
||||
* For task 1,
|
||||
* @code
|
||||
* static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle1);
|
||||
* static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n";
|
||||
* SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle1);
|
||||
* SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle1,
|
||||
* Task1_SerialManagerTxCallback,
|
||||
* s_serialWriteHandle1);
|
||||
* SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle1,
|
||||
* s_nonBlockingWelcome1,
|
||||
* sizeof(s_nonBlockingWelcome1) - 1U);
|
||||
* @endcode
|
||||
* For task 2,
|
||||
* @code
|
||||
* static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle2);
|
||||
* static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n";
|
||||
* SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle2);
|
||||
* SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle2,
|
||||
* Task2_SerialManagerTxCallback,
|
||||
* s_serialWriteHandle2);
|
||||
* SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle2,
|
||||
* s_nonBlockingWelcome2,
|
||||
* sizeof(s_nonBlockingWelcome2) - 1U);
|
||||
* @endcode
|
||||
*/
|
||||
serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);
|
||||
|
||||
/*!
|
||||
* @brief Closes a writing handle for the serial manager module.
|
||||
*
|
||||
* This function Closes a writing handle for the serial manager module.
|
||||
*
|
||||
* @param writeHandle The serial manager module writing handle pointer.
|
||||
* @retval kStatus_SerialManager_Success The writing handle is closed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);
|
||||
|
||||
/*!
|
||||
* @brief Opens a reading handle for the serial manager module.
|
||||
*
|
||||
* This function Opens a reading handle for the serial manager module. The reading handle can not be
|
||||
* opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when
|
||||
* the previous reading handle is not closed. And there can only be one buffer for receiving for the
|
||||
* reading handle at the same time.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* @param readHandle The serial manager module reading handle pointer.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* You can define the handle in the following two ways:
|
||||
* #SERIAL_MANAGER_READ_HANDLE_DEFINE(readHandle);
|
||||
* or
|
||||
* uint32_t readHandle[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
* @retval kStatus_SerialManager_Success The reading handle is opened.
|
||||
* @retval kStatus_SerialManager_Busy Previous reading handle is not closed.
|
||||
*
|
||||
* Example below shows how to use this API to read data.
|
||||
* @code
|
||||
* static SERIAL_MANAGER_READ_HANDLE_DEFINE(s_serialReadHandle);
|
||||
* SerialManager_OpenReadHandle((serial_handle_t)serialHandle, (serial_read_handle_t)s_serialReadHandle);
|
||||
* static uint8_t s_nonBlockingBuffer[64];
|
||||
* SerialManager_InstallRxCallback((serial_read_handle_t)s_serialReadHandle,
|
||||
* APP_SerialManagerRxCallback,
|
||||
* s_serialReadHandle);
|
||||
* SerialManager_ReadNonBlocking((serial_read_handle_t)s_serialReadHandle,
|
||||
* s_nonBlockingBuffer,
|
||||
* sizeof(s_nonBlockingBuffer));
|
||||
* @endcode
|
||||
*/
|
||||
serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);
|
||||
|
||||
/*!
|
||||
* @brief Closes a reading for the serial manager module.
|
||||
*
|
||||
* This function Closes a reading for the serial manager module.
|
||||
*
|
||||
* @param readHandle The serial manager module reading handle pointer.
|
||||
* @retval kStatus_SerialManager_Success The reading handle is closed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);
|
||||
|
||||
/*!
|
||||
* @brief Transmits data with the blocking mode.
|
||||
*
|
||||
* This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.
|
||||
* This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for transmission for the writing handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_WriteBlocking and the function SerialManager_WriteNonBlocking
|
||||
* cannot be used at the same time.
|
||||
* And, the function SerialManager_CancelWriting cannot be used to abort the transmission of this function.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to write.
|
||||
* @param length Length of the data to write.
|
||||
* @retval kStatus_SerialManager_Success Successfully sent all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length);
|
||||
|
||||
/*!
|
||||
* @brief Reads data with the blocking mode.
|
||||
*
|
||||
* This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.
|
||||
* This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for receiving for the reading handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_ReadBlocking and the function SerialManager_ReadNonBlocking
|
||||
* cannot be used at the same time.
|
||||
* And, the function SerialManager_CancelReading cannot be used to abort the transmission of this function.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to store the received data.
|
||||
* @param length The length of the data to be received.
|
||||
* @retval kStatus_SerialManager_Success Successfully received all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
/*!
|
||||
* @brief Transmits data with the non-blocking mode.
|
||||
*
|
||||
* This is a non-blocking function, which returns directly without waiting for all data to be sent.
|
||||
* When all data is sent, the module notifies the upper layer through a TX callback function and passes
|
||||
* the status parameter @ref kStatus_SerialManager_Success.
|
||||
* This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for transmission for the writing handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
|
||||
* cannot be used at the same time. And, the TX callback is mandatory before the function could be used.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to write.
|
||||
* @param length Length of the data to write.
|
||||
* @retval kStatus_SerialManager_Success Successfully sent all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length);
|
||||
|
||||
/*!
|
||||
* @brief Reads data with the non-blocking mode.
|
||||
*
|
||||
* This is a non-blocking function, which returns directly without waiting for all data to be received.
|
||||
* When all data is received, the module driver notifies the upper layer
|
||||
* through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.
|
||||
* This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for receiving for the reading handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
|
||||
* cannot be used at the same time. And, the RX callback is mandatory before the function could be used.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to store the received data.
|
||||
* @param length The length of the data to be received.
|
||||
* @retval kStatus_SerialManager_Success Successfully received all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length);
|
||||
|
||||
/*!
|
||||
* @brief Tries to read data.
|
||||
*
|
||||
* The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be
|
||||
* copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.
|
||||
* After the data is copied, the actual data length is passed by the parameter length.
|
||||
* And There can only one buffer for receiving for the reading handle at the same time.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to store the received data.
|
||||
* @param length The length of the data to be received.
|
||||
* @param receivedLength Length received from the ring buffer directly.
|
||||
* @retval kStatus_SerialManager_Success Successfully received all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length,
|
||||
uint32_t *receivedLength);
|
||||
|
||||
/*!
|
||||
* @brief Cancels unfinished send transmission.
|
||||
*
|
||||
* The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer
|
||||
* through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
|
||||
*
|
||||
* @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of
|
||||
* the function #SerialManager_WriteBlocking.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Get successfully abort the sending.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);
|
||||
|
||||
/*!
|
||||
* @brief Cancels unfinished receive transmission.
|
||||
*
|
||||
* The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper
|
||||
* layer
|
||||
* through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
|
||||
*
|
||||
* @note The function #SerialManager_CancelReading cannot be used to abort the transmission of
|
||||
* the function #SerialManager_ReadBlocking.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Get successfully abort the receiving.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);
|
||||
|
||||
/*!
|
||||
* @brief Installs a TX callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the TX callback and callback parameter for the serial manager module.
|
||||
* When any status of TX transmission changed, the driver will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_SerialManager_Success Successfully install the callback.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Installs a RX callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the RX callback and callback parameter for the serial manager module.
|
||||
* When any status of RX transmission changed, the driver will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_SerialManager_Success Successfully install the callback.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Check if need polling ISR.
|
||||
*
|
||||
* This function is used to check if need polling ISR.
|
||||
*
|
||||
* @retval TRUE if need polling.
|
||||
*/
|
||||
static inline bool SerialManager_needPollingIsr(void)
|
||||
{
|
||||
#if (defined(__DSC__) && defined(__CW__))
|
||||
return !(isIRQAllowed());
|
||||
#elif defined(CPSR_M_Msk)
|
||||
return (0x13 == (__get_CPSR() & CPSR_M_Msk));
|
||||
#elif defined(DAIF_I_BIT)
|
||||
return (__get_DAIF() & DAIF_I_BIT);
|
||||
#elif defined(__XCC__)
|
||||
return (xthal_get_interrupt() & xthal_get_intenable());
|
||||
#else
|
||||
return (0U != __get_IPSR());
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Prepares to enter low power consumption.
|
||||
*
|
||||
* This function is used to prepare to enter low power consumption.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Successful operation.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);
|
||||
|
||||
/*!
|
||||
* @brief Restores from low power consumption.
|
||||
*
|
||||
* This function is used to restore from low power consumption.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Successful operation.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);
|
||||
|
||||
/*!
|
||||
* @brief This function performs initialization of the callbacks structure used to disable lowpower
|
||||
* when serial manager is active.
|
||||
*
|
||||
*
|
||||
* @param pfCallback Pointer to the function structure used to allow/disable lowpower.
|
||||
*
|
||||
*/
|
||||
void SerialManager_SetLowpowerCriticalCb(const serial_manager_lowpower_critical_CBs_t *pfCallback);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/*! @} */
|
||||
#endif /* __SERIAL_MANAGER_H__ */
|
||||
@ -1,189 +0,0 @@
|
||||
/*
|
||||
* Copyright 2019-2020, 2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_PORT_INTERNAL_H__
|
||||
#define __SERIAL_PORT_INTERNAL_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
|
||||
serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);
|
||||
serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_UartIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle);
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
serial_manager_status_t Serial_UartDmaInit(serial_handle_t serialHandle, void *serialConfig);
|
||||
serial_manager_status_t Serial_UartDmaDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartDmaWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_UartDmaCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartDmaInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_UartDmaInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_UartDmaIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
serial_manager_status_t Serial_UartDmaEnterLowpower(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartDmaExitLowpower(serial_handle_t serialHandle);
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
|
||||
serial_manager_status_t Serial_RpmsgInit(serial_handle_t serialHandle, void *serialConfig);
|
||||
serial_manager_status_t Serial_RpmsgDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_RpmsgWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_RpmsgWriteBlocking(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_RpmsgRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_RpmsgCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_RpmsgInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_RpmsgInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
#endif
|
||||
serial_manager_status_t Serial_RpmsgEnterLowpower(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_RpmsgExitLowpower(serial_handle_t serialHandle);
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
|
||||
serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);
|
||||
serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
|
||||
serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);
|
||||
serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#endif
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_SwoIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
|
||||
serial_manager_status_t Serial_PortVirtualInit(serial_handle_t serialHandle, void *config);
|
||||
serial_manager_status_t Serial_PortVirtualDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_PortVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_PortVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_PortVirtualCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_PortVirtualInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_PortVirtualInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_PortVirtualIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && SERIAL_PORT_TYPE_SPI_MASTER > 0U)
|
||||
serial_manager_status_t Serial_SpiMasterInit(serial_handle_t serialHandle, void *serialConfig);
|
||||
serial_manager_status_t Serial_SpiMasterDeinit(serial_handle_t serialHandle);
|
||||
void Serial_SpiMasterTxCallback(hal_spi_master_handle_t handle, hal_spi_status_t status, void *callbackParam);
|
||||
void Serial_SpiMasterRxCallback(hal_spi_master_handle_t handle, hal_spi_status_t status, void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiMasterWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_SpiMasterRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_SpiMasterInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiMasterInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiMasterCancelWrite(serial_handle_t serialHandle);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
|
||||
serial_manager_status_t Serial_SpiSlaveInit(serial_handle_t serialHandle, void *serialConfig);
|
||||
serial_manager_status_t Serial_SpiSlaveDeinit(serial_handle_t serialHandle);
|
||||
void Serial_SpiSlaveTxCallback(hal_spi_slave_handle_t handle, hal_spi_status_t status, void *callbackParam);
|
||||
void Serial_SpiSlaveRxCallback(hal_spi_slave_handle_t handle, hal_spi_status_t status, void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiSlaveWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_SpiSlaveRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_SpiSlaveInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiSlaveInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiSlaveCancelWrite(serial_handle_t serialHandle);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
|
||||
serial_manager_status_t Serial_PortBleWuInit(serial_handle_t serialHandle, void *config);
|
||||
serial_manager_status_t Serial_PortBleWuDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_PortBleWuWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_PortBleWuRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_PortBleWuCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_PortBleWuInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_PortBleWuInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_PortBleWuIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SERIAL_PORT_INTERNAL_H__ */
|
||||
@ -1,717 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018 -2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_component_serial_manager.h"
|
||||
#include "fsl_component_serial_port_internal.h"
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) || \
|
||||
(defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
#include "fsl_adapter_uart.h"
|
||||
|
||||
#include "fsl_component_serial_port_uart.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#ifndef NDEBUG
|
||||
#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
|
||||
#undef assert
|
||||
#define assert(n)
|
||||
#else
|
||||
/* MISRA C-2012 Rule 17.2 */
|
||||
#undef assert
|
||||
#define assert(n) \
|
||||
while (!(n)) \
|
||||
{ \
|
||||
; \
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U
|
||||
typedef struct _serial_uart_send_state
|
||||
{
|
||||
uint8_t *buffer;
|
||||
uint32_t length;
|
||||
serial_manager_callback_t callback;
|
||||
void *callbackParam;
|
||||
volatile uint8_t busy;
|
||||
} serial_uart_send_state_t;
|
||||
|
||||
typedef struct _serial_uart_recv_state
|
||||
{
|
||||
serial_manager_callback_t callback;
|
||||
void *callbackParam;
|
||||
volatile uint8_t busy;
|
||||
volatile uint8_t rxEnable;
|
||||
uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH];
|
||||
} serial_uart_recv_state_t;
|
||||
|
||||
typedef struct _serial_uart_dma_recv_state
|
||||
{
|
||||
serial_manager_callback_t callback;
|
||||
void *callbackParam;
|
||||
volatile uint8_t busy;
|
||||
volatile uint8_t rxEnable;
|
||||
uint8_t readBuffer[SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH];
|
||||
} serial_uart_dma_recv_state_t;
|
||||
|
||||
typedef struct _serial_uart_block_state
|
||||
{
|
||||
UART_HANDLE_DEFINE(usartHandleBuffer);
|
||||
} serial_uart_block_state_t;
|
||||
#endif
|
||||
|
||||
typedef struct _serial_uart_state
|
||||
{
|
||||
UART_HANDLE_DEFINE(usartHandleBuffer);
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_uart_send_state_t tx;
|
||||
serial_uart_recv_state_t rx;
|
||||
#endif
|
||||
} serial_uart_state_t;
|
||||
#endif
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
typedef struct _serial_uart_dma_state
|
||||
{
|
||||
UART_HANDLE_DEFINE(usartHandleBuffer);
|
||||
UART_DMA_HANDLE_DEFINE(uartDmaHandle);
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_uart_send_state_t tx;
|
||||
serial_uart_dma_recv_state_t rx;
|
||||
#endif
|
||||
} serial_uart_dma_state_t;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
static serial_manager_status_t Serial_UartEnableReceiving(serial_uart_state_t *serialUartHandle)
|
||||
{
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
hal_uart_transfer_t transfer;
|
||||
#endif
|
||||
if (1U == serialUartHandle->rx.rxEnable)
|
||||
{
|
||||
serialUartHandle->rx.busy = 1U;
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
transfer.data = &serialUartHandle->rx.readBuffer[0];
|
||||
transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
|
||||
if (kStatus_HAL_UartSuccess !=
|
||||
HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
|
||||
#else
|
||||
if (kStatus_HAL_UartSuccess !=
|
||||
HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
&serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
|
||||
#endif
|
||||
{
|
||||
serialUartHandle->rx.busy = 0U;
|
||||
return kStatus_SerialManager_Error;
|
||||
}
|
||||
}
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
/* UART user callback */
|
||||
static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
serial_manager_callback_message_t serialMsg;
|
||||
|
||||
assert(userData);
|
||||
serialUartHandle = (serial_uart_state_t *)userData;
|
||||
|
||||
if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status)
|
||||
{
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
(void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#else
|
||||
(void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#endif
|
||||
if ((NULL != serialUartHandle->rx.callback))
|
||||
{
|
||||
serialMsg.buffer = &serialUartHandle->rx.readBuffer[0];
|
||||
serialMsg.length = sizeof(serialUartHandle->rx.readBuffer);
|
||||
serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &serialMsg,
|
||||
kStatus_SerialManager_Success);
|
||||
}
|
||||
}
|
||||
else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status)
|
||||
{
|
||||
if (0U != serialUartHandle->tx.busy)
|
||||
{
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
if ((NULL != serialUartHandle->tx.callback))
|
||||
{
|
||||
serialMsg.buffer = serialUartHandle->tx.buffer;
|
||||
serialMsg.length = serialUartHandle->tx.length;
|
||||
serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg,
|
||||
kStatus_SerialManager_Success);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_port_uart_config_t *uartConfig = (serial_port_uart_config_t *)serialConfig;
|
||||
#endif
|
||||
serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success;
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
#if 0 /* Not used below! */
|
||||
hal_uart_transfer_t transfer;
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
assert(serialConfig);
|
||||
assert(serialHandle);
|
||||
assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t));
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
serialManagerStatus = (serial_manager_status_t)HAL_UartInit(
|
||||
((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), (const hal_uart_config_t *)serialConfig);
|
||||
assert(kStatus_SerialManager_Success == serialManagerStatus);
|
||||
(void)serialManagerStatus;
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serialUartHandle->rx.rxEnable = uartConfig->enableRx;
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
|
||||
(void)HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
Serial_UartCallback, serialUartHandle);
|
||||
#else
|
||||
(void)HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), Serial_UartCallback,
|
||||
serialUartHandle);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return serialManagerStatus;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
(void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#else
|
||||
(void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#endif
|
||||
#endif
|
||||
(void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
serialUartHandle->rx.busy = 0U;
|
||||
#endif
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
|
||||
serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
hal_uart_status_t uartstatus;
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
hal_uart_transfer_t transfer;
|
||||
#endif
|
||||
|
||||
assert(serialHandle);
|
||||
assert(buffer);
|
||||
assert(length);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
if (0U != serialUartHandle->tx.busy)
|
||||
{
|
||||
return kStatus_SerialManager_Busy;
|
||||
}
|
||||
serialUartHandle->tx.busy = 1U;
|
||||
|
||||
serialUartHandle->tx.buffer = buffer;
|
||||
serialUartHandle->tx.length = length;
|
||||
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
transfer.data = buffer;
|
||||
transfer.dataSize = length;
|
||||
uartstatus =
|
||||
HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer);
|
||||
#else
|
||||
|
||||
uartstatus = HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
|
||||
#endif
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
assert(serialHandle);
|
||||
(void)buffer;
|
||||
(void)length;
|
||||
return (serial_manager_status_t)Serial_UartEnableReceiving(serialHandle);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
assert(buffer);
|
||||
assert(length);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
buffer, length);
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
assert(buffer);
|
||||
assert(length);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
return (serial_manager_status_t)HAL_UartReceiveBlocking(
|
||||
((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
serial_manager_callback_message_t serialMsg;
|
||||
uint32_t primask;
|
||||
uint8_t isBusy = 0U;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
primask = DisableGlobalIRQ();
|
||||
isBusy = serialUartHandle->tx.busy;
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
EnableGlobalIRQ(primask);
|
||||
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
(void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#else
|
||||
(void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#endif
|
||||
if (0U != isBusy)
|
||||
{
|
||||
if ((NULL != serialUartHandle->tx.callback))
|
||||
{
|
||||
serialMsg.buffer = serialUartHandle->tx.buffer;
|
||||
serialMsg.length = serialUartHandle->tx.length;
|
||||
serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg,
|
||||
kStatus_SerialManager_Canceled);
|
||||
}
|
||||
}
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
serialUartHandle->tx.callback = callback;
|
||||
serialUartHandle->tx.callbackParam = callbackParam;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
serialUartHandle->rx.callback = callback;
|
||||
serialUartHandle->rx.callbackParam = callbackParam;
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
(void)Serial_UartEnableReceiving(serialUartHandle);
|
||||
#endif
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
void Serial_UartIsrFunction(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
}
|
||||
#endif
|
||||
|
||||
serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
hal_uart_status_t uartstatus;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
uartstatus = HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
serial_manager_status_t status = kStatus_SerialManager_Success;
|
||||
hal_uart_status_t uartstatus;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
uartstatus = HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
status = Serial_UartEnableReceiving(serialUartHandle);
|
||||
#endif
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
static serial_manager_status_t Serial_UartDmaEnableReceiving(serial_uart_dma_state_t *serialUartHandle)
|
||||
{
|
||||
if (1U == serialUartHandle->rx.rxEnable)
|
||||
{
|
||||
serialUartHandle->rx.busy = 1U;
|
||||
if (kStatus_HAL_UartDmaSuccess !=
|
||||
HAL_UartDMATransferReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
&serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer),
|
||||
false))
|
||||
|
||||
{
|
||||
serialUartHandle->rx.busy = 0U;
|
||||
return kStatus_SerialManager_Error;
|
||||
}
|
||||
}
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
/* UART user callback */
|
||||
static void Serial_UartDmaCallback(hal_uart_dma_handle_t handle, hal_dma_callback_msg_t *dmaMsg, void *callbackParam)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
serial_manager_callback_message_t cb_msg;
|
||||
|
||||
assert(callbackParam);
|
||||
serialUartHandle = (serial_uart_dma_state_t *)callbackParam;
|
||||
|
||||
if (((hal_uart_dma_status_t)kStatus_HAL_UartDmaRxIdle == dmaMsg->status) ||
|
||||
(kStatus_HAL_UartDmaIdleline == dmaMsg->status))
|
||||
{
|
||||
if ((NULL != serialUartHandle->rx.callback))
|
||||
{
|
||||
cb_msg.buffer = dmaMsg->data;
|
||||
cb_msg.length = dmaMsg->dataSize;
|
||||
serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &cb_msg, kStatus_SerialManager_Success);
|
||||
}
|
||||
|
||||
if (kStatus_HAL_UartDmaSuccess ==
|
||||
HAL_UartDMATransferReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
&serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer),
|
||||
false))
|
||||
{
|
||||
serialUartHandle->rx.busy = 1U;
|
||||
}
|
||||
}
|
||||
else if (kStatus_HAL_UartDmaTxIdle == dmaMsg->status)
|
||||
{
|
||||
if (0U != serialUartHandle->tx.busy)
|
||||
{
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
if ((NULL != serialUartHandle->tx.callback))
|
||||
{
|
||||
cb_msg.buffer = dmaMsg->data;
|
||||
cb_msg.length = dmaMsg->dataSize;
|
||||
serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &cb_msg,
|
||||
kStatus_SerialManager_Success);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
serial_manager_status_t Serial_UartDmaInit(serial_handle_t serialHandle, void *serialConfig)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
serial_port_uart_dma_config_t *uartConfig = (serial_port_uart_dma_config_t *)serialConfig;
|
||||
#endif
|
||||
serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success;
|
||||
|
||||
assert(serialConfig);
|
||||
assert(serialHandle);
|
||||
|
||||
assert(SERIAL_PORT_UART_DMA_HANDLE_SIZE >= sizeof(serial_uart_dma_state_t));
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
serialManagerStatus = (serial_manager_status_t)HAL_UartInit(
|
||||
((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), (const hal_uart_config_t *)serialConfig);
|
||||
assert(kStatus_SerialManager_Success == serialManagerStatus);
|
||||
(void)serialManagerStatus;
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
|
||||
hal_uart_dma_config_t dmaConfig;
|
||||
|
||||
dmaConfig.uart_instance = uartConfig->instance;
|
||||
dmaConfig.dma_instance = uartConfig->dma_instance;
|
||||
dmaConfig.rx_channel = uartConfig->rx_channel;
|
||||
dmaConfig.tx_channel = uartConfig->tx_channel;
|
||||
dmaConfig.dma_mux_configure = uartConfig->dma_mux_configure;
|
||||
dmaConfig.dma_channel_mux_configure = uartConfig->dma_channel_mux_configure;
|
||||
|
||||
// Init uart dma
|
||||
(void)HAL_UartDMAInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
(hal_uart_dma_handle_t *)serialUartHandle->uartDmaHandle, &dmaConfig);
|
||||
|
||||
#endif
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
|
||||
serialUartHandle->rx.rxEnable = uartConfig->enableRx;
|
||||
(void)HAL_UartDMATransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
Serial_UartDmaCallback, serialUartHandle);
|
||||
|
||||
#endif
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serialManagerStatus = Serial_UartDmaEnableReceiving(serialUartHandle);
|
||||
#endif
|
||||
|
||||
return serialManagerStatus;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartDmaDeinit(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
(void)HAL_UartDMAAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
|
||||
(void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
(void)HAL_UartDMADeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
serialUartHandle->rx.busy = 0U;
|
||||
#endif
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
|
||||
serial_manager_status_t Serial_UartDmaWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
hal_uart_status_t uartstatus;
|
||||
|
||||
assert(serialHandle);
|
||||
assert(buffer);
|
||||
assert(length);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
if (0U != serialUartHandle->tx.busy)
|
||||
{
|
||||
return kStatus_SerialManager_Busy;
|
||||
}
|
||||
serialUartHandle->tx.busy = 1U;
|
||||
|
||||
serialUartHandle->tx.buffer = buffer;
|
||||
serialUartHandle->tx.length = length;
|
||||
|
||||
uartstatus = (hal_uart_status_t)HAL_UartDMATransferSend(
|
||||
((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
|
||||
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_UartDmaCancelWrite(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
serial_manager_callback_message_t serialMsg;
|
||||
uint32_t primask;
|
||||
uint8_t isBusy = 0U;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
primask = DisableGlobalIRQ();
|
||||
isBusy = serialUartHandle->tx.busy;
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
EnableGlobalIRQ(primask);
|
||||
|
||||
(void)HAL_UartDMAAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
|
||||
if (0U != isBusy)
|
||||
{
|
||||
if ((NULL != serialUartHandle->tx.callback))
|
||||
{
|
||||
serialMsg.buffer = serialUartHandle->tx.buffer;
|
||||
serialMsg.length = serialUartHandle->tx.length;
|
||||
serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg,
|
||||
kStatus_SerialManager_Canceled);
|
||||
}
|
||||
}
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartDmaInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
serialUartHandle->tx.callback = callback;
|
||||
serialUartHandle->tx.callbackParam = callbackParam;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartDmaInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
serialUartHandle->rx.callback = callback;
|
||||
serialUartHandle->rx.callbackParam = callbackParam;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
void Serial_UartDmaIsrFunction(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
}
|
||||
#endif
|
||||
|
||||
serial_manager_status_t Serial_UartDmaEnterLowpower(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
hal_uart_status_t uartstatus;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
uartstatus = HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartDmaExitLowpower(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
serial_manager_status_t status = kStatus_SerialManager_Success;
|
||||
hal_uart_status_t uartstatus;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
uartstatus = HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@ -1,106 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_PORT_UART_H__
|
||||
#define __SERIAL_PORT_UART_H__
|
||||
|
||||
#include "fsl_adapter_uart.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup serial_port_uart
|
||||
* @ingroup serialmanager
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief serial port uart handle size*/
|
||||
|
||||
#ifndef SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH
|
||||
#define SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH (64U)
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
|
||||
#define SERIAL_PORT_UART_HANDLE_SIZE (76U + HAL_UART_HANDLE_SIZE)
|
||||
#define SERIAL_PORT_UART_BLOCK_HANDLE_SIZE (HAL_UART_BLOCK_HANDLE_SIZE)
|
||||
#else
|
||||
#define SERIAL_PORT_UART_HANDLE_SIZE (HAL_UART_HANDLE_SIZE)
|
||||
#endif
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
#define SERIAL_PORT_UART_DMA_HANDLE_SIZE (76U + HAL_UART_DMA_HANDLE_SIZE + 132U)
|
||||
#endif
|
||||
|
||||
#ifndef SERIAL_USE_CONFIGURE_STRUCTURE
|
||||
#define SERIAL_USE_CONFIGURE_STRUCTURE (0U) /*!< Enable or disable the confgure structure pointer */
|
||||
#endif
|
||||
|
||||
/*! @brief serial port uart parity mode*/
|
||||
typedef enum _serial_port_uart_parity_mode
|
||||
{
|
||||
kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */
|
||||
kSerialManager_UartParityEven = 0x2U, /*!< Parity even enabled */
|
||||
kSerialManager_UartParityOdd = 0x3U, /*!< Parity odd enabled */
|
||||
} serial_port_uart_parity_mode_t;
|
||||
|
||||
/*! @brief serial port uart stop bit count*/
|
||||
typedef enum _serial_port_uart_stop_bit_count
|
||||
{
|
||||
kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */
|
||||
kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */
|
||||
} serial_port_uart_stop_bit_count_t;
|
||||
|
||||
typedef struct _serial_port_uart_config
|
||||
{
|
||||
uint32_t clockRate; /*!< clock rate */
|
||||
uint32_t baudRate; /*!< baud rate */
|
||||
serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
|
||||
serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
|
||||
|
||||
uint8_t enableRx; /*!< Enable RX */
|
||||
uint8_t enableTx; /*!< Enable TX */
|
||||
uint8_t enableRxRTS; /*!< Enable RX RTS */
|
||||
uint8_t enableTxCTS; /*!< Enable TX CTS */
|
||||
uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
|
||||
please refer to the SOC corresponding RM. */
|
||||
|
||||
#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
|
||||
uint8_t txFifoWatermark;
|
||||
uint8_t rxFifoWatermark;
|
||||
#endif
|
||||
} serial_port_uart_config_t;
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
typedef struct _serial_port_uart_dma_config
|
||||
{
|
||||
uint32_t clockRate; /*!< clock rate */
|
||||
uint32_t baudRate; /*!< baud rate */
|
||||
serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
|
||||
serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
|
||||
|
||||
uint8_t enableRx; /*!< Enable RX */
|
||||
uint8_t enableTx; /*!< Enable TX */
|
||||
uint8_t enableRxRTS; /*!< Enable RX RTS */
|
||||
uint8_t enableTxCTS; /*!< Enable TX CTS */
|
||||
uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
|
||||
please refer to the SOC corresponding RM. */
|
||||
#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
|
||||
uint8_t txFifoWatermark;
|
||||
uint8_t rxFifoWatermark;
|
||||
#endif
|
||||
uint8_t dma_instance;
|
||||
uint8_t rx_channel;
|
||||
uint8_t tx_channel;
|
||||
void *dma_mux_configure;
|
||||
void *dma_channel_mux_configure;
|
||||
|
||||
} serial_port_uart_dma_config_t;
|
||||
#endif
|
||||
/*! @} */
|
||||
#endif /* __SERIAL_PORT_UART_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,829 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018-2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __HAL_UART_ADAPTER_H__
|
||||
#define __HAL_UART_ADAPTER_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
#if defined(SDK_OS_FREE_RTOS)
|
||||
#include "FreeRTOS.h"
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @addtogroup UART_Adapter
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
#define UART_ADAPTER_NON_BLOCKING_MODE (1U)
|
||||
#else
|
||||
#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
|
||||
#define UART_ADAPTER_NON_BLOCKING_MODE (0U)
|
||||
#else
|
||||
#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
#ifndef HAL_UART_ISR_PRIORITY
|
||||
#define HAL_UART_ISR_PRIORITY (25U)
|
||||
#endif
|
||||
#else
|
||||
#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
|
||||
#ifndef HAL_UART_ISR_PRIORITY
|
||||
#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
|
||||
#endif
|
||||
#else
|
||||
/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
|
||||
* The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
|
||||
* priority is 3 (2^2 - 1). So, the default value is 3.
|
||||
*/
|
||||
#ifndef HAL_UART_ISR_PRIORITY
|
||||
#define HAL_UART_ISR_PRIORITY (3U)
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef HAL_UART_ADAPTER_LOWPOWER
|
||||
#define HAL_UART_ADAPTER_LOWPOWER (0U)
|
||||
#endif /* HAL_UART_ADAPTER_LOWPOWER */
|
||||
|
||||
/*! @brief Enable or disable uart hardware FIFO mode (1 - enable, 0 - disable) */
|
||||
#ifndef HAL_UART_ADAPTER_FIFO
|
||||
#define HAL_UART_ADAPTER_FIFO (1U)
|
||||
#endif /* HAL_UART_ADAPTER_FIFO */
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
#ifndef HAL_UART_DMA_ENABLE
|
||||
#define HAL_UART_DMA_ENABLE (1U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef HAL_UART_DMA_ENABLE
|
||||
#define HAL_UART_DMA_ENABLE (0U)
|
||||
#endif /* HAL_UART_DMA_ENABLE */
|
||||
|
||||
/*! @brief Enable or disable uart DMA adapter int mode (1 - enable, 0 - disable) */
|
||||
#ifndef HAL_UART_DMA_INIT_ENABLE
|
||||
#define HAL_UART_DMA_INIT_ENABLE (1U)
|
||||
#endif /* HAL_SPI_MASTER_DMA_INIT_ENABLE */
|
||||
|
||||
/*! @brief Definition of uart dma adapter software idleline detection timeout value in ms. */
|
||||
#ifndef HAL_UART_DMA_IDLELINE_TIMEOUT
|
||||
#define HAL_UART_DMA_IDLELINE_TIMEOUT (1U)
|
||||
#endif /* HAL_UART_DMA_IDLELINE_TIMEOUT */
|
||||
|
||||
/*! @brief Definition of uart adapter handle size. */
|
||||
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
|
||||
#define HAL_UART_HANDLE_SIZE (92U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
|
||||
#define HAL_UART_BLOCK_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
|
||||
#else
|
||||
#define HAL_UART_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
|
||||
#endif
|
||||
|
||||
/*! @brief Definition of uart dma adapter handle size. */
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
|
||||
#define HAL_UART_DMA_HANDLE_SIZE (124U + HAL_UART_ADAPTER_LOWPOWER * 36U)
|
||||
#elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
|
||||
#define HAL_UART_DMA_HANDLE_SIZE (140U + HAL_UART_ADAPTER_LOWPOWER * 36U)
|
||||
#else
|
||||
#error This SOC does not have DMA or EDMA available!
|
||||
#endif
|
||||
#endif /* HAL_UART_DMA_ENABLE */
|
||||
|
||||
/*!
|
||||
* @brief Defines the uart handle
|
||||
*
|
||||
* This macro is used to define a 4 byte aligned uart handle.
|
||||
* Then use "(hal_uart_handle_t)name" to get the uart handle.
|
||||
*
|
||||
* The macro should be global and could be optional. You could also define uart handle by yourself.
|
||||
*
|
||||
* This is an example,
|
||||
* @code
|
||||
* UART_HANDLE_DEFINE(uartHandle);
|
||||
* @endcode
|
||||
*
|
||||
* @param name The name string of the uart handle.
|
||||
*/
|
||||
#define UART_HANDLE_DEFINE(name) uint32_t name[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
#define UART_DMA_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
#endif
|
||||
|
||||
/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */
|
||||
#ifndef HAL_UART_TRANSFER_MODE
|
||||
#define HAL_UART_TRANSFER_MODE (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief The handle of uart adapter. */
|
||||
typedef void *hal_uart_handle_t;
|
||||
|
||||
/*! @brief The handle of uart dma adapter. */
|
||||
typedef void *hal_uart_dma_handle_t;
|
||||
|
||||
/*! @brief UART status */
|
||||
typedef enum _hal_uart_status
|
||||
{
|
||||
kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */
|
||||
kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */
|
||||
kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */
|
||||
kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */
|
||||
kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */
|
||||
kStatus_HAL_UartBaudrateNotSupport =
|
||||
MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */
|
||||
kStatus_HAL_UartProtocolError = MAKE_STATUS(
|
||||
kStatusGroup_HAL_UART,
|
||||
6), /*!< Error occurs for Noise, Framing, Parity, etc.
|
||||
For transactional transfer, The up layer needs to abort the transfer and then starts again */
|
||||
kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */
|
||||
} hal_uart_status_t;
|
||||
|
||||
/*! @brief UART parity mode. */
|
||||
typedef enum _hal_uart_parity_mode
|
||||
{
|
||||
kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */
|
||||
kHAL_UartParityEven = 0x2U, /*!< Parity even enabled */
|
||||
kHAL_UartParityOdd = 0x3U, /*!< Parity odd enabled */
|
||||
} hal_uart_parity_mode_t;
|
||||
|
||||
/*! @brief UART stop bit count. */
|
||||
typedef enum _hal_uart_stop_bit_count
|
||||
{
|
||||
kHAL_UartOneStopBit = 0U, /*!< One stop bit */
|
||||
kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */
|
||||
} hal_uart_stop_bit_count_t;
|
||||
|
||||
/*! @brief UART configuration structure. */
|
||||
typedef struct _hal_uart_config
|
||||
{
|
||||
uint32_t srcClock_Hz; /*!< Source clock */
|
||||
uint32_t baudRate_Bps; /*!< Baud rate */
|
||||
hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
|
||||
hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
|
||||
uint8_t enableRx; /*!< Enable RX */
|
||||
uint8_t enableTx; /*!< Enable TX */
|
||||
uint8_t enableRxRTS; /*!< Enable RX RTS */
|
||||
uint8_t enableTxCTS; /*!< Enable TX CTS */
|
||||
uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
|
||||
SOC corresponding RM.
|
||||
Invalid instance value will cause initialization failure. */
|
||||
#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
|
||||
uint8_t txFifoWatermark;
|
||||
uint8_t rxFifoWatermark;
|
||||
#endif
|
||||
} hal_uart_config_t;
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
/*! @brief UART DMA status */
|
||||
typedef enum _hal_uart_dma_status
|
||||
{
|
||||
kStatus_HAL_UartDmaSuccess = 0U,
|
||||
kStatus_HAL_UartDmaRxIdle = (1U << 1U),
|
||||
kStatus_HAL_UartDmaRxBusy = (1U << 2U),
|
||||
kStatus_HAL_UartDmaTxIdle = (1U << 3U),
|
||||
kStatus_HAL_UartDmaTxBusy = (1U << 4U),
|
||||
kStatus_HAL_UartDmaIdleline = (1U << 5U),
|
||||
kStatus_HAL_UartDmaError = (1U << 6U),
|
||||
} hal_uart_dma_status_t;
|
||||
|
||||
typedef struct _dma_mux_configure_t
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint8_t dma_mux_instance;
|
||||
uint32_t rx_request;
|
||||
uint32_t tx_request;
|
||||
} dma_dmamux_configure;
|
||||
};
|
||||
} dma_mux_configure_t;
|
||||
typedef struct _dma_channel_mux_configure_t
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t dma_rx_channel_mux;
|
||||
uint32_t dma_tx_channel_mux;
|
||||
} dma_dmamux_configure;
|
||||
};
|
||||
} dma_channel_mux_configure_t;
|
||||
|
||||
typedef struct _hal_uart_dma_config_t
|
||||
{
|
||||
uint8_t uart_instance;
|
||||
uint8_t dma_instance;
|
||||
uint8_t rx_channel;
|
||||
uint8_t tx_channel;
|
||||
void *dma_mux_configure;
|
||||
void *dma_channel_mux_configure;
|
||||
} hal_uart_dma_config_t;
|
||||
#endif /* HAL_UART_DMA_ENABLE */
|
||||
|
||||
/*! @brief UART transfer callback function. */
|
||||
typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
typedef struct _dma_callback_msg
|
||||
{
|
||||
hal_uart_dma_status_t status;
|
||||
uint8_t *data;
|
||||
uint32_t dataSize;
|
||||
} hal_dma_callback_msg_t;
|
||||
|
||||
/*! @brief UART transfer callback function. */
|
||||
typedef void (*hal_uart_dma_transfer_callback_t)(hal_uart_dma_handle_t handle,
|
||||
hal_dma_callback_msg_t *msg,
|
||||
void *callbackParam);
|
||||
#endif /* HAL_UART_DMA_ENABLE */
|
||||
|
||||
/*! @brief UART transfer structure. */
|
||||
typedef struct _hal_uart_transfer
|
||||
{
|
||||
uint8_t *data; /*!< The buffer of data to be transfer.*/
|
||||
size_t dataSize; /*!< The byte count to be transfer. */
|
||||
} hal_uart_transfer_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes a UART instance with the UART handle and the user configuration structure.
|
||||
*
|
||||
* This function configures the UART module with user-defined settings. The user can configure the configuration
|
||||
* structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by
|
||||
* the caller. Example below shows how to use this API to configure the UART.
|
||||
* @code
|
||||
* UART_HANDLE_DEFINE(g_UartHandle);
|
||||
* hal_uart_config_t config;
|
||||
* config.srcClock_Hz = 48000000;
|
||||
* config.baudRate_Bps = 115200U;
|
||||
* config.parityMode = kHAL_UartParityDisabled;
|
||||
* config.stopBitCount = kHAL_UartOneStopBit;
|
||||
* config.enableRx = 1;
|
||||
* config.enableTx = 1;
|
||||
* config.enableRxRTS = 0;
|
||||
* config.enableTxCTS = 0;
|
||||
* config.instance = 0;
|
||||
* HAL_UartInit((hal_uart_handle_t)g_UartHandle, &config);
|
||||
* @endcode
|
||||
*
|
||||
* @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* You can define the handle in the following two ways:
|
||||
* #UART_HANDLE_DEFINE(handle);
|
||||
* or
|
||||
* uint32_t handle[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
|
||||
* @param uart_config Pointer to user-defined configuration structure.
|
||||
* @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.
|
||||
* @retval kStatus_HAL_UartSuccess UART initialization succeed
|
||||
*/
|
||||
hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *uart_config);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes a UART instance.
|
||||
*
|
||||
* This function waits for TX complete, disables TX and RX, and disables the UART clock.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_HAL_UartSuccess UART de-initialization succeed
|
||||
*/
|
||||
hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Blocking bus Operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Reads RX data register using a blocking method.
|
||||
*
|
||||
* This function polls the RX register, waits for the RX register to be full or for RX FIFO to
|
||||
* have data, and reads data from the RX register.
|
||||
*
|
||||
* @note The function #HAL_UartReceiveBlocking and the function HAL_UartTransferReceiveNonBlocking
|
||||
* cannot be used at the same time.
|
||||
* And, the function HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data Start address of the buffer to store the received data.
|
||||
* @param length Size of the buffer.
|
||||
* @retval kStatus_HAL_UartError An error occurred while receiving data.
|
||||
* @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully received all data.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
|
||||
|
||||
/*!
|
||||
* @brief Writes to the TX register using a blocking method.
|
||||
*
|
||||
* This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
|
||||
* to have room and writes data to the TX buffer.
|
||||
*
|
||||
* @note The function #HAL_UartSendBlocking and the function HAL_UartTransferSendNonBlocking
|
||||
* cannot be used at the same time.
|
||||
* And, the function HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data Start address of the data to write.
|
||||
* @param length Size of the data to write.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully sent all data.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
|
||||
/*!
|
||||
* @name Transactional
|
||||
* @note The transactional API and the functional API cannot be used at the same time. The macro
|
||||
* #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
|
||||
* functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Installs a callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the callback and callback parameter for UART module.
|
||||
* When any status of the UART changed, the driver will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully install the callback.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
|
||||
hal_uart_transfer_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Receives a buffer of data using an interrupt method.
|
||||
*
|
||||
* This function receives data using an interrupt method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be received.
|
||||
* The receive request is saved by the UART driver.
|
||||
* When the new data arrives, the receive request is serviced first.
|
||||
* When all data is received, the UART driver notifies the upper layer
|
||||
* through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle.
|
||||
*
|
||||
* @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
|
||||
* cannot be used at the same time.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param transfer UART transfer structure, see #hal_uart_transfer_t.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
|
||||
* @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
|
||||
|
||||
/*!
|
||||
* @brief Transmits a buffer of data using the interrupt method.
|
||||
*
|
||||
* This function sends data using an interrupt method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be written to the TX register. When
|
||||
* all data is written to the TX register in the ISR, the UART driver calls the callback
|
||||
* function and passes the @ref kStatus_HAL_UartTxIdle as status parameter.
|
||||
*
|
||||
* @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
|
||||
* cannot be used at the same time.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param transfer UART transfer structure. See #hal_uart_transfer_t.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
|
||||
* @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes that have been received.
|
||||
*
|
||||
* This function gets the number of bytes that have been received.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param count Receive bytes count.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes written to the UART TX register.
|
||||
*
|
||||
* This function gets the number of bytes written to the UART TX
|
||||
* register by using the interrupt method.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param count Send bytes count.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data receiving.
|
||||
*
|
||||
* This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
|
||||
* how many bytes are not received yet.
|
||||
*
|
||||
* @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of
|
||||
* the function #HAL_UartReceiveBlocking.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_Success Get successfully abort the receiving.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data sending.
|
||||
*
|
||||
* This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
|
||||
* how many bytes are not sent out.
|
||||
*
|
||||
* @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of
|
||||
* the function #HAL_UartSendBlocking.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_Success Get successfully abort the sending.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#else
|
||||
|
||||
/*!
|
||||
* @name Functional API with non-blocking mode.
|
||||
* @note The functional API and the transactional API cannot be used at the same time. The macro
|
||||
* #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
|
||||
* functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Installs a callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the callback and callback parameter for UART module.
|
||||
* When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully install the callback.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
|
||||
hal_uart_transfer_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Receives a buffer of data using an interrupt method.
|
||||
*
|
||||
* This function receives data using an interrupt method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be received.
|
||||
* The receive request is saved by the UART adapter.
|
||||
* When the new data arrives, the receive request is serviced first.
|
||||
* When all data is received, the UART adapter notifies the upper layer
|
||||
* through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle.
|
||||
*
|
||||
* @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking
|
||||
* cannot be used at the same time.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data Start address of the data to write.
|
||||
* @param length Size of the data to write.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
|
||||
* @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
|
||||
|
||||
/*!
|
||||
* @brief Transmits a buffer of data using the interrupt method.
|
||||
*
|
||||
* This function sends data using an interrupt method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be written to the TX register. When
|
||||
* all data is written to the TX register in the ISR, the UART driver calls the callback
|
||||
* function and passes the @ref kStatus_HAL_UartTxIdle as status parameter.
|
||||
*
|
||||
* @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking
|
||||
* cannot be used at the same time.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data Start address of the data to write.
|
||||
* @param length Size of the data to write.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
|
||||
* @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes that have been received.
|
||||
*
|
||||
* This function gets the number of bytes that have been received.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param reCount Receive bytes count.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes written to the UART TX register.
|
||||
*
|
||||
* This function gets the number of bytes written to the UART TX
|
||||
* register by using the interrupt method.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param seCount Send bytes count.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data receiving.
|
||||
*
|
||||
* This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
|
||||
* how many bytes are not received yet.
|
||||
*
|
||||
* @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of
|
||||
* the function #HAL_UartReceiveBlocking.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_Success Get successfully abort the receiving.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data sending.
|
||||
*
|
||||
* This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
|
||||
* how many bytes are not sent out.
|
||||
*
|
||||
* @note The function #HAL_UartAbortSend cannot be used to abort the transmission of
|
||||
* the function #HAL_UartSendBlocking.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_Success Get successfully abort the sending.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
|
||||
/*!
|
||||
* @brief Initializes a UART dma instance with the UART dma handle and the user configuration structure.
|
||||
*
|
||||
* This function configures the UART dma module with user-defined settings. The user can configure the configuration
|
||||
* structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated
|
||||
* by the caller. Example below shows how to use this API to configure the UART.
|
||||
* @code
|
||||
*
|
||||
* Init TimerManager, only used in UART without Idleline interrupt
|
||||
* timer_config_t timerConfig;
|
||||
* timerConfig.srcClock_Hz = 16000000;
|
||||
* timerConfig.instance = 0;
|
||||
* TM_Init(&timerConfig);
|
||||
*
|
||||
* Init the DMA module
|
||||
* DMA_Init(DMA0);
|
||||
*
|
||||
* Define a uart dma handle
|
||||
* UART_HANDLE_DEFINE(g_uartHandle);
|
||||
* UART_DMA_HANDLE_DEFINE(g_UartDmaHandle);
|
||||
*
|
||||
* Configure uart settings
|
||||
* hal_uart_config_t uartConfig;
|
||||
* uartConfig.srcClock_Hz = 48000000;
|
||||
* uartConfig.baudRate_Bps = 115200;
|
||||
* uartConfig.parityMode = kHAL_UartParityDisabled;
|
||||
* uartConfig.stopBitCount = kHAL_UartOneStopBit;
|
||||
* uartConfig.enableRx = 1;
|
||||
* uartConfig.enableTx = 1;
|
||||
* uartConfig.enableRxRTS = 0;
|
||||
* uartConfig.enableTxCTS = 0;
|
||||
* uartConfig.instance = 0;
|
||||
*
|
||||
* Init uart
|
||||
* HAL_UartInit((hal_uart_handle_t *)g_uartHandle, &uartConfig);
|
||||
*
|
||||
* Configure uart dma settings
|
||||
* hal_uart_dma_config_t dmaConfig;
|
||||
* dmaConfig.uart_instance = 0;
|
||||
* dmaConfig.dma_instance = 0;
|
||||
* dmaConfig.rx_channel = 0;
|
||||
* dmaConfig.tx_channel = 1;
|
||||
*
|
||||
* Init uart dma
|
||||
* HAL_UartDMAInit((hal_uart_handle_t *)g_uartHandle, (hal_uart_dma_handle_t *)g_uartDmaHandle, &dmaConfig);
|
||||
* @endcode
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param dmaHandle Pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated by the caller.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* You can define the handle in the following two ways:
|
||||
* #UART_DMA_HANDLE_DEFINE(handle);
|
||||
* or
|
||||
* uint32_t handle[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
|
||||
* @param dmaConfig Pointer to user-defined configuration structure.
|
||||
* @retval kStatus_HAL_UartDmaError UART dma initialization failed.
|
||||
* @retval kStatus_HAL_UartDmaSuccess UART dma initialization succeed.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle,
|
||||
hal_uart_dma_handle_t dmaHandle,
|
||||
hal_uart_dma_config_t *dmaConfig);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes a UART DMA instance.
|
||||
*
|
||||
* This function will abort uart dma receive/send transfer and deinitialize UART.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_HAL_UartDmaSuccess UART DMA de-initialization succeed
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle);
|
||||
|
||||
/*!
|
||||
* @brief Installs a callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the callback and callback parameter for UART DMA module.
|
||||
* When any status of the UART DMA changed, the driver will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Successfully install the callback.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle,
|
||||
hal_uart_dma_transfer_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Receives a buffer of data using an dma method.
|
||||
*
|
||||
* This function receives data using an dma method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be received.
|
||||
* The receive request is saved by the UART DMA driver.
|
||||
* When all data is received, the UART DMA adapter notifies the upper layer
|
||||
* through a callback function and passes the status parameter @ref kStatus_HAL_UartDmaRxIdle.
|
||||
*
|
||||
* When an idleline is detected, the UART DMA adapter notifies the upper layer through a callback function,
|
||||
* and passes the status parameter @ref kStatus_HAL_UartDmaIdleline. For the UARTs without hardware idleline
|
||||
* interrupt(like usart), it will use a software idleline detection method with the help of TimerManager.
|
||||
*
|
||||
* When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data data Start address of the buffer to store the received data.
|
||||
* @param length Size of the buffer.
|
||||
* @param receiveAll Idleline interrupt will not end transfer process if set true.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Successfully start the data receive.
|
||||
* @retval kStatus_HAL_UartDmaRxBusy Previous receive request is not finished.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle,
|
||||
uint8_t *data,
|
||||
size_t length,
|
||||
bool receiveAll);
|
||||
|
||||
/*!
|
||||
* @brief Transmits a buffer of data using an dma method.
|
||||
*
|
||||
* This function sends data using an dma method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be written to the TX register. When
|
||||
* all data is written to the TX register by DMA, the UART DMA driver calls the callback
|
||||
* function and passes the @ref kStatus_HAL_UartDmaTxIdle as status parameter.
|
||||
*
|
||||
* When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data data Start address of the data to write.
|
||||
* @param length Size of the data to write.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Successfully start the data transmission.
|
||||
* @retval kStatus_HAL_UartDmaTxBusy Previous send request is not finished.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes that have been received.
|
||||
*
|
||||
* This function gets the number of bytes that have been received.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param reCount Receive bytes count.
|
||||
* @retval kStatus_HAL_UartDmaError An error occurred.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p reCount.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes written to the UART TX register.
|
||||
*
|
||||
* This function gets the number of bytes written to the UART TX
|
||||
* register by using the DMA method.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param seCount Send bytes count.
|
||||
* @retval kStatus_HAL_UartDmaError An error occurred.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p seCount.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the DMA-driven data receiving.
|
||||
*
|
||||
* This function aborts the DMA-driven data receiving.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Get successfully abort the receiving.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the DMA-driven data sending.
|
||||
*
|
||||
* This function aborts the DMA-driven data sending.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_Success Get successfully abort the sending.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle);
|
||||
#endif /* HAL_UART_DMA_ENABLE */
|
||||
|
||||
/*!
|
||||
* @brief Prepares to enter low power consumption.
|
||||
*
|
||||
* This function is used to prepare to enter low power consumption.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_HAL_UartSuccess Successful operation.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle);
|
||||
|
||||
/*!
|
||||
* @brief Restores from low power consumption.
|
||||
*
|
||||
* This function is used to restore from low power consumption.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_HAL_UartSuccess Successful operation.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle);
|
||||
|
||||
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
|
||||
/*!
|
||||
* @brief UART IRQ handle function.
|
||||
*
|
||||
* This function handles the UART transmit and receive IRQ request.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
*/
|
||||
void HAL_UartIsrFunction(hal_uart_handle_t handle);
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/*! @}*/
|
||||
#endif /* __HAL_UART_ADAPTER_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,42 +0,0 @@
|
||||
/*
|
||||
* Copyright 2014-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2023 NXP
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __FSL_DEVICE_REGISTERS_H__
|
||||
#define __FSL_DEVICE_REGISTERS_H__
|
||||
|
||||
/*
|
||||
* Include the cpu specific register header files.
|
||||
*
|
||||
* The CPU macro should be declared in the project or makefile.
|
||||
*/
|
||||
#if (defined(CPU_MCXN947VDF_cm33_core0) || defined(CPU_MCXN947VNL_cm33_core0))
|
||||
|
||||
#define MCXN947_cm33_core0_SERIES
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "MCXN947_cm33_core0.h"
|
||||
/* CPU specific feature definitions */
|
||||
#include "MCXN947_cm33_core0_features.h"
|
||||
|
||||
#elif (defined(CPU_MCXN947VDF_cm33_core1) || defined(CPU_MCXN947VNL_cm33_core1))
|
||||
|
||||
#define MCXN947_cm33_core1_SERIES
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "MCXN947_cm33_core1.h"
|
||||
/* CPU specific feature definitions */
|
||||
#include "MCXN947_cm33_core1_features.h"
|
||||
|
||||
#else
|
||||
#error "No valid CPU defined!"
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_DEVICE_REGISTERS_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
@ -1,130 +0,0 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MCXN947VDF_cm33_core0
|
||||
** MCXN947VNL_cm33_core0
|
||||
**
|
||||
** Compilers: GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** Keil ARM C/C++ Compiler
|
||||
** MCUXpresso Compiler
|
||||
**
|
||||
** Reference manual: MCXNx4x Reference Manual
|
||||
** Version: rev. 2.0, 2023-02-01
|
||||
** Build: b231219
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2023 NXP
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2022-10-01)
|
||||
** Initial version
|
||||
** - rev. 2.0 (2023-02-01)
|
||||
** Initial version based on Rev. 2 Draft B
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MCXN947_cm33_core0
|
||||
* @version 2.0
|
||||
* @date 2023-02-01
|
||||
* @brief Device specific configuration file for MCXN947_cm33_core0
|
||||
* (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
__attribute__ ((weak)) void SystemInit (void) {
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
||||
|
||||
|
||||
SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
|
||||
|
||||
SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */
|
||||
|
||||
SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */
|
||||
|
||||
#if defined(__MCUXPRESSO)
|
||||
extern void(*const g_pfnVectors[]) (void);
|
||||
SCB->VTOR = (uint32_t) &g_pfnVectors;
|
||||
#else
|
||||
extern void *__Vectors;
|
||||
SCB->VTOR = (uint32_t) &__Vectors;
|
||||
#endif
|
||||
/* enable the flash cache LPCAC */
|
||||
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
|
||||
|
||||
/* Disable aGDET trigger the CHIP_RESET */
|
||||
ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
|
||||
ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
|
||||
/* Disable aGDET interrupt and reset */
|
||||
SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK;
|
||||
SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK;
|
||||
SPC0->GLITCH_DETECT_SC = 0x3C;
|
||||
SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK;
|
||||
|
||||
/* Disable dGDET trigger the CHIP_RESET */
|
||||
ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
|
||||
ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
|
||||
GDET0->GDET_ENABLE1 = 0;
|
||||
GDET1->GDET_ENABLE1 = 0;
|
||||
|
||||
SystemInitHook();
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemCoreClockUpdate()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemCoreClockUpdate (void) {
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInitHook()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
__attribute__ ((weak)) void SystemInitHook (void) {
|
||||
/* Void implementation of the weak function. */
|
||||
}
|
||||
@ -1,108 +0,0 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MCXN947VDF_cm33_core0
|
||||
** MCXN947VNL_cm33_core0
|
||||
**
|
||||
** Compilers: GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** Keil ARM C/C++ Compiler
|
||||
** MCUXpresso Compiler
|
||||
**
|
||||
** Reference manual: MCXNx4x Reference Manual
|
||||
** Version: rev. 2.0, 2023-02-01
|
||||
** Build: b231219
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2023 NXP
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2022-10-01)
|
||||
** Initial version
|
||||
** - rev. 2.0 (2023-02-01)
|
||||
** Initial version based on Rev. 2 Draft B
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MCXN947_cm33_core0
|
||||
* @version 2.0
|
||||
* @date 2023-02-01
|
||||
* @brief Device specific configuration file for MCXN947_cm33_core0 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_MCXN947_cm33_core0_H_
|
||||
#define _SYSTEM_MCXN947_cm33_core0_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
|
||||
#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */
|
||||
#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
/**
|
||||
* @brief SystemInit function hook.
|
||||
*
|
||||
* This weak function allows to call specific initialization code during the
|
||||
* SystemInit() execution.This can be used when an application specific code needs
|
||||
* to be called as close to the reset entry as possible (for example the Multicore
|
||||
* Manager MCMGR_EarlyInit() function call).
|
||||
* NOTE: No global r/w variables can be used in this hook function because the
|
||||
* initialization of these variables happens after this function.
|
||||
*/
|
||||
void SystemInitHook (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_MCXN947_cm33_core0_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,85 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
#define SDK_MEM_MAGIC_NUMBER 12345U
|
||||
|
||||
typedef struct _mem_align_control_block
|
||||
{
|
||||
uint16_t identifier; /*!< Identifier for the memory control block. */
|
||||
uint16_t offset; /*!< offset from aligned address to real address */
|
||||
} mem_align_cb_t;
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.common"
|
||||
#endif
|
||||
|
||||
#if !((defined(__DSC__) && defined(__CW__)))
|
||||
void *SDK_Malloc(size_t size, size_t alignbytes)
|
||||
{
|
||||
mem_align_cb_t *p_cb = NULL;
|
||||
uint32_t alignedsize;
|
||||
|
||||
/* Check overflow. */
|
||||
alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
|
||||
if (alignedsize < size)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
|
||||
|
||||
union
|
||||
{
|
||||
void *pointer_value;
|
||||
uintptr_t unsigned_value;
|
||||
} p_align_addr, p_addr;
|
||||
|
||||
p_addr.pointer_value = malloc((size_t)alignedsize);
|
||||
|
||||
if (p_addr.pointer_value == NULL)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
|
||||
|
||||
p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
|
||||
p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
|
||||
p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
|
||||
|
||||
return p_align_addr.pointer_value;
|
||||
}
|
||||
|
||||
void SDK_Free(void *ptr)
|
||||
{
|
||||
union
|
||||
{
|
||||
void *pointer_value;
|
||||
uintptr_t unsigned_value;
|
||||
} p_free;
|
||||
p_free.pointer_value = ptr;
|
||||
mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
|
||||
|
||||
if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
|
||||
|
||||
free(p_free.pointer_value);
|
||||
}
|
||||
#endif
|
||||
@ -1,321 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FSL_COMMON_H_
|
||||
#define FSL_COMMON_H_
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
|
||||
#include <stddef.h>
|
||||
#endif
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup ksdk_common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Configurations
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Macro to use the default weak IRQ handler in drivers. */
|
||||
#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
|
||||
#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Construct a status code value from a group and code number. */
|
||||
#define MAKE_STATUS(group, code) ((((group)*100L) + (code)))
|
||||
|
||||
/*! @brief Construct the version number for drivers.
|
||||
*
|
||||
* The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M)
|
||||
* and 16-bit platforms(such as DSC).
|
||||
*
|
||||
* @verbatim
|
||||
|
||||
| Unused || Major Version || Minor Version || Bug Fix |
|
||||
31 25 24 17 16 9 8 0
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix))
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief common driver version. */
|
||||
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
|
||||
/*@}*/
|
||||
|
||||
/* Debug console type definition. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */
|
||||
|
||||
/*! @brief Status group numbers. */
|
||||
enum _status_groups
|
||||
{
|
||||
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
|
||||
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
|
||||
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
|
||||
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
|
||||
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
|
||||
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
|
||||
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
|
||||
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
|
||||
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
|
||||
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
|
||||
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
|
||||
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
|
||||
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
|
||||
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
|
||||
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
|
||||
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
|
||||
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
|
||||
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
|
||||
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
|
||||
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
|
||||
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
|
||||
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
|
||||
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
|
||||
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
|
||||
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
|
||||
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
|
||||
kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
|
||||
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
|
||||
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
|
||||
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
|
||||
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
|
||||
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
|
||||
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
|
||||
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
|
||||
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
|
||||
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
|
||||
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
|
||||
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
|
||||
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
|
||||
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
|
||||
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
|
||||
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
|
||||
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
|
||||
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
|
||||
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
|
||||
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
|
||||
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
|
||||
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
|
||||
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
|
||||
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
|
||||
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
|
||||
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
|
||||
kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
|
||||
kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
|
||||
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
|
||||
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
|
||||
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
|
||||
kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
|
||||
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
|
||||
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
|
||||
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
|
||||
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
|
||||
kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
|
||||
kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
|
||||
kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */
|
||||
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
|
||||
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
|
||||
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
|
||||
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
|
||||
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
|
||||
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
|
||||
kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/
|
||||
kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */
|
||||
kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */
|
||||
kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */
|
||||
kStatusGroup_VBAT = 107, /*!< Group number for VBAT status codes */
|
||||
|
||||
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
|
||||
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
|
||||
kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
|
||||
kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
|
||||
kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
|
||||
kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
|
||||
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
|
||||
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
|
||||
kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */
|
||||
kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */
|
||||
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
|
||||
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
|
||||
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
|
||||
kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
|
||||
kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
|
||||
kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
|
||||
kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
|
||||
kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
|
||||
kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
|
||||
kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
|
||||
kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
|
||||
kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */
|
||||
kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
|
||||
kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */
|
||||
kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */
|
||||
kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */
|
||||
kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */
|
||||
kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */
|
||||
kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */
|
||||
kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */
|
||||
kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */
|
||||
kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */
|
||||
kStatusGroup_ELEMU = 157, /*!< Group number for ELEMU status codes. */
|
||||
kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */
|
||||
kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */
|
||||
kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */
|
||||
kStatusGroup_ELS_PKC = 161, /*!< Group number for ELS PKC status codes. */
|
||||
kStatusGroup_CSS_PKC = 162, /*!< Group number for CSS PKC status codes. */
|
||||
kStatusGroup_HOSTIF = 163, /*!< Group number for HOSTIF status codes. */
|
||||
kStatusGroup_CLIF = 164, /*!< Group number for CLIF status codes. */
|
||||
kStatusGroup_BMA = 165, /*!< Group number for BMA status codes. */
|
||||
kStatusGroup_NETC = 166, /*!< Group number for NETC status codes. */
|
||||
kStatusGroup_ELE = 167, /*!< Group number for ELE status codes. */
|
||||
};
|
||||
|
||||
/*! \public
|
||||
* @brief Generic status return codes.
|
||||
*/
|
||||
enum
|
||||
{
|
||||
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */
|
||||
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */
|
||||
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */
|
||||
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */
|
||||
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */
|
||||
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */
|
||||
kStatus_NoTransferInProgress =
|
||||
MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */
|
||||
kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */
|
||||
kStatus_NoData =
|
||||
MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */
|
||||
};
|
||||
|
||||
/*! @brief Type used for all status and error return values. */
|
||||
typedef int32_t status_t;
|
||||
|
||||
/*!
|
||||
* @name Min/max macros
|
||||
* @{
|
||||
*/
|
||||
#if !defined(MIN)
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#if !defined(MAX)
|
||||
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @brief Computes the number of elements in an array. */
|
||||
#if !defined(ARRAY_SIZE)
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
#endif
|
||||
|
||||
/*! @name UINT16_MAX/UINT32_MAX value */
|
||||
/* @{ */
|
||||
#if !defined(UINT16_MAX)
|
||||
#define UINT16_MAX ((uint16_t)-1)
|
||||
#endif
|
||||
|
||||
#if !defined(UINT32_MAX)
|
||||
#define UINT32_MAX ((uint32_t)-1)
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @name Suppress fallthrough warning macro */
|
||||
/* For switch case code block, if case section ends without "break;" statement, there wil be
|
||||
fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
|
||||
To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
|
||||
case section which misses "break;"statement.
|
||||
*/
|
||||
/* @{ */
|
||||
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
|
||||
#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
|
||||
#else
|
||||
#define SUPPRESS_FALL_THROUGH_WARNING()
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !((defined(__DSC__) && defined(__CW__)))
|
||||
/*!
|
||||
* @brief Allocate memory with given alignment and aligned size.
|
||||
*
|
||||
* This is provided to support the dynamically allocated memory
|
||||
* used in cache-able region.
|
||||
* @param size The length required to malloc.
|
||||
* @param alignbytes The alignment size.
|
||||
* @retval The allocated memory.
|
||||
*/
|
||||
void *SDK_Malloc(size_t size, size_t alignbytes);
|
||||
|
||||
/*!
|
||||
* @brief Free memory.
|
||||
*
|
||||
* @param ptr The memory to be release.
|
||||
*/
|
||||
void SDK_Free(void *ptr);
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Delay at least for some time.
|
||||
* Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
|
||||
* if precise delay count was needed, please implement a new delay function with hardware timer.
|
||||
*
|
||||
* @param delayTime_us Delay time in unit of microsecond.
|
||||
* @param coreClock_Hz Core clock frequency with Hz.
|
||||
*/
|
||||
void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#if (defined(__DSC__) && defined(__CW__))
|
||||
#include "fsl_common_dsc.h"
|
||||
#elif defined(__XTENSA__)
|
||||
#include "fsl_common_dsp.h"
|
||||
#else
|
||||
#include "fsl_common_arm.h"
|
||||
#endif
|
||||
|
||||
#endif /* FSL_COMMON_H_ */
|
||||
@ -1,249 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.common_arm"
|
||||
#endif
|
||||
|
||||
#ifndef __GIC_PRIO_BITS
|
||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
|
||||
{
|
||||
#ifdef __VECTOR_TABLE
|
||||
#undef __VECTOR_TABLE
|
||||
#endif
|
||||
|
||||
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
extern uint32_t Image$$VECTOR_ROM$$Base[];
|
||||
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||
extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[];
|
||||
|
||||
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
|
||||
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base))
|
||||
#elif defined(__ICCARM__)
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
|
||||
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
|
||||
#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
|
||||
uint32_t n;
|
||||
uint32_t ret;
|
||||
uint32_t irqMaskValue;
|
||||
|
||||
irqMaskValue = DisableGlobalIRQ();
|
||||
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
|
||||
{
|
||||
/* Copy the vector table from ROM to RAM */
|
||||
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
|
||||
{
|
||||
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
|
||||
}
|
||||
/* Point the VTOR to the position of vector table */
|
||||
SCB->VTOR = (uint32_t)__VECTOR_RAM;
|
||||
}
|
||||
|
||||
ret = __VECTOR_RAM[(int32_t)irq + 16];
|
||||
/* make sure the __VECTOR_RAM is noncachable */
|
||||
__VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
|
||||
|
||||
EnableGlobalIRQ(irqMaskValue);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||
#endif /* __GIC_PRIO_BITS. */
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
|
||||
/*
|
||||
* When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
|
||||
* powerlib should be used instead of these functions.
|
||||
*/
|
||||
#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
|
||||
|
||||
/*
|
||||
* When the SYSCON STARTER registers are discontinuous, these functions are
|
||||
* implemented in fsl_power.c.
|
||||
*/
|
||||
#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
|
||||
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
|
||||
uint32_t index = 0;
|
||||
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
SYSCON->STARTERSET[index] = 1UL << intNumber;
|
||||
(void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
|
||||
}
|
||||
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
|
||||
(void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
|
||||
uint32_t index = 0;
|
||||
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
SYSCON->STARTERCLR[index] = 1UL << intNumber;
|
||||
}
|
||||
#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
|
||||
#endif /* FSL_FEATURE_POWERLIB_EXTEND */
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
#if defined(DWT)
|
||||
/* Use WDT. */
|
||||
void MSDK_EnableCpuCycleCounter(void)
|
||||
{
|
||||
/* Make sure the DWT trace fucntion is enabled. */
|
||||
if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
|
||||
{
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
}
|
||||
|
||||
/* CYCCNT not supported on this device. */
|
||||
assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
|
||||
|
||||
/* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */
|
||||
if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
|
||||
{
|
||||
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t MSDK_GetCpuCycleCount(void)
|
||||
{
|
||||
return DWT->CYCCNT;
|
||||
}
|
||||
#endif /* defined(DWT) */
|
||||
|
||||
#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT))
|
||||
/* Use software loop. */
|
||||
#if defined(__CC_ARM) /* This macro is arm v5 specific */
|
||||
/* clang-format off */
|
||||
__ASM static void DelayLoop(uint32_t count)
|
||||
{
|
||||
loop
|
||||
SUBS R0, R0, #1
|
||||
CMP R0, #0
|
||||
BNE loop
|
||||
BX LR
|
||||
}
|
||||
#elif defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */
|
||||
static void DelayLoop(uint32_t count)
|
||||
{
|
||||
__ASM volatile(" MOV X0, %0" : : "r"(count));
|
||||
__ASM volatile(
|
||||
"loop: \n"
|
||||
" SUB X0, X0, #1 \n"
|
||||
" CMP X0, #0 \n"
|
||||
|
||||
" BNE loop \n"
|
||||
:
|
||||
:
|
||||
: "r0");
|
||||
}
|
||||
/* clang-format on */
|
||||
#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
|
||||
/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
|
||||
* use SUB and CMP here for compatibility */
|
||||
static void DelayLoop(uint32_t count)
|
||||
{
|
||||
__ASM volatile(" MOV R0, %0" : : "r"(count));
|
||||
__ASM volatile(
|
||||
"loop: \n"
|
||||
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
|
||||
" SUB R0, R0, #1 \n"
|
||||
#else
|
||||
" SUBS R0, R0, #1 \n"
|
||||
#endif
|
||||
" CMP R0, #0 \n"
|
||||
|
||||
" BNE loop \n"
|
||||
:
|
||||
:
|
||||
: "r0");
|
||||
}
|
||||
#endif /* defined(__CC_ARM) */
|
||||
#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
|
||||
|
||||
/*!
|
||||
* @brief Delay at least for some time.
|
||||
* Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
|
||||
* effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
|
||||
* coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
|
||||
* up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
|
||||
*
|
||||
* @param delayTime_us Delay time in unit of microsecond.
|
||||
* @param coreClock_Hz Core clock frequency with Hz.
|
||||
*/
|
||||
void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
|
||||
{
|
||||
uint64_t count;
|
||||
|
||||
if (delayTime_us > 0U)
|
||||
{
|
||||
count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
|
||||
|
||||
assert(count <= UINT32_MAX);
|
||||
|
||||
#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
|
||||
|
||||
MSDK_EnableCpuCycleCounter();
|
||||
/* Calculate the count ticks. */
|
||||
count += MSDK_GetCpuCycleCount();
|
||||
|
||||
if (count > UINT32_MAX)
|
||||
{
|
||||
count -= UINT32_MAX;
|
||||
/* Wait for cyccnt overflow. */
|
||||
while (count < MSDK_GetCpuCycleCount())
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/* Wait for cyccnt reach count value. */
|
||||
while (count > MSDK_GetCpuCycleCount())
|
||||
{
|
||||
}
|
||||
#else
|
||||
/* Divide value may be different in various environment to ensure delay is precise.
|
||||
* Every loop count includes three instructions, due to Cortex-M7 sometimes executes
|
||||
* two instructions in one period, through test here set divide 1.5. Other M cores use
|
||||
* divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
|
||||
* not matter because other instructions outside while loop is enough to fill the time.
|
||||
*/
|
||||
#if (__CORTEX_M == 7)
|
||||
count = count / 3U * 2U;
|
||||
#else
|
||||
count = count / 4U;
|
||||
#endif
|
||||
DelayLoop((uint32_t)count);
|
||||
#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
|
||||
}
|
||||
}
|
||||
@ -1,842 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FSL_COMMON_ARM_H_
|
||||
#define FSL_COMMON_ARM_H_
|
||||
|
||||
/*
|
||||
* For CMSIS pack RTE.
|
||||
* CMSIS pack RTE generates "RTC_Components.h" which contains the statements
|
||||
* of the related <RTE_Components_h> element for all selected software components.
|
||||
*/
|
||||
#ifdef _RTE_
|
||||
#include "RTE_Components.h"
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @addtogroup ksdk_common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @name Atomic modification
|
||||
*
|
||||
* These macros are used for atomic access, such as read-modify-write
|
||||
* to the peripheral registers.
|
||||
*
|
||||
* - SDK_ATOMIC_LOCAL_ADD
|
||||
* - SDK_ATOMIC_LOCAL_SET
|
||||
* - SDK_ATOMIC_LOCAL_CLEAR
|
||||
* - SDK_ATOMIC_LOCAL_TOGGLE
|
||||
* - SDK_ATOMIC_LOCAL_CLEAR_AND_SET
|
||||
*
|
||||
* Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
|
||||
* means the address of the peripheral register or variable you want to modify
|
||||
* atomically, the parameter @c clearBits is the bits to clear, the parameter
|
||||
* @c setBits it the bits to set.
|
||||
* For example, to set a 32-bit register bit1:bit0 to 0b10, use like this:
|
||||
*
|
||||
* @code
|
||||
volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR;
|
||||
|
||||
SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02);
|
||||
@endcode
|
||||
*
|
||||
* In this example, the register bit1:bit0 are cleared and bit1 is set, as a result,
|
||||
* register bit1:bit0 = 0b10.
|
||||
*
|
||||
* @note For the platforms don't support exclusive load and store, these macros
|
||||
* disable the global interrupt to pretect the modification.
|
||||
*
|
||||
* @note These macros only guarantee the local processor atomic operations. For
|
||||
* the multi-processor devices, use hardware semaphore such as SEMA42 to
|
||||
* guarantee exclusive access if necessary.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
|
||||
/* clang-format on */
|
||||
|
||||
/* If the LDREX and STREX are supported, use them. */
|
||||
#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \
|
||||
do \
|
||||
{ \
|
||||
(val) = __LDREXB(addr); \
|
||||
(ops); \
|
||||
} while (0UL != __STREXB((val), (addr)))
|
||||
|
||||
#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \
|
||||
do \
|
||||
{ \
|
||||
(val) = __LDREXH(addr); \
|
||||
(ops); \
|
||||
} while (0UL != __STREXH((val), (addr)))
|
||||
|
||||
#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \
|
||||
do \
|
||||
{ \
|
||||
(val) = __LDREXW(addr); \
|
||||
(ops); \
|
||||
} while (0UL != __STREXW((val), (addr)))
|
||||
|
||||
static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val)
|
||||
{
|
||||
uint8_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val)
|
||||
{
|
||||
uint16_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val)
|
||||
{
|
||||
uint32_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val)
|
||||
{
|
||||
uint8_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val)
|
||||
{
|
||||
uint16_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val)
|
||||
{
|
||||
uint32_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits)
|
||||
{
|
||||
uint8_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits)
|
||||
{
|
||||
uint16_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits)
|
||||
{
|
||||
uint32_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits)
|
||||
{
|
||||
uint8_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits)
|
||||
{
|
||||
uint16_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits)
|
||||
{
|
||||
uint32_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits)
|
||||
{
|
||||
uint8_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits)
|
||||
{
|
||||
uint16_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits)
|
||||
{
|
||||
uint32_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits)
|
||||
{
|
||||
uint8_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits)
|
||||
{
|
||||
uint16_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
|
||||
}
|
||||
|
||||
static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits)
|
||||
{
|
||||
uint32_t s_val;
|
||||
|
||||
_SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
|
||||
}
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_ADD(addr, val) \
|
||||
((1UL == sizeof(*(addr))) ? \
|
||||
_SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \
|
||||
((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
|
||||
_SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_SUB(addr, val) \
|
||||
((1UL == sizeof(*(addr))) ? \
|
||||
_SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \
|
||||
((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
|
||||
_SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
|
||||
((1UL == sizeof(*(addr))) ? \
|
||||
_SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \
|
||||
((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
|
||||
_SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
|
||||
((1UL == sizeof(*(addr))) ? \
|
||||
_SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \
|
||||
((2UL == sizeof(*(addr))) ? \
|
||||
_SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
|
||||
_SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
|
||||
((1UL == sizeof(*(addr))) ? \
|
||||
_SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \
|
||||
((2UL == sizeof(*(addr))) ? \
|
||||
_SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
|
||||
_SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
|
||||
((1UL == sizeof(*(addr))) ? \
|
||||
_SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \
|
||||
((2UL == sizeof(*(addr))) ? \
|
||||
_SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \
|
||||
_SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits))))
|
||||
#else
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_ADD(addr, val) \
|
||||
do \
|
||||
{ \
|
||||
uint32_t s_atomicOldInt; \
|
||||
s_atomicOldInt = DisableGlobalIRQ(); \
|
||||
*(addr) += (val); \
|
||||
EnableGlobalIRQ(s_atomicOldInt); \
|
||||
} while (false)
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_SUB(addr, val) \
|
||||
do \
|
||||
{ \
|
||||
uint32_t s_atomicOldInt; \
|
||||
s_atomicOldInt = DisableGlobalIRQ(); \
|
||||
*(addr) -= (val); \
|
||||
EnableGlobalIRQ(s_atomicOldInt); \
|
||||
} while (false)
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
|
||||
do \
|
||||
{ \
|
||||
uint32_t s_atomicOldInt; \
|
||||
s_atomicOldInt = DisableGlobalIRQ(); \
|
||||
*(addr) |= (bits); \
|
||||
EnableGlobalIRQ(s_atomicOldInt); \
|
||||
} while (false)
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
|
||||
do \
|
||||
{ \
|
||||
uint32_t s_atomicOldInt; \
|
||||
s_atomicOldInt = DisableGlobalIRQ(); \
|
||||
*(addr) &= ~(bits); \
|
||||
EnableGlobalIRQ(s_atomicOldInt); \
|
||||
} while (false)
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
|
||||
do \
|
||||
{ \
|
||||
uint32_t s_atomicOldInt; \
|
||||
s_atomicOldInt = DisableGlobalIRQ(); \
|
||||
*(addr) ^= (bits); \
|
||||
EnableGlobalIRQ(s_atomicOldInt); \
|
||||
} while (false)
|
||||
|
||||
#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
|
||||
do \
|
||||
{ \
|
||||
uint32_t s_atomicOldInt; \
|
||||
s_atomicOldInt = DisableGlobalIRQ(); \
|
||||
*(addr) = (*(addr) & ~(clearBits)) | (setBits); \
|
||||
EnableGlobalIRQ(s_atomicOldInt); \
|
||||
} while (false)
|
||||
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @name Timer utilities */
|
||||
/* @{ */
|
||||
/*! Macro to convert a microsecond period to raw count value */
|
||||
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
|
||||
/*! Macro to convert a raw count value to microsecond */
|
||||
#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz))
|
||||
|
||||
/*! Macro to convert a millisecond period to raw count value */
|
||||
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
|
||||
/*! Macro to convert a raw count value to millisecond */
|
||||
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz))
|
||||
/* @} */
|
||||
|
||||
/*! @name ISR exit barrier
|
||||
* @{
|
||||
*
|
||||
* ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
* exception return operation might vector to incorrect interrupt.
|
||||
* For Cortex-M7, if core speed much faster than peripheral register write speed,
|
||||
* the peripheral interrupt flags may be still set after exiting ISR, this results to
|
||||
* the same error similar with errata 83869.
|
||||
*/
|
||||
#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
|
||||
#define SDK_ISR_EXIT_BARRIER __DSB()
|
||||
#else
|
||||
#define SDK_ISR_EXIT_BARRIER
|
||||
#endif
|
||||
|
||||
/* @} */
|
||||
|
||||
/*! @name Alignment variable definition macros */
|
||||
/* @{ */
|
||||
#if (defined(__ICCARM__))
|
||||
/*
|
||||
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
|
||||
* http:/ /supp.iar.com/Support/?note=24725
|
||||
*/
|
||||
_Pragma("diag_suppress=Pm120")
|
||||
#define SDK_PRAGMA(x) _Pragma(#x)
|
||||
_Pragma("diag_error=Pm120")
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
||||
#elif defined(__GNUC__)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
#else
|
||||
#error Toolchain not supported
|
||||
#endif
|
||||
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#endif
|
||||
|
||||
/*! Macro to change a value to a given size aligned value */
|
||||
#define SDK_SIZEALIGN(var, alignbytes) \
|
||||
((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
|
||||
/* @} */
|
||||
|
||||
/*! @name Non-cacheable region definition macros */
|
||||
/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
|
||||
* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable
|
||||
* variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
|
||||
* these zero-inited variables will be initialized to zero in system startup.
|
||||
*/
|
||||
/* @{ */
|
||||
|
||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \
|
||||
defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
||||
|
||||
#if (defined(__ICCARM__))
|
||||
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||
SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
|
||||
|
||||
#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
|
||||
#if (defined(__CC_ARM))
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
|
||||
#endif
|
||||
|
||||
#elif (defined(__GNUC__))
|
||||
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
|
||||
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
|
||||
*/
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes)
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes)
|
||||
|
||||
#endif
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Time sensitive region
|
||||
* @{
|
||||
*/
|
||||
#if (defined(__ICCARM__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
|
||||
#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess"
|
||||
#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
|
||||
SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess"
|
||||
#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var
|
||||
#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var
|
||||
#elif (defined(__GNUC__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var
|
||||
#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes)))
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif /* defined(__ICCARM__) */
|
||||
|
||||
/*! @name Ram Function */
|
||||
#if (defined(__ICCARM__))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
|
||||
#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
||||
#elif (defined(__GNUC__))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif /* defined(__ICCARM__) */
|
||||
/* @} */
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
void DefaultISR(void);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
|
||||
* defined in previous of this file.
|
||||
*/
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*
|
||||
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
|
||||
*/
|
||||
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
||||
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
||||
#include "fsl_reset.h"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief Enable specific interrupt.
|
||||
*
|
||||
* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt enabled successfully
|
||||
* @retval kStatus_Fail Failed to enable the interrupt
|
||||
*/
|
||||
static inline status_t EnableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
status_t status = kStatus_Success;
|
||||
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
else
|
||||
{
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_EnableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_EnableIRQ(interrupt);
|
||||
#endif
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt.
|
||||
*
|
||||
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt disabled successfully
|
||||
* @retval kStatus_Fail Failed to disable the interrupt
|
||||
*/
|
||||
static inline status_t DisableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
status_t status = kStatus_Success;
|
||||
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
else
|
||||
{
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_DisableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_DisableIRQ(interrupt);
|
||||
#endif
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the IRQ, and also set the interrupt priority.
|
||||
*
|
||||
* Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ to Enable.
|
||||
* @param priNum Priority number set to interrupt controller register.
|
||||
* @retval kStatus_Success Interrupt priority set successfully
|
||||
* @retval kStatus_Fail Failed to set the interrupt priority.
|
||||
*/
|
||||
static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)
|
||||
{
|
||||
status_t status = kStatus_Success;
|
||||
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
else
|
||||
{
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_SetPriority(interrupt, priNum);
|
||||
GIC_EnableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_SetPriority(interrupt, priNum);
|
||||
NVIC_EnableIRQ(interrupt);
|
||||
#endif
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set the IRQ priority.
|
||||
*
|
||||
* Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ to set.
|
||||
* @param priNum Priority number set to interrupt controller register.
|
||||
*
|
||||
* @retval kStatus_Success Interrupt priority set successfully
|
||||
* @retval kStatus_Fail Failed to set the interrupt priority.
|
||||
*/
|
||||
static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)
|
||||
{
|
||||
status_t status = kStatus_Success;
|
||||
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
else
|
||||
{
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_SetPriority(interrupt, priNum);
|
||||
#else
|
||||
NVIC_SetPriority(interrupt, priNum);
|
||||
#endif
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear the pending IRQ flag.
|
||||
*
|
||||
* Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The flag which IRQ to clear.
|
||||
*
|
||||
* @retval kStatus_Success Interrupt priority set successfully
|
||||
* @retval kStatus_Fail Failed to set the interrupt priority.
|
||||
*/
|
||||
static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
status_t status = kStatus_Success;
|
||||
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
else
|
||||
{
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_ClearPendingIRQ(interrupt);
|
||||
#else
|
||||
NVIC_ClearPendingIRQ(interrupt);
|
||||
#endif
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the global IRQ
|
||||
*
|
||||
* Disable the global interrupt and return the current primask register. User is required to provided the primask
|
||||
* register for the EnableGlobalIRQ().
|
||||
*
|
||||
* @return Current primask value.
|
||||
*/
|
||||
static inline uint32_t DisableGlobalIRQ(void)
|
||||
{
|
||||
uint32_t mask;
|
||||
|
||||
#if defined(CPSR_I_Msk)
|
||||
mask = __get_CPSR() & CPSR_I_Msk;
|
||||
#elif defined(DAIF_I_BIT)
|
||||
mask = __get_DAIF() & DAIF_I_BIT;
|
||||
#else
|
||||
mask = __get_PRIMASK();
|
||||
#endif
|
||||
__disable_irq();
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the global IRQ
|
||||
*
|
||||
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
|
||||
* convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
|
||||
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
|
||||
*
|
||||
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
|
||||
* DisableGlobalIRQ().
|
||||
*/
|
||||
static inline void EnableGlobalIRQ(uint32_t primask)
|
||||
{
|
||||
#if defined(CPSR_I_Msk)
|
||||
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
|
||||
#elif defined(DAIF_I_BIT)
|
||||
if (0UL == primask)
|
||||
{
|
||||
__enable_irq();
|
||||
}
|
||||
#else
|
||||
__set_PRIMASK(primask);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||
/*!
|
||||
* @brief install IRQ handler
|
||||
*
|
||||
* @param irq IRQ number
|
||||
* @param irqHandler IRQ handler address
|
||||
* @return The old IRQ handler address
|
||||
*/
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
|
||||
/*
|
||||
* When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
|
||||
* powerlib should be used instead of these functions.
|
||||
*/
|
||||
#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
|
||||
/*!
|
||||
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Enable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Disable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
#endif /* FSL_FEATURE_POWERLIB_EXTEND */
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
#if defined(DWT)
|
||||
/*!
|
||||
* @brief Enable the counter to get CPU cycles.
|
||||
*/
|
||||
void MSDK_EnableCpuCycleCounter(void);
|
||||
|
||||
/*!
|
||||
* @brief Get the current CPU cycle count.
|
||||
*
|
||||
* @return Current CPU cycle count.
|
||||
*/
|
||||
uint32_t MSDK_GetCpuCycleCount(void);
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* FSL_COMMON_ARM_H_ */
|
||||
@ -1,440 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2019, 2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_gpio.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.gpio"
|
||||
#endif
|
||||
|
||||
#if defined(GPIO_RSTS)
|
||||
#define GPIO_RESETS_ARRAY GPIO_RSTS
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
|
||||
defined(FSL_FEATURE_SOC_PORT_COUNT)
|
||||
static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
|
||||
static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
|
||||
|
||||
#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Array to map FGPIO instance number to clock name. */
|
||||
static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
|
||||
|
||||
#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
|
||||
|
||||
#if defined(GPIO_RESETS_ARRAY)
|
||||
/* Reset array */
|
||||
static const reset_ip_name_t s_gpioResets[] = GPIO_RESETS_ARRAY;
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
|
||||
defined(FSL_FEATURE_SOC_PORT_COUNT)
|
||||
/*!
|
||||
* @brief Gets the GPIO instance according to the GPIO base
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
|
||||
* @retval GPIO instance
|
||||
*/
|
||||
static uint32_t GPIO_GetInstance(GPIO_Type *base);
|
||||
#endif
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
|
||||
defined(FSL_FEATURE_SOC_PORT_COUNT) || defined(GPIO_RESETS_ARRAY)
|
||||
static uint32_t GPIO_GetInstance(GPIO_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
|
||||
{
|
||||
if (s_gpioBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_gpioBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
#endif
|
||||
/*!
|
||||
* brief Initializes a GPIO pin used by the board.
|
||||
*
|
||||
* To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
|
||||
* Then, call the GPIO_PinInit() function.
|
||||
*
|
||||
* This is an example to define an input pin or an output pin configuration.
|
||||
* code
|
||||
* Define a digital input pin configuration,
|
||||
* gpio_pin_config_t config =
|
||||
* {
|
||||
* kGPIO_DigitalInput,
|
||||
* 0,
|
||||
* }
|
||||
* Define a digital output pin configuration,
|
||||
* gpio_pin_config_t config =
|
||||
* {
|
||||
* kGPIO_DigitalOutput,
|
||||
* 0,
|
||||
* }
|
||||
* endcode
|
||||
*
|
||||
* param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* param pin GPIO port pin number
|
||||
* param config GPIO pin configuration pointer
|
||||
*/
|
||||
void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
#if defined(GPIO_RESETS_ARRAY)
|
||||
RESET_ReleasePeripheralReset(s_gpioResets[GPIO_GetInstance(base)]);
|
||||
#endif
|
||||
|
||||
if (config->pinDirection == kGPIO_DigitalInput)
|
||||
{
|
||||
base->PDDR &= GPIO_FIT_REG(~(1UL << pin));
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIO_PinWrite(base, pin, config->outputLogic);
|
||||
base->PDDR |= GPIO_FIT_REG((1UL << pin));
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
|
||||
void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info)
|
||||
{
|
||||
info->feature = (uint16_t)base->VERID;
|
||||
info->minor = (uint8_t)(base->VERID >> GPIO_VERID_MINOR_SHIFT);
|
||||
info->major = (uint8_t)(base->VERID >> GPIO_VERID_MAJOR_SHIFT);
|
||||
}
|
||||
#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
|
||||
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
|
||||
defined(FSL_FEATURE_SOC_PORT_COUNT)
|
||||
/*!
|
||||
* brief Reads the GPIO port interrupt status flag.
|
||||
*
|
||||
* If a pin is configured to generate the DMA request, the corresponding flag
|
||||
* is cleared automatically at the completion of the requested DMA transfer.
|
||||
* Otherwise, the flag remains set until a logic one is written to that flag.
|
||||
* If configured for a level sensitive interrupt that remains asserted, the flag
|
||||
* is set again immediately.
|
||||
*
|
||||
* param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
|
||||
* pin 0 and 17 have the interrupt.
|
||||
*/
|
||||
uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base)
|
||||
{
|
||||
uint8_t instance;
|
||||
PORT_Type *portBase;
|
||||
instance = (uint8_t)GPIO_GetInstance(base);
|
||||
portBase = s_portBases[instance];
|
||||
return portBase->ISFR;
|
||||
}
|
||||
#else
|
||||
/*!
|
||||
* brief Read the GPIO interrupt status flags.
|
||||
*
|
||||
* param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* return The current GPIO's interrupt status flag.
|
||||
* '1' means the related pin's flag is set, '0' means the related pin's flag not set.
|
||||
* For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
|
||||
*/
|
||||
uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base)
|
||||
{
|
||||
return base->ISFR[0];
|
||||
}
|
||||
#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
|
||||
/*!
|
||||
* brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).
|
||||
* param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
|
||||
*
|
||||
* return The current GPIO's interrupt status flag based on the selected interrupt channel.
|
||||
* '1' means the related pin's flag is set, '0' means the related pin's flag not set.
|
||||
* For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
|
||||
*/
|
||||
uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < 2U);
|
||||
return base->ISFR[channel];
|
||||
}
|
||||
#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
|
||||
/*!
|
||||
* brief Read individual pin's interrupt status flag.
|
||||
*
|
||||
* param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
|
||||
* param pin GPIO specific pin number.
|
||||
* return The current selected pin's interrupt status flag.
|
||||
*/
|
||||
uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin)
|
||||
{
|
||||
return (uint8_t)((base->ICR[pin] & GPIO_ICR_ISF_MASK) >> GPIO_ICR_ISF_SHIFT);
|
||||
}
|
||||
#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
|
||||
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
|
||||
defined(FSL_FEATURE_SOC_PORT_COUNT)
|
||||
/*!
|
||||
* brief Clears multiple GPIO pin interrupt status flags.
|
||||
*
|
||||
* param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* param mask GPIO pin number macro
|
||||
*/
|
||||
void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
uint8_t instance;
|
||||
PORT_Type *portBase;
|
||||
instance = (uint8_t)GPIO_GetInstance(base);
|
||||
portBase = s_portBases[instance];
|
||||
portBase->ISFR = mask;
|
||||
}
|
||||
#else
|
||||
/*!
|
||||
* brief Clears GPIO pin interrupt status flags.
|
||||
*
|
||||
* param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* param mask GPIO pin number macro
|
||||
*/
|
||||
void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->ISFR[0] = GPIO_FIT_REG(mask);
|
||||
}
|
||||
#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
|
||||
/*!
|
||||
* brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).
|
||||
*
|
||||
* param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* param mask GPIO pin number macro
|
||||
* param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
|
||||
*/
|
||||
void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel)
|
||||
{
|
||||
assert(channel < 2U);
|
||||
base->ISFR[channel] = GPIO_FIT_REG(mask);
|
||||
}
|
||||
#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
|
||||
/*!
|
||||
* brief Clear GPIO individual pin's interrupt status flag.
|
||||
*
|
||||
* param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
|
||||
* param pin GPIO specific pin number.
|
||||
*/
|
||||
void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin)
|
||||
{
|
||||
base->ICR[pin] |= GPIO_FIT_REG(GPIO_ICR_ISF(1U));
|
||||
}
|
||||
#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
|
||||
|
||||
#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
|
||||
/*!
|
||||
* brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
|
||||
* words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level
|
||||
* attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register
|
||||
* organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little
|
||||
* endian data convention.
|
||||
*
|
||||
* param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* param attribute GPIO checker attribute
|
||||
*/
|
||||
void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
|
||||
{
|
||||
#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
|
||||
base->GACR = ((uint8_t)attribute << GPIO_GACR_ACB_SHIFT);
|
||||
#else
|
||||
base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
|
||||
((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
|
||||
#endif /* FSL_FEATURE_GPIO_REGISTERS_WIDTH */
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
|
||||
defined(FSL_FEATURE_SOC_PORT_COUNT)
|
||||
static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
|
||||
#endif
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
|
||||
defined(FSL_FEATURE_SOC_PORT_COUNT)
|
||||
/*!
|
||||
* @brief Gets the FGPIO instance according to the GPIO base
|
||||
*
|
||||
* @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
|
||||
* @retval FGPIO instance
|
||||
*/
|
||||
static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
|
||||
#endif
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
|
||||
defined(FSL_FEATURE_SOC_PORT_COUNT)
|
||||
static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
|
||||
{
|
||||
if (s_fgpioBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_fgpioBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
|
||||
/*!
|
||||
* brief Initializes the FGPIO peripheral.
|
||||
*
|
||||
* This function ungates the FGPIO clock.
|
||||
*
|
||||
* param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
*/
|
||||
void FGPIO_PortInit(FGPIO_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Ungate FGPIO periphral clock */
|
||||
CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
|
||||
|
||||
/*!
|
||||
* brief Initializes a FGPIO pin used by the board.
|
||||
*
|
||||
* To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
|
||||
* Then, call the FGPIO_PinInit() function.
|
||||
*
|
||||
* This is an example to define an input pin or an output pin configuration:
|
||||
* code
|
||||
* Define a digital input pin configuration,
|
||||
* gpio_pin_config_t config =
|
||||
* {
|
||||
* kGPIO_DigitalInput,
|
||||
* 0,
|
||||
* }
|
||||
* Define a digital output pin configuration,
|
||||
* gpio_pin_config_t config =
|
||||
* {
|
||||
* kGPIO_DigitalOutput,
|
||||
* 0,
|
||||
* }
|
||||
* endcode
|
||||
*
|
||||
* param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* param pin FGPIO port pin number
|
||||
* param config FGPIO pin configuration pointer
|
||||
*/
|
||||
void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
if (config->pinDirection == kGPIO_DigitalInput)
|
||||
{
|
||||
base->PDDR &= ~(1UL << pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
FGPIO_PinWrite(base, pin, config->outputLogic);
|
||||
base->PDDR |= (1UL << pin);
|
||||
}
|
||||
}
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
|
||||
defined(FSL_FEATURE_SOC_PORT_COUNT)
|
||||
/*!
|
||||
* brief Reads the FGPIO port interrupt status flag.
|
||||
*
|
||||
* If a pin is configured to generate the DMA request, the corresponding flag
|
||||
* is cleared automatically at the completion of the requested DMA transfer.
|
||||
* Otherwise, the flag remains set until a logic one is written to that flag.
|
||||
* If configured for a level-sensitive interrupt that remains asserted, the flag
|
||||
* is set again immediately.
|
||||
*
|
||||
* param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
|
||||
* pin 0 and 17 have the interrupt.
|
||||
*/
|
||||
uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base)
|
||||
{
|
||||
uint8_t instance;
|
||||
instance = (uint8_t)FGPIO_GetInstance(base);
|
||||
PORT_Type *portBase;
|
||||
portBase = s_portBases[instance];
|
||||
return portBase->ISFR;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Clears the multiple FGPIO pin interrupt status flag.
|
||||
*
|
||||
* param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* param mask FGPIO pin number macro
|
||||
*/
|
||||
void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
uint8_t instance;
|
||||
instance = (uint8_t)FGPIO_GetInstance(base);
|
||||
PORT_Type *portBase;
|
||||
portBase = s_portBases[instance];
|
||||
portBase->ISFR = mask;
|
||||
}
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
|
||||
/*!
|
||||
* brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
|
||||
* words. Each 32-bit data port includes a GACR register, which defines the byte-level
|
||||
* attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
|
||||
* bytes in the GACR follow a standard little endian
|
||||
* data convention.
|
||||
*
|
||||
* param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* param attribute FGPIO checker attribute
|
||||
*/
|
||||
void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
|
||||
{
|
||||
base->GACR = ((uint32_t)attribute << FGPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB1_SHIFT) |
|
||||
((uint32_t)attribute << FGPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB3_SHIFT);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
|
||||
@ -1,799 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FSL_GPIO_H_
|
||||
#define FSL_GPIO_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup gpio
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief GPIO driver version. */
|
||||
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3))
|
||||
/*@}*/
|
||||
|
||||
#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
|
||||
#define GPIO_FIT_REG(value) \
|
||||
((uint8_t)(value)) /*!< For some platforms with 8-bit register width, cast the type to uint8_t */
|
||||
#else
|
||||
#define GPIO_FIT_REG(value) ((uint32_t)(value))
|
||||
#endif /*FSL_FEATURE_GPIO_REGISTERS_WIDTH*/
|
||||
|
||||
/*! @brief GPIO direction definition */
|
||||
typedef enum _gpio_pin_direction
|
||||
{
|
||||
kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
|
||||
kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
|
||||
} gpio_pin_direction_t;
|
||||
|
||||
#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
|
||||
/*! @brief GPIO checker attribute */
|
||||
typedef enum _gpio_checker_attribute
|
||||
{
|
||||
kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
|
||||
0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
|
||||
kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
|
||||
0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */
|
||||
kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
|
||||
0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */
|
||||
kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
|
||||
0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */
|
||||
kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
|
||||
0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */
|
||||
kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
|
||||
0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */
|
||||
kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
|
||||
0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */
|
||||
kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
|
||||
0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */
|
||||
kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */
|
||||
} gpio_checker_attribute_t;
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief The GPIO pin configuration structure.
|
||||
*
|
||||
* Each pin can only be configured as either an output pin or an input pin at a time.
|
||||
* If configured as an input pin, leave the outputConfig unused.
|
||||
* Note that in some use cases, the corresponding port property should be configured in advance
|
||||
* with the PORT_SetPinConfig().
|
||||
*/
|
||||
typedef struct _gpio_pin_config
|
||||
{
|
||||
gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
|
||||
/* Output configurations; ignore if configured as an input pin */
|
||||
uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
|
||||
} gpio_pin_config_t;
|
||||
|
||||
#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) || \
|
||||
!(defined(FSL_FEATURE_SOC_PORT_COUNT))
|
||||
/*! @brief Configures the interrupt generation condition. */
|
||||
typedef enum _gpio_interrupt_config
|
||||
{
|
||||
kGPIO_InterruptStatusFlagDisabled = 0x0U, /*!< Interrupt status flag is disabled. */
|
||||
kGPIO_DMARisingEdge = 0x1U, /*!< ISF flag and DMA request on rising edge. */
|
||||
kGPIO_DMAFallingEdge = 0x2U, /*!< ISF flag and DMA request on falling edge. */
|
||||
kGPIO_DMAEitherEdge = 0x3U, /*!< ISF flag and DMA request on either edge. */
|
||||
kGPIO_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
|
||||
kGPIO_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
|
||||
kGPIO_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
|
||||
kGPIO_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
|
||||
kGPIO_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
|
||||
kGPIO_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
|
||||
kGPIO_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
|
||||
kGPIO_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
|
||||
kGPIO_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
|
||||
kGPIO_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */
|
||||
} gpio_interrupt_config_t;
|
||||
#endif
|
||||
|
||||
#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
|
||||
/*! @brief Configures the selection of interrupt/DMA request/trigger output. */
|
||||
typedef enum _gpio_interrupt_selection
|
||||
{
|
||||
kGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */
|
||||
kGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */
|
||||
} gpio_interrupt_selection_t;
|
||||
#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
|
||||
|
||||
#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
|
||||
/*! @brief GPIO version information. */
|
||||
typedef struct _gpio_version_info
|
||||
{
|
||||
uint16_t feature; /*!< Feature Specification Number. */
|
||||
uint8_t minor; /*!< Minor Version Number. */
|
||||
uint8_t major; /*!< Major Version Number. */
|
||||
} gpio_version_info_t;
|
||||
#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
|
||||
|
||||
#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL
|
||||
/*! @brief GPIO pin and interrupt control. */
|
||||
typedef enum
|
||||
{
|
||||
kGPIO_PinControlNonSecure = 0x01U, /*!< Pin Control Non-Secure. */
|
||||
kGPIO_InterruptControlNonSecure = 0x02U, /*!< Interrupt Control Non-Secure. */
|
||||
kGPIO_PinControlNonPrivilege = 0x04U, /*!< Pin Control Non-Privilege. */
|
||||
kGPIO_InterruptControlNonPrivilege = 0x08U, /*!< Interrupt Control Non-Privilege. */
|
||||
} gpio_pin_interrupt_control_t;
|
||||
#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @addtogroup gpio_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @name GPIO Configuration */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes a GPIO pin used by the board.
|
||||
*
|
||||
* To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
|
||||
* Then, call the GPIO_PinInit() function.
|
||||
*
|
||||
* This is an example to define an input pin or an output pin configuration.
|
||||
* @code
|
||||
* Define a digital input pin configuration,
|
||||
* gpio_pin_config_t config =
|
||||
* {
|
||||
* kGPIO_DigitalInput,
|
||||
* 0,
|
||||
* }
|
||||
* Define a digital output pin configuration,
|
||||
* gpio_pin_config_t config =
|
||||
* {
|
||||
* kGPIO_DigitalOutput,
|
||||
* 0,
|
||||
* }
|
||||
* @endcode
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param pin GPIO port pin number
|
||||
* @param config GPIO pin configuration pointer
|
||||
*/
|
||||
void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
|
||||
|
||||
#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER
|
||||
/*!
|
||||
* @brief Get GPIO version information.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param info GPIO version information
|
||||
*/
|
||||
void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info);
|
||||
#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
|
||||
|
||||
#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL
|
||||
/*!
|
||||
* @brief lock or unlock secure privilege.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask pin or interrupt macro
|
||||
*/
|
||||
static inline void GPIO_SecurePrivilegeLock(GPIO_Type *base, gpio_pin_interrupt_control_t mask)
|
||||
{
|
||||
base->LOCK |= GPIO_FIT_REG(mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable Pin Control Non-Secure.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_EnablePinControlNonSecure(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->PCNS |= GPIO_FIT_REG(mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable Pin Control Non-Secure.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_DisablePinControlNonSecure(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->PCNS &= GPIO_FIT_REG(~mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable Pin Control Non-Privilege.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_EnablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->PCNP |= GPIO_FIT_REG(mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable Pin Control Non-Privilege.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_DisablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->PCNP &= GPIO_FIT_REG(~mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable Interrupt Control Non-Secure.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_EnableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->ICNS |= GPIO_FIT_REG(mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable Interrupt Control Non-Secure.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_DisableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->ICNS &= GPIO_FIT_REG(~mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable Interrupt Control Non-Privilege.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_EnableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->ICNP |= GPIO_FIT_REG(mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable Interrupt Control Non-Privilege.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_DisableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->ICNP &= GPIO_FIT_REG(~mask);
|
||||
}
|
||||
#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */
|
||||
|
||||
#if defined(FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL
|
||||
/*!
|
||||
* @brief Enable port input.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortInputEnable(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->PIDR &= GPIO_FIT_REG(~mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable port input.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->PIDR |= GPIO_FIT_REG(mask);
|
||||
}
|
||||
#endif /* FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*! @name GPIO Output Operations */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param pin GPIO pin number
|
||||
* @param output GPIO pin output logic level.
|
||||
* - 0: corresponding pin output low-logic level.
|
||||
* - 1: corresponding pin output high-logic level.
|
||||
*/
|
||||
static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
|
||||
{
|
||||
#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
|
||||
if (output == 0U)
|
||||
{
|
||||
base->PCOR = GPIO_FIT_REG(1UL << pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
base->PSOR = GPIO_FIT_REG(1UL << pin);
|
||||
}
|
||||
#else
|
||||
if (output == 0U)
|
||||
{
|
||||
base->PDOR |= GPIO_FIT_REG(1UL << pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
base->PDOR &= ~GPIO_FIT_REG(1UL << pin);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple GPIO pins to the logic 1.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
|
||||
base->PSOR = GPIO_FIT_REG(mask);
|
||||
#else
|
||||
base->PDOR |= GPIO_FIT_REG(mask);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple GPIO pins to the logic 0.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
|
||||
base->PCOR = GPIO_FIT_REG(mask);
|
||||
#else
|
||||
base->PDOR &= ~GPIO_FIT_REG(mask);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reverses the current output logic of the multiple GPIO pins.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL)
|
||||
base->PTOR = GPIO_FIT_REG(mask);
|
||||
#else
|
||||
base->PDOR ^= GPIO_FIT_REG(mask);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*! @name GPIO Input Operations */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Reads the current input value of the GPIO port.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param pin GPIO pin number
|
||||
* @retval GPIO port input value
|
||||
* - 0: corresponding pin input low-logic level.
|
||||
* - 1: corresponding pin input high-logic level.
|
||||
*/
|
||||
static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
|
||||
{
|
||||
return (((uint32_t)(base->PDIR) >> pin) & 0x01UL);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*! @name GPIO Interrupt */
|
||||
/*@{*/
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
|
||||
defined(FSL_FEATURE_SOC_PORT_COUNT)
|
||||
/*!
|
||||
* @brief Reads the GPIO port interrupt status flag.
|
||||
*
|
||||
* If a pin is configured to generate the DMA request, the corresponding flag
|
||||
* is cleared automatically at the completion of the requested DMA transfer.
|
||||
* Otherwise, the flag remains set until a logic one is written to that flag.
|
||||
* If configured for a level sensitive interrupt that remains asserted, the flag
|
||||
* is set again immediately.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
|
||||
* pin 0 and 17 have the interrupt.
|
||||
*/
|
||||
uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Clears multiple GPIO pin interrupt status flags.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask);
|
||||
#else
|
||||
/*!
|
||||
* @brief Configures the gpio pin interrupt/DMA request.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer.
|
||||
* @param pin GPIO pin number.
|
||||
* @param config GPIO pin interrupt configuration.
|
||||
* - #kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled.
|
||||
* - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
|
||||
* - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
|
||||
* - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
|
||||
* - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
|
||||
* - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
|
||||
* - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
|
||||
* - #kGPIO_InterruptLogicZero : Interrupt when logic zero.
|
||||
* - #kGPIO_InterruptRisingEdge : Interrupt on rising edge.
|
||||
* - #kGPIO_InterruptFallingEdge: Interrupt on falling edge.
|
||||
* - #kGPIO_InterruptEitherEdge : Interrupt on either edge.
|
||||
* - #kGPIO_InterruptLogicOne : Interrupt when logic one.
|
||||
* - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
|
||||
* - #kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).
|
||||
*/
|
||||
static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config)
|
||||
{
|
||||
assert(base);
|
||||
|
||||
base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | GPIO_ICR_IRQC(config));
|
||||
}
|
||||
|
||||
#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
|
||||
/*!
|
||||
* @brief Configures the gpio pin interrupt/DMA request/trigger output channel selection.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer.
|
||||
* @param pin GPIO pin number.
|
||||
* @param selection GPIO pin interrupt output selection.
|
||||
* - #kGPIO_InterruptOutput0: Interrupt/DMA request/trigger output 0.
|
||||
* - #kGPIO_InterruptOutput1 : Interrupt/DMA request/trigger output 1.
|
||||
*/
|
||||
static inline void GPIO_SetPinInterruptChannel(GPIO_Type *base, uint32_t pin, gpio_interrupt_selection_t selection)
|
||||
{
|
||||
assert(base);
|
||||
|
||||
base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQS_MASK) | GPIO_ICR_IRQS(selection));
|
||||
}
|
||||
#endif
|
||||
/*!
|
||||
* @brief Read the GPIO interrupt status flags.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @return The current GPIO's interrupt status flag.
|
||||
* '1' means the related pin's flag is set, '0' means the related pin's flag not set.
|
||||
* For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
|
||||
*/
|
||||
uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base);
|
||||
#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
|
||||
/*!
|
||||
* @brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).
|
||||
*
|
||||
* @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
|
||||
* @return The current GPIO's interrupt status flag based on the selected interrupt channel.
|
||||
* '1' means the related pin's flag is set, '0' means the related pin's flag not set.
|
||||
* For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.
|
||||
*/
|
||||
uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel);
|
||||
#endif
|
||||
/*!
|
||||
* @brief Read individual pin's interrupt status flag.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
|
||||
* @param pin GPIO specific pin number.
|
||||
* @return The current selected pin's interrupt status flag.
|
||||
*/
|
||||
uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin);
|
||||
|
||||
/*!
|
||||
* @brief Clears GPIO pin interrupt status flags.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask);
|
||||
#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
|
||||
/*!
|
||||
* @brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
* @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1.
|
||||
*/
|
||||
void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel);
|
||||
#endif
|
||||
/*!
|
||||
* @brief Clear GPIO individual pin's interrupt status flag.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
|
||||
* @param pin GPIO specific pin number.
|
||||
*/
|
||||
void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin);
|
||||
|
||||
/*!
|
||||
* @brief Reads the GPIO DMA request flags.
|
||||
* The corresponding flag will be cleared automatically at the completion of the requested
|
||||
* DMA transfer
|
||||
*/
|
||||
static inline uint32_t GPIO_GetPinsDMARequestFlags(GPIO_Type *base)
|
||||
{
|
||||
assert(base);
|
||||
return (base->ISFR[1]);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the GPIO interrupt configuration in PCR register for multiple pins.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer.
|
||||
* @param mask GPIO pin number macro.
|
||||
* @param config GPIO pin interrupt configuration.
|
||||
* - #kGPIO_InterruptStatusFlagDisabled: Interrupt disabled.
|
||||
* - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
|
||||
* - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
|
||||
* - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
|
||||
* - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
|
||||
* - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
|
||||
* - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
|
||||
* - #kGPIO_InterruptLogicZero : Interrupt when logic zero.
|
||||
* - #kGPIO_InterruptRisingEdge : Interrupt on rising edge.
|
||||
* - #kGPIO_InterruptFallingEdge: Interrupt on falling edge.
|
||||
* - #kGPIO_InterruptEitherEdge : Interrupt on either edge.
|
||||
* - #kGPIO_InterruptLogicOne : Interrupt when logic one.
|
||||
* - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
|
||||
* - #kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..
|
||||
*/
|
||||
static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config)
|
||||
{
|
||||
assert(base);
|
||||
|
||||
if (0UL != (mask & 0xffffUL))
|
||||
{
|
||||
base->GICLR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU));
|
||||
}
|
||||
mask = mask >> 16U;
|
||||
if (mask != 0UL)
|
||||
{
|
||||
base->GICHR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
|
||||
/*!
|
||||
* brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
|
||||
* words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level
|
||||
* attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register
|
||||
* organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little
|
||||
* endian data convention.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
|
||||
* @param attribute GPIO checker attribute
|
||||
*/
|
||||
void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* @addtogroup fgpio_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*
|
||||
* Introduces the FGPIO feature.
|
||||
*
|
||||
* The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT
|
||||
* interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and
|
||||
* complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
|
||||
*/
|
||||
|
||||
#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
|
||||
|
||||
/*! @name FGPIO Configuration */
|
||||
/*@{*/
|
||||
|
||||
#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
|
||||
/*!
|
||||
* @brief Initializes the FGPIO peripheral.
|
||||
*
|
||||
* This function ungates the FGPIO clock.
|
||||
*
|
||||
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
*/
|
||||
void FGPIO_PortInit(FGPIO_Type *base);
|
||||
#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
|
||||
|
||||
/*!
|
||||
* @brief Initializes a FGPIO pin used by the board.
|
||||
*
|
||||
* To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
|
||||
* Then, call the FGPIO_PinInit() function.
|
||||
*
|
||||
* This is an example to define an input pin or an output pin configuration:
|
||||
* @code
|
||||
* Define a digital input pin configuration,
|
||||
* gpio_pin_config_t config =
|
||||
* {
|
||||
* kGPIO_DigitalInput,
|
||||
* 0,
|
||||
* }
|
||||
* Define a digital output pin configuration,
|
||||
* gpio_pin_config_t config =
|
||||
* {
|
||||
* kGPIO_DigitalOutput,
|
||||
* 0,
|
||||
* }
|
||||
* @endcode
|
||||
*
|
||||
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* @param pin FGPIO port pin number
|
||||
* @param config FGPIO pin configuration pointer
|
||||
*/
|
||||
void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*! @name FGPIO Output Operations */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
|
||||
*
|
||||
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* @param pin FGPIO pin number
|
||||
* @param output FGPIOpin output logic level.
|
||||
* - 0: corresponding pin output low-logic level.
|
||||
* - 1: corresponding pin output high-logic level.
|
||||
*/
|
||||
static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output)
|
||||
{
|
||||
if (output == 0U)
|
||||
{
|
||||
base->PCOR = 1UL << pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->PSOR = 1UL << pin;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple FGPIO pins to the logic 1.
|
||||
*
|
||||
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* @param mask FGPIO pin number macro
|
||||
*/
|
||||
static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->PSOR = mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple FGPIO pins to the logic 0.
|
||||
*
|
||||
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* @param mask FGPIO pin number macro
|
||||
*/
|
||||
static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->PCOR = mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reverses the current output logic of the multiple FGPIO pins.
|
||||
*
|
||||
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* @param mask FGPIO pin number macro
|
||||
*/
|
||||
static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->PTOR = mask;
|
||||
}
|
||||
/*@}*/
|
||||
|
||||
/*! @name FGPIO Input Operations */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Reads the current input value of the FGPIO port.
|
||||
*
|
||||
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* @param pin FGPIO pin number
|
||||
* @retval FGPIO port input value
|
||||
* - 0: corresponding pin input low-logic level.
|
||||
* - 1: corresponding pin input high-logic level.
|
||||
*/
|
||||
static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin)
|
||||
{
|
||||
return (((base->PDIR) >> pin) & 0x01U);
|
||||
}
|
||||
/*@}*/
|
||||
|
||||
/*! @name FGPIO Interrupt */
|
||||
/*@{*/
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
|
||||
defined(FSL_FEATURE_SOC_PORT_COUNT)
|
||||
|
||||
/*!
|
||||
* @brief Reads the FGPIO port interrupt status flag.
|
||||
*
|
||||
* If a pin is configured to generate the DMA request, the corresponding flag
|
||||
* is cleared automatically at the completion of the requested DMA transfer.
|
||||
* Otherwise, the flag remains set until a logic one is written to that flag.
|
||||
* If configured for a level-sensitive interrupt that remains asserted, the flag
|
||||
* is set again immediately.
|
||||
*
|
||||
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
|
||||
* pin 0 and 17 have the interrupt.
|
||||
*/
|
||||
uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Clears the multiple FGPIO pin interrupt status flag.
|
||||
*
|
||||
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* @param mask FGPIO pin number macro
|
||||
*/
|
||||
void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask);
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
|
||||
/*!
|
||||
* @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
|
||||
* words. Each 32-bit data port includes a GACR register, which defines the byte-level
|
||||
* attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
|
||||
* bytes in the GACR follow a standard little endian
|
||||
* data convention.
|
||||
*
|
||||
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||||
* @param attribute FGPIO checker attribute
|
||||
*/
|
||||
void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
|
||||
#endif /* FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FSL_GPIO_H_*/
|
||||
@ -1,380 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_lpflexcomm.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm"
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Used for conversion between `void*` and `uint32_t`.
|
||||
*/
|
||||
typedef union pvoid_to_u32
|
||||
{
|
||||
void *pvoid;
|
||||
uint32_t u32;
|
||||
} pvoid_to_u32_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*! @brief check whether lpflexcomm supports peripheral type */
|
||||
static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph);
|
||||
|
||||
/*! @brief Changes LP_FLEXCOMM mode. */
|
||||
static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock);
|
||||
|
||||
/*! @brief Common LPFLEXCOMM IRQhandle. */
|
||||
static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance);
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Array to map LP_FLEXCOMM instance number to base address. */
|
||||
static const uint32_t s_lpflexcommBaseAddrs[] = LP_FLEXCOMM_BASE_ADDRS;
|
||||
|
||||
/*! @brief Array to map LP_FLEXCOMM instance PTRS. */
|
||||
static LP_FLEXCOMM_Type *const s_lpflexcommBase[] = LP_FLEXCOMM_BASE_PTRS;
|
||||
|
||||
/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
|
||||
static lpflexcomm_irq_handler_t s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)];
|
||||
|
||||
/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
|
||||
static void *s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)];
|
||||
|
||||
/*! @brief Array to map LP_FLEXCOMM instance number to IRQ number. */
|
||||
IRQn_Type const kFlexcommIrqs[] = LP_FLEXCOMM_IRQS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief IDs of clock for each LP_FLEXCOMM module */
|
||||
static const clock_ip_name_t s_lpflexcommClocks[] = LP_FLEXCOMM_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
#if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET)
|
||||
/*! @brief Pointers to LP_FLEXCOMM resets for each instance. */
|
||||
static const reset_ip_name_t s_lpflexcommResets[] = LP_FLEXCOMM_RSTS;
|
||||
#endif
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
/* check whether lpflexcomm supports peripheral type */
|
||||
static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph)
|
||||
{
|
||||
if (periph == LP_FLEXCOMM_PERIPH_NONE)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
else if (periph <= LP_FLEXCOMM_PERIPH_LPI2C)
|
||||
{
|
||||
return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false;
|
||||
}
|
||||
else if (periph == LP_FLEXCOMM_PERIPH_LPI2CAndLPUART)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
/*! @brief Returns for LP_FLEXCOMM base address. */
|
||||
uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance)
|
||||
{
|
||||
if(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs))
|
||||
{
|
||||
return s_lpflexcommBaseAddrs[instance];
|
||||
}
|
||||
return 0U;
|
||||
}
|
||||
|
||||
/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */
|
||||
uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance)
|
||||
{
|
||||
LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance];
|
||||
return base->ISTAT;
|
||||
}
|
||||
|
||||
/* Get the index corresponding to the LP_FLEXCOMM */
|
||||
/*! brief Returns instance number for LP_FLEXCOMM module with given base address. */
|
||||
uint32_t LP_FLEXCOMM_GetInstance(void *base)
|
||||
{
|
||||
uint32_t i;
|
||||
pvoid_to_u32_t BaseAddr;
|
||||
BaseAddr.pvoid = base;
|
||||
|
||||
for (i = 0U; i < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs); i++)
|
||||
{
|
||||
if (BaseAddr.u32 == s_lpflexcommBaseAddrs[i])
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(i < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs));
|
||||
return i;
|
||||
}
|
||||
|
||||
/* Changes LP_FLEXCOMM mode */
|
||||
static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock)
|
||||
{
|
||||
assert(periph <= LP_FLEXCOMM_PERIPH_LPI2CAndLPUART);
|
||||
LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance];
|
||||
|
||||
/* Check whether peripheral type is present */
|
||||
if (!LP_FLEXCOMM_PeripheralIsPresent(base, periph))
|
||||
{
|
||||
return kStatus_OutOfRange;
|
||||
}
|
||||
|
||||
/* Flexcomm is locked to different peripheral type than expected */
|
||||
if (((base->PSELID & LP_FLEXCOMM_PSELID_LOCK_MASK) != 0U) &&
|
||||
((base->PSELID & LP_FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph))
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Check if we are asked to lock */
|
||||
if (lock != 0)
|
||||
{
|
||||
base->PSELID = (uint32_t)periph | LP_FLEXCOMM_PSELID_LOCK_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->PSELID = (uint32_t)periph;
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*! brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */
|
||||
status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph)
|
||||
{
|
||||
assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable the peripheral clock */
|
||||
CLOCK_EnableClock(s_lpflexcommClocks[instance]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
#if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET)
|
||||
/* Reset the LP_FLEXCOMM module before configuring it.*/
|
||||
RESET_ClearPeripheralReset(s_lpflexcommResets[instance]);
|
||||
#endif
|
||||
/* Set the LP_FLEXCOMM to given peripheral */
|
||||
return LP_FLEXCOMM_SetPeriph(instance, periph, 0);
|
||||
}
|
||||
|
||||
/*! brief Deinitializes LP_FLEXCOMM. */
|
||||
void LP_FLEXCOMM_Deinit(uint32_t instance)
|
||||
{
|
||||
assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable the peripheral clock */
|
||||
CLOCK_DisableClock(s_lpflexcommClocks[instance]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
RESET_SetPeripheralReset(s_lpflexcommResets[instance]);
|
||||
}
|
||||
|
||||
/*! brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to
|
||||
* LP_FLEXCOMM mode */
|
||||
void LP_FLEXCOMM_SetIRQHandler(uint32_t instance,
|
||||
lpflexcomm_irq_handler_t handler,
|
||||
void *lpflexcommHandle,
|
||||
LP_FLEXCOMM_PERIPH_T periph)
|
||||
{
|
||||
assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
|
||||
/* Clear handler first to avoid execution of the handler with wrong handle */
|
||||
s_lpflexcommIrqHandler[periph][instance] = NULL;
|
||||
s_lpflexcommHandle[periph][instance] = lpflexcommHandle;
|
||||
s_lpflexcommIrqHandler[periph][instance] = handler;
|
||||
}
|
||||
|
||||
static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance)
|
||||
{
|
||||
uint32_t interruptStat;
|
||||
|
||||
interruptStat = LP_FLEXCOMM_GetInterruptStatus(instance);
|
||||
if ((interruptStat &
|
||||
((uint32_t)kLPFLEXCOMM_I2cSlaveInterruptFlag | (uint32_t)kLPFLEXCOMM_I2cMasterInterruptFlag)) != 0U)
|
||||
{
|
||||
if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C][instance] != NULL)
|
||||
{
|
||||
s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C][instance](
|
||||
instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPI2C][instance]);
|
||||
}
|
||||
}
|
||||
if ((interruptStat & ((uint32_t)kLPFLEXCOMM_UartRxInterruptFlag | (uint32_t)kLPFLEXCOMM_UartTxInterruptFlag)) != 0U)
|
||||
{
|
||||
if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPUART][instance] != NULL)
|
||||
{
|
||||
s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPUART][instance](
|
||||
instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPUART][instance]);
|
||||
}
|
||||
}
|
||||
if (((interruptStat & (uint32_t)kLPFLEXCOMM_SpiInterruptFlag)) != 0U)
|
||||
{
|
||||
if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPSPI][instance] != NULL)
|
||||
{
|
||||
s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPSPI][instance](
|
||||
instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPSPI][instance]);
|
||||
}
|
||||
}
|
||||
SDK_ISR_EXIT_BARRIER;
|
||||
}
|
||||
|
||||
/* IRQ handler functions overloading weak symbols in the startup */
|
||||
#if defined(LP_FLEXCOMM0)
|
||||
void LP_FLEXCOMM0_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM0_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(0U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM1)
|
||||
void LP_FLEXCOMM1_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM1_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(1U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM2)
|
||||
void LP_FLEXCOMM2_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM2_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(2U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM3)
|
||||
void LP_FLEXCOMM3_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM3_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(3U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM4)
|
||||
void LP_FLEXCOMM4_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM4_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(4U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM5)
|
||||
void LP_FLEXCOMM5_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM5_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(5U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM6)
|
||||
void LP_FLEXCOMM6_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM6_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(6U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM7)
|
||||
void LP_FLEXCOMM7_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM7_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(7U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM8)
|
||||
void LP_FLEXCOMM8_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM8_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(8U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM9)
|
||||
void LP_FLEXCOMM9_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM9_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(9U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM10)
|
||||
void LP_FLEXCOMM10_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM10_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(10U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM11)
|
||||
void LP_FLEXCOMM11_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM11_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(11U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM12)
|
||||
void LP_FLEXCOMM12_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM12_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(12U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM13)
|
||||
void LP_FLEXCOMM13_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM13_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(13U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM17)
|
||||
void LP_FLEXCOMM17_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM17_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(17U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM18)
|
||||
void LP_FLEXCOMM18_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM18_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(18U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM19)
|
||||
void LP_FLEXCOMM19_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM19_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(19U);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(LP_FLEXCOMM20)
|
||||
void LP_FLEXCOMM20_DriverIRQHandler(void);
|
||||
void LP_FLEXCOMM20_DriverIRQHandler(void)
|
||||
{
|
||||
LP_FLEXCOMM_CommonIRQHandler(20U);
|
||||
}
|
||||
#endif
|
||||
@ -1,88 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef FSL_LP_FLEXCOMM_H_
|
||||
#define FSL_LP_FLEXCOMM_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup lpflexcomm_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief FlexCOMM driver version. */
|
||||
#define FSL_LP_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief LP_FLEXCOMM peripheral modes. */
|
||||
typedef enum
|
||||
{
|
||||
LP_FLEXCOMM_PERIPH_NONE, /*!< No peripheral */
|
||||
LP_FLEXCOMM_PERIPH_LPUART, /*!< LPUART peripheral */
|
||||
LP_FLEXCOMM_PERIPH_LPSPI, /*!< LPSPI Peripheral */
|
||||
LP_FLEXCOMM_PERIPH_LPI2C, /*!< LPI2C Peripheral */
|
||||
LP_FLEXCOMM_PERIPH_LPI2CAndLPUART = 7, /*!< LPI2C and LPUART Peripheral */
|
||||
} LP_FLEXCOMM_PERIPH_T;
|
||||
|
||||
/*! @brief LP_FLEXCOMM interrupt source flags. */
|
||||
enum _lpflexcomm_interrupt_flag
|
||||
{
|
||||
kLPFLEXCOMM_I2cSlaveInterruptFlag = LP_FLEXCOMM_ISTAT_I2CS_MASK, /* LPI2C slave interrupt. */
|
||||
kLPFLEXCOMM_I2cMasterInterruptFlag = LP_FLEXCOMM_ISTAT_I2CM_MASK, /* LPI2C master interrupt. */
|
||||
kLPFLEXCOMM_SpiInterruptFlag = LP_FLEXCOMM_ISTAT_SPI_MASK, /* LPSPI interrupt. */
|
||||
kLPFLEXCOMM_UartRxInterruptFlag = LP_FLEXCOMM_ISTAT_UARTRX_MASK, /* LPUART RX interrupt. */
|
||||
kLPFLEXCOMM_UartTxInterruptFlag = LP_FLEXCOMM_ISTAT_UARTTX_MASK, /* LPUART TX interrupt. */
|
||||
|
||||
kLPFLEXCOMM_AllInterruptFlag = kLPFLEXCOMM_I2cSlaveInterruptFlag | kLPFLEXCOMM_I2cMasterInterruptFlag |
|
||||
kLPFLEXCOMM_SpiInterruptFlag | kLPFLEXCOMM_UartRxInterruptFlag |
|
||||
kLPFLEXCOMM_UartTxInterruptFlag,
|
||||
};
|
||||
|
||||
/*! @brief Typedef for interrupt handler. */
|
||||
typedef void (*lpflexcomm_irq_handler_t)(uint32_t instance, void *handle);
|
||||
|
||||
/*! @brief Array with IRQ number for each LP_FLEXCOMM module. */
|
||||
extern IRQn_Type const kFlexcommIrqs[];
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*! @brief Returns instance number for LP_FLEXCOMM module with given base address. */
|
||||
uint32_t LP_FLEXCOMM_GetInstance(void *base);
|
||||
|
||||
/*! @brief Returns for LP_FLEXCOMM base address. */
|
||||
uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance);
|
||||
|
||||
/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */
|
||||
uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance);
|
||||
|
||||
/*! @brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */
|
||||
status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph);
|
||||
|
||||
/*! @brief Deinitializes LP_FLEXCOMM. */
|
||||
void LP_FLEXCOMM_Deinit(uint32_t instance);
|
||||
|
||||
/*! @brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to
|
||||
* LP_FLEXCOMM mode */
|
||||
void LP_FLEXCOMM_SetIRQHandler(uint32_t instance,
|
||||
lpflexcomm_irq_handler_t handler,
|
||||
void *lpflexcommHandle,
|
||||
LP_FLEXCOMM_PERIPH_T periph);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* FSL_LP_FLEXCOMM_H_*/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,679 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef FSL_PORT_H_
|
||||
#define FSL_PORT_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup port
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.port"
|
||||
#endif
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief PORT driver version. */
|
||||
#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
|
||||
/*@}*/
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
|
||||
/*! @brief Internal resistor pull feature selection */
|
||||
enum _port_pull
|
||||
{
|
||||
kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
|
||||
kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */
|
||||
kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
|
||||
/*! @brief Internal resistor pull value selection */
|
||||
enum _port_pull_value
|
||||
{
|
||||
kPORT_LowPullResistor = 0U, /*!< Low internal pull resistor value is selected. */
|
||||
kPORT_HighPullResistor = 1U, /*!< High internal pull resistor value is selected. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
|
||||
/*! @brief Slew rate selection */
|
||||
enum _port_slew_rate
|
||||
{
|
||||
kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
|
||||
kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
|
||||
/*! @brief Open Drain feature enable/disable */
|
||||
enum _port_open_drain_enable
|
||||
{
|
||||
kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
|
||||
kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
|
||||
/*! @brief Passive filter feature enable/disable */
|
||||
enum _port_passive_filter_enable
|
||||
{
|
||||
kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
|
||||
kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
|
||||
/*! @brief Configures the drive strength. */
|
||||
enum _port_drive_strength
|
||||
{
|
||||
kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */
|
||||
kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
|
||||
/*! @brief Configures the drive strength1. */
|
||||
enum _port_drive_strength1
|
||||
{
|
||||
kPORT_NormalDriveStrength = 0U, /*!< Normal drive strength */
|
||||
kPORT_DoubleDriveStrength = 1U, /*!< Double drive strength */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
|
||||
/*! @brief input buffer disable/enable. */
|
||||
enum _port_input_buffer
|
||||
{
|
||||
kPORT_InputBufferDisable = 0U, /*!< Digital input is disabled */
|
||||
kPORT_InputBufferEnable = 1U, /*!< Digital input is enabled */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT
|
||||
/*! @brief Digital input is not inverted or it is inverted. */
|
||||
enum _port_invet_input
|
||||
{
|
||||
kPORT_InputNormal = 0U, /*!< Digital input is not inverted */
|
||||
kPORT_InputInvert = 1U, /*!< Digital input is inverted */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
|
||||
/*! @brief Unlock/lock the pin control register field[15:0] */
|
||||
enum _port_lock_register
|
||||
{
|
||||
kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
|
||||
kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
|
||||
};
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
|
||||
/*! @brief Pin mux selection */
|
||||
typedef enum _port_mux
|
||||
{
|
||||
kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
|
||||
kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */
|
||||
kPORT_MuxAlt0 = 0U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt1 = 1U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt2 = 2U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt3 = 3U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt4 = 4U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt5 = 5U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt6 = 6U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt7 = 7U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt8 = 8U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt9 = 9U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt10 = 10U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt11 = 11U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt12 = 12U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt13 = 13U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt14 = 14U, /*!< Chip-specific */
|
||||
kPORT_MuxAlt15 = 15U, /*!< Chip-specific */
|
||||
} port_mux_t;
|
||||
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
|
||||
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
|
||||
/*! @brief Configures the interrupt generation condition. */
|
||||
typedef enum _port_interrupt
|
||||
{
|
||||
kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST || defined(DOXYGEN_OUTPUT)
|
||||
kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
|
||||
kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
|
||||
kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG || defined(DOXYGEN_OUTPUT)
|
||||
kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
|
||||
kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
|
||||
kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
|
||||
#endif
|
||||
kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
|
||||
kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
|
||||
kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
|
||||
kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
|
||||
kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
|
||||
#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER || defined(DOXYGEN_OUTPUT)
|
||||
kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
|
||||
kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */
|
||||
#endif
|
||||
} port_interrupt_t;
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
|
||||
/*! @brief Digital filter clock source selection */
|
||||
typedef enum _port_digital_filter_clock_source
|
||||
{
|
||||
kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
|
||||
kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
|
||||
} port_digital_filter_clock_source_t;
|
||||
|
||||
/*! @brief PORT digital filter feature configuration definition */
|
||||
typedef struct _port_digital_filter_config
|
||||
{
|
||||
uint32_t digitalFilterWidth; /*!< Set digital filter width */
|
||||
port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
|
||||
} port_digital_filter_config_t;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
|
||||
/*! @brief PORT pin configuration structure */
|
||||
typedef struct _port_pin_config
|
||||
{
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
|
||||
uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
|
||||
#else
|
||||
uint16_t : 2;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
|
||||
uint16_t pullValueSelect : 1; /*!< Pull value select */
|
||||
#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
|
||||
uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
|
||||
|
||||
#if !(defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE)
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
|
||||
uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
|
||||
uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
|
||||
uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
|
||||
uint16_t driveStrength1 : 1; /*!< Normal/Double drive strength enable/disable */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3)
|
||||
uint16_t mux : 3; /*!< Pin mux Configure */
|
||||
uint16_t : 1;
|
||||
#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4)
|
||||
uint16_t mux : 4; /*!< Pin mux Configure */
|
||||
#else
|
||||
uint16_t : 4;
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
|
||||
uint16_t inputBuffer : 1; /*!< Input Buffer Configure */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT
|
||||
uint16_t invertInput : 1; /*!< Invert Input Configure */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */
|
||||
|
||||
uint16_t : 1;
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
|
||||
uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
|
||||
#else
|
||||
uint16_t : 1;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
|
||||
} port_pin_config_t;
|
||||
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
|
||||
/*! @brief PORT version information. */
|
||||
typedef struct _port_version_info
|
||||
{
|
||||
uint16_t feature; /*!< Feature Specification Number. */
|
||||
uint8_t minor; /*!< Minor Version Number. */
|
||||
uint8_t major; /*!< Major Version Number. */
|
||||
} port_version_info_t;
|
||||
#endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE
|
||||
/*! @brief PORT voltage range. */
|
||||
typedef enum _port_voltage_range
|
||||
{
|
||||
kPORT_VoltageRange1Dot71V_3Dot6V = 0x0U, /*!< Port voltage range is 1.71 V - 3.6 V. */
|
||||
kPORT_VoltageRange2Dot70V_3Dot6V = 0x1U, /*!< Port voltage range is 2.70 V - 3.6 V. */
|
||||
} port_voltage_range_t;
|
||||
#endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
|
||||
/*! @name Configuration */
|
||||
/*@{*/
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
|
||||
/*!
|
||||
* @brief Get PORT version information.
|
||||
*
|
||||
* @param base PORT peripheral base pointer
|
||||
* @param info PORT version information
|
||||
*/
|
||||
static inline void PORT_GetVersionInfo(PORT_Type *base, port_version_info_t *info)
|
||||
{
|
||||
uint32_t verid = base->VERID;
|
||||
info->feature = (uint16_t)verid;
|
||||
info->minor = (uint8_t)(verid >> PORT_VERID_MINOR_SHIFT);
|
||||
info->major = (uint8_t)(verid >> PORT_VERID_MAJOR_SHIFT);
|
||||
}
|
||||
#endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE
|
||||
/*!
|
||||
* @brief Get PORT version information.
|
||||
*
|
||||
* @note : PORTA_CONFIG[RANGE] controls the voltage ranges of Port A, B, and C. Read or write PORTB_CONFIG[RANGE] and
|
||||
* PORTC_CONFIG[RANGE] does not take effect.
|
||||
*
|
||||
* @param base PORT peripheral base pointer
|
||||
* @param range port voltage range
|
||||
*/
|
||||
static inline void PORT_SecletPortVoltageRange(PORT_Type *base, port_voltage_range_t range)
|
||||
{
|
||||
base->CONFIG = (uint32_t)range;
|
||||
}
|
||||
#endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */
|
||||
|
||||
/*!
|
||||
* @brief Sets the port PCR register.
|
||||
*
|
||||
* This is an example to define an input pin or output pin PCR configuration.
|
||||
* @code
|
||||
* // Define a digital input pin PCR configuration
|
||||
* port_pin_config_t config = {
|
||||
* kPORT_PullUp,
|
||||
* kPORT_FastSlewRate,
|
||||
* kPORT_PassiveFilterDisable,
|
||||
* kPORT_OpenDrainDisable,
|
||||
* kPORT_LowDriveStrength,
|
||||
* kPORT_MuxAsGpio,
|
||||
* kPORT_UnLockRegister,
|
||||
* };
|
||||
* @endcode
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param config PORT PCR register configuration structure.
|
||||
*/
|
||||
static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
uint32_t addr = (uint32_t)&base->PCR[pin];
|
||||
*(volatile uint16_t *)(addr) = *((const uint16_t *)(const void *)config);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the port PCR register for multiple pins.
|
||||
*
|
||||
* This is an example to define input pins or output pins PCR configuration.
|
||||
* @code
|
||||
* Define a digital input pin PCR configuration
|
||||
* port_pin_config_t config = {
|
||||
* kPORT_PullUp ,
|
||||
* kPORT_PullEnable,
|
||||
* kPORT_FastSlewRate,
|
||||
* kPORT_PassiveFilterDisable,
|
||||
* kPORT_OpenDrainDisable,
|
||||
* kPORT_LowDriveStrength,
|
||||
* kPORT_MuxAsGpio,
|
||||
* kPORT_UnlockRegister,
|
||||
* };
|
||||
* @endcode
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
* @param config PORT PCR register configuration structure.
|
||||
*/
|
||||
static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
uint16_t pcrl = *((const uint16_t *)(const void *)config);
|
||||
|
||||
if (0U != (mask & 0xffffU))
|
||||
{
|
||||
base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
|
||||
}
|
||||
if (0U != (mask >> 16))
|
||||
{
|
||||
base->GPCHR = (mask & 0xffff0000U) | pcrl;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG
|
||||
/*!
|
||||
* @brief Sets the port interrupt configuration in PCR register for multiple pins.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
* @param config PORT pin interrupt configuration.
|
||||
* - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
|
||||
* - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
|
||||
* - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
|
||||
* - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
|
||||
* - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
|
||||
* - #kPORT_InterruptLogicZero : Interrupt when logic zero.
|
||||
* - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
|
||||
* - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
|
||||
* - #kPORT_InterruptEitherEdge : Interrupt on either edge.
|
||||
* - #kPORT_InterruptLogicOne : Interrupt when logic one.
|
||||
* - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
|
||||
* - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..
|
||||
*/
|
||||
static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
if (0U != ((uint32_t)mask & 0xffffU))
|
||||
{
|
||||
base->GICLR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU);
|
||||
}
|
||||
mask = mask >> 16;
|
||||
if (0U != mask)
|
||||
{
|
||||
base->GICHR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Configures the pin muxing.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param mux pin muxing slot selection.
|
||||
* - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
|
||||
* - #kPORT_MuxAsGpio : Set as GPIO.
|
||||
* - #kPORT_MuxAlt2 : chip-specific.
|
||||
* - #kPORT_MuxAlt3 : chip-specific.
|
||||
* - #kPORT_MuxAlt4 : chip-specific.
|
||||
* - #kPORT_MuxAlt5 : chip-specific.
|
||||
* - #kPORT_MuxAlt6 : chip-specific.
|
||||
* - #kPORT_MuxAlt7 : chip-specific.
|
||||
* @note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
|
||||
* the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
|
||||
* reset to zero : kPORT_PinDisabledOrAnalog).
|
||||
* This function is recommended to use to reset the pin mux
|
||||
*
|
||||
*/
|
||||
static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
|
||||
{
|
||||
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
|
||||
}
|
||||
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
|
||||
|
||||
/*!
|
||||
* @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
* @param enable PORT digital filter configuration.
|
||||
*/
|
||||
static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable == true)
|
||||
{
|
||||
base->DFER |= mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->DFER &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param config PORT digital filter configuration structure.
|
||||
*/
|
||||
static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
base->DFCR = PORT_DFCR_CS(config->clockSource);
|
||||
base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
|
||||
}
|
||||
|
||||
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
|
||||
/*@}*/
|
||||
|
||||
/*! @name Interrupt */
|
||||
/*@{*/
|
||||
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
|
||||
/*!
|
||||
* @brief Configures the port pin interrupt/DMA request.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param config PORT pin interrupt configuration.
|
||||
* - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
|
||||
* - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
|
||||
* - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
|
||||
* - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
|
||||
* - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
|
||||
* - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
|
||||
* - #kPORT_InterruptLogicZero : Interrupt when logic zero.
|
||||
* - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
|
||||
* - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
|
||||
* - #kPORT_InterruptEitherEdge : Interrupt on either edge.
|
||||
* - #kPORT_InterruptLogicOne : Interrupt when logic one.
|
||||
* - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
|
||||
* - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).
|
||||
*/
|
||||
static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
|
||||
{
|
||||
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
|
||||
/*!
|
||||
* @brief Configures the port pin drive strength.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param strength PORT pin drive strength
|
||||
* - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
|
||||
* - #kPORT_HighDriveStrength = 1U - High-drive strength is configured.
|
||||
*/
|
||||
static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength)
|
||||
{
|
||||
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
|
||||
/*!
|
||||
* @brief Enables the port pin double drive strength.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param enable PORT pin drive strength configuration.
|
||||
*/
|
||||
static inline void PORT_EnablePinDoubleDriveStrength(PORT_Type *base, uint32_t pin, bool enable)
|
||||
{
|
||||
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE1_MASK) | PORT_PCR_DSE1(enable);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
|
||||
/*!
|
||||
* @brief Configures the port pin pull value.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param pin PORT pin number.
|
||||
* @param value PORT pin pull value
|
||||
* - #kPORT_LowPullResistor = 0U - Low internal pull resistor value is selected.
|
||||
* - #kPORT_HighPullResistor = 1U - High internal pull resistor value is selected.
|
||||
*/
|
||||
static inline void PORT_SetPinPullValue(PORT_Type *base, uint32_t pin, uint8_t value)
|
||||
{
|
||||
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_PV_MASK) | PORT_PCR_PV(value);
|
||||
}
|
||||
#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
|
||||
|
||||
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
|
||||
/*!
|
||||
* @brief Reads the whole port status flag.
|
||||
*
|
||||
* If a pin is configured to generate the DMA request, the corresponding flag
|
||||
* is cleared automatically at the completion of the requested DMA transfer.
|
||||
* Otherwise, the flag remains set until a logic one is written to that flag.
|
||||
* If configured for a level sensitive interrupt that remains asserted, the flag
|
||||
* is set again immediately.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @return Current port interrupt status flags, for example, 0x00010001 means the
|
||||
* pin 0 and 16 have the interrupt.
|
||||
*/
|
||||
static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
|
||||
{
|
||||
return base->ISFR;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the multiple pin interrupt status flag.
|
||||
*
|
||||
* @param base PORT peripheral base pointer.
|
||||
* @param mask PORT pin number macro.
|
||||
*/
|
||||
static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
|
||||
{
|
||||
base->ISFR = mask;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_PORT_SUPPORT_EFT) && FSL_FEATURE_PORT_SUPPORT_EFT
|
||||
/*!
|
||||
* @brief Get EFT detect flags.
|
||||
*
|
||||
* @param base PORT peripheral base pointer
|
||||
* @return EFT detect flags
|
||||
*/
|
||||
static inline uint32_t PORT_GetEFTDetectFlags(PORT_Type *base)
|
||||
{
|
||||
return base->EDFR;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable EFT detect interrupts.
|
||||
*
|
||||
* @param base PORT peripheral base pointer
|
||||
* @param interrupt EFT detect interrupt
|
||||
*/
|
||||
static inline void PORT_EnableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)
|
||||
{
|
||||
base->EDIER |= interrupt;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable EFT detect interrupts.
|
||||
*
|
||||
* @param base PORT peripheral base pointer
|
||||
* @param interrupt EFT detect interrupt
|
||||
*/
|
||||
static inline void PORT_DisableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)
|
||||
{
|
||||
base->EDIER &= ~interrupt;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear all low EFT detector.
|
||||
*
|
||||
* @note : Port B and Port C pins share the same EFT detector clear control from PORTC_EDCR register. Any write to the
|
||||
* PORTB_EDCR does not take effect.
|
||||
* @param base PORT peripheral base pointer
|
||||
* @param interrupt EFT detect interrupt
|
||||
*/
|
||||
static inline void PORT_ClearAllLowEFTDetectors(PORT_Type *base)
|
||||
{
|
||||
base->EDCR |= PORT_EDCR_EDLC_MASK;
|
||||
base->EDCR &= ~PORT_EDCR_EDLC_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear all high EFT detector.
|
||||
*
|
||||
* @param base PORT peripheral base pointer
|
||||
* @param interrupt EFT detect interrupt
|
||||
*/
|
||||
static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base)
|
||||
{
|
||||
base->EDCR |= PORT_EDCR_EDHC_MASK;
|
||||
base->EDCR &= ~PORT_EDCR_EDHC_MASK;
|
||||
}
|
||||
#endif /* FSL_FEATURE_PORT_SUPPORT_EFT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* FSL_PORT_H_ */
|
||||
@ -1,102 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022, NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_reset.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.reset"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
|
||||
/*!
|
||||
* brief Assert reset to peripheral.
|
||||
*
|
||||
* Asserts reset signal to specified peripheral module.
|
||||
*
|
||||
* param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
|
||||
* and reset bit position in the reset register.
|
||||
*/
|
||||
void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
|
||||
{
|
||||
const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
|
||||
const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
|
||||
const uint32_t bitMask = 1UL << bitPos;
|
||||
volatile uint32_t *pResetCtrl;
|
||||
|
||||
assert(bitPos < 32u);
|
||||
|
||||
/* reset register is in SYSCON */
|
||||
/* set bit */
|
||||
SYSCON->PRESETCTRLSET[regIndex] = bitMask;
|
||||
/* wait until it reads 0b1 */
|
||||
pResetCtrl = &(SYSCON->PRESETCTRL0);
|
||||
while (0u == ((uint32_t)((volatile uint32_t *)pResetCtrl)[regIndex] & bitMask))
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Clear reset to peripheral.
|
||||
*
|
||||
* Clears reset signal to specified peripheral module, allows it to operate.
|
||||
*
|
||||
* param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
|
||||
* and reset bit position in the reset register.
|
||||
*/
|
||||
void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
|
||||
{
|
||||
const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
|
||||
const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
|
||||
const uint32_t bitMask = 1UL << bitPos;
|
||||
volatile uint32_t *pResetCtrl;
|
||||
|
||||
assert(bitPos < 32u);
|
||||
|
||||
/* reset register is in SYSCON */
|
||||
|
||||
/* clear bit */
|
||||
SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
|
||||
/* wait until it reads 0b0 */
|
||||
pResetCtrl = &(SYSCON->PRESETCTRL0);
|
||||
while (bitMask == ((uint32_t)((volatile uint32_t *)pResetCtrl)[regIndex] & bitMask))
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Reset peripheral module.
|
||||
*
|
||||
* Reset peripheral module.
|
||||
*
|
||||
* param peripheral Peripheral to reset. The enum argument contains encoding of reset register
|
||||
* and reset bit position in the reset register.
|
||||
*/
|
||||
void RESET_PeripheralReset(reset_ip_name_t peripheral)
|
||||
{
|
||||
RESET_SetPeripheralReset(peripheral);
|
||||
RESET_ClearPeripheralReset(peripheral);
|
||||
}
|
||||
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */
|
||||
@ -1,261 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022, NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _FSL_RESET_H_
|
||||
#define _FSL_RESET_H_
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup reset
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief reset driver version 2.4.0 */
|
||||
#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief Enumeration for peripheral reset control bits
|
||||
*
|
||||
* Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
|
||||
*/
|
||||
typedef enum _SYSCON_RSTn
|
||||
{
|
||||
kFMU_RST_SHIFT_RSTn = 0 | 9U, /**< Flash management unit reset control */
|
||||
kFLEXSPI_RST_SHIFT_RSTn = 0 | 11U, /**< FLEXSPI reset control */
|
||||
kMUX_RST_SHIFT_RSTn = 0 | 12U, /**< Input mux reset control */
|
||||
kPORT0_RST_SHIFT_RSTn = 0 | 13U, /**< PORT0 reset control */
|
||||
kPORT1_RST_SHIFT_RSTn = 0 | 14U, /**< PORT1 reset control */
|
||||
kPORT2_RST_SHIFT_RSTn = 0 | 15U, /**< PORT2 reset control */
|
||||
kPORT3_RST_SHIFT_RSTn = 0 | 16U, /**< PORT3 reset control */
|
||||
kPORT4_RST_SHIFT_RSTn = 0 | 17U, /**< PORT4 reset control */
|
||||
kGPIO0_RST_SHIFT_RSTn = 0 | 19U, /**< GPIO0 reset control */
|
||||
kGPIO1_RST_SHIFT_RSTn = 0 | 20U, /**< GPIO1 reset control */
|
||||
kGPIO2_RST_SHIFT_RSTn = 0 | 21U, /**< GPIO2 reset control */
|
||||
kGPIO3_RST_SHIFT_RSTn = 0 | 22U, /**< GPIO3 reset control */
|
||||
kGPIO4_RST_SHIFT_RSTn = 0 | 23U, /**< GPIO4 reset control */
|
||||
kPINT_RST_SHIFT_RSTn = 0 | 25U, /**< Pin interrupt (PINT) reset control */
|
||||
kDMA0_RST_SHIFT_RSTn = 0 | 26U, /**< DMA0 reset control */
|
||||
kCRC_RST_SHIFT_RSTn = 0 | 27U, /**< CRC reset control */
|
||||
kMAILBOX_RST_SHIFT_RSTn = 0 | 31U, /**< Mailbox reset control */
|
||||
|
||||
kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
|
||||
kOSTIMER_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer reset control */
|
||||
kSCT_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM(SCT) reset control */
|
||||
kADC0_RST_SHIFT_RSTn = 65536 | 3U, /**< ADC0 reset control */
|
||||
kADC1_RST_SHIFT_RSTn = 65536 | 4U, /**< ADC1 reset control */
|
||||
kDAC0_RST_SHIFT_RSTn = 65536 | 5U, /**< DAC0 reset control */
|
||||
kEVSIM0_RST_SHIFT_RSTn = 65536 | 8U, /**< EVSIM0 reset control */
|
||||
kEVSIM1_RST_SHIFT_RSTn = 65536 | 9U, /**< EVSIM1 reset control */
|
||||
kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
|
||||
kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
|
||||
kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
|
||||
kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
|
||||
kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
|
||||
kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
|
||||
kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
|
||||
kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
|
||||
kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
|
||||
kFC8_RST_SHIFT_RSTn = 65536 | 19U, /**< Flexcomm Interface 8 reset control */
|
||||
kFC9_RST_SHIFT_RSTn = 65536 | 20U, /**< MICFIL reset control */
|
||||
kMICFIL_RST_SHIFT_RSTn = 65536 | 21U, /**< Flexcomm Interface 7 reset control */
|
||||
kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */
|
||||
kUSB0_RAM_RST_SHIFT_RSTn = 65536 | 23U, /**< USB0 RAM reset control */
|
||||
kUSB0_FS_DCD_RST_SHIFT_RSTn = 65536 | 24U, /**< USB0-FS DCD reset control */
|
||||
kUSB0_FS_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0-FS reset control */
|
||||
kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */
|
||||
kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */
|
||||
kSMART_DMA_RST_SHIFT_RSTn = 65536 | 31U, /**< SmartDMA reset control */
|
||||
|
||||
kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */
|
||||
kENET_RST_SHIFT_RSTn = 131072 | 2U, /**< Ethernet reset control */
|
||||
kUSDHC_RST_SHIFT_RSTn = 131072 | 3U, /**< uSDHC reset control */
|
||||
kFLEXIO_RST_SHIFT_RSTn = 131072 | 4U, /**< FLEXIO reset control */
|
||||
kSAI0_RST_SHIFT_RSTn = 131072 | 5U, /**< SAI0 reset control */
|
||||
kSAI1_RST_SHIFT_RSTn = 131072 | 6U, /**< SAI1 reset control */
|
||||
kTRO_RST_SHIFT_RSTn = 131072 | 7U, /**< TRO reset control */
|
||||
kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */
|
||||
kTRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< TRNG reset control */
|
||||
kFLEXCAN0_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcan0 reset control */
|
||||
kFLEXCAN1_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcan1 reset control */
|
||||
kUSB_HS_RST_SHIFT_RSTn = 131072 | 16U, /**< USB HS reset control */
|
||||
kUSB_HS_PHY_RST_SHIFT_RSTn = 131072 | 17U, /**< USB HS PHY reset control */
|
||||
kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */
|
||||
kPLU_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU reset control */
|
||||
kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */
|
||||
kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */
|
||||
kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */
|
||||
kPKC_RST_SHIFT_RSTn = 131072 | 24U, /**< PKC reset control */
|
||||
kSM3_RST_SHIFT_RSTn = 131072 | 30U, /**< SM3 reset control */
|
||||
|
||||
kI3C0_RST_SHIFT_RSTn = 196608 | 0U, /**< I3C0 reset control */
|
||||
kI3C1_RST_SHIFT_RSTn = 196608 | 1U, /**< I3C1 reset control */
|
||||
kSINC_RST_SHIFT_RSTn = 196608 | 2U, /**< SINC reset control */
|
||||
kCOOLFLUX_RST_SHIFT_RSTn = 196608 | 3U, /**< CoolFlux reset control */
|
||||
kENC0_RST_SHIFT_RSTn = 196608 | 4U, /**< ENC0 reset control */
|
||||
kENC1_RST_SHIFT_RSTn = 196608 | 5U, /**< ENC1 reset control */
|
||||
kPWM0_RST_SHIFT_RSTn = 196608 | 6U, /**< PWM0 reset control */
|
||||
kPWM1_RST_SHIFT_RSTn = 196608 | 7U, /**< PWM1 reset control */
|
||||
kAOI0_RST_SHIFT_RSTn = 196608 | 8U, /**< AOI0 reset control */
|
||||
kDAC1_RST_SHIFT_RSTn = 196608 | 11U, /**< DAC1 reset control */
|
||||
kDAC2_RST_SHIFT_RSTn = 196608 | 12U, /**< DAC2 reset control */
|
||||
kOPAMP0_RST_SHIFT_RSTn = 196608 | 13U, /**< OPAMP0 reset control */
|
||||
kOPAMP1_RST_SHIFT_RSTn = 196608 | 14U, /**< OPAMP1 reset control */
|
||||
kOPAMP2_RST_SHIFT_RSTn = 196608 | 15U, /**< OPAMP2 reset control */
|
||||
kCMP2_RST_SHIFT_RSTn = 196608 | 18U, /**< CMP2 reset control */
|
||||
kVREF_RST_SHIFT_RSTn = 196608 | 19U, /**< VREF reset control */
|
||||
kCOOLFLUX_APB_RST_SHIFT_RSTn = 196608 | 20U, /**< CoolFlux APB reset control */
|
||||
kNEUTRON_RST_SHIFT_RSTn = 196608 | 21U, /**< Neutron mini reset control */
|
||||
kTSI_RST_SHIFT_RSTn = 196608 | 22U, /**< TSI reset control */
|
||||
kEWM_RST_SHIFT_RSTn = 196608 | 23U, /**< EWM reset control */
|
||||
kEIM_RST_SHIFT_RSTn = 196608 | 24U, /**< EIM reset control */
|
||||
kSEMA42_RST_SHIFT_RSTn = 196608 | 27U, /**< Semaphore reset control */
|
||||
} SYSCON_RSTn_t;
|
||||
|
||||
/** Array initializers with peripheral reset bits **/
|
||||
#define ADC_RSTS \
|
||||
{ \
|
||||
kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for ADC peripheral */
|
||||
#define CRC_RSTS \
|
||||
{ \
|
||||
kCRC_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for CRC peripheral */
|
||||
#define CTIMER_RSTS \
|
||||
{ \
|
||||
kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \
|
||||
kCTIMER4_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for CTIMER peripheral */
|
||||
#define DMA_RSTS_N \
|
||||
{ \
|
||||
kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for DMA peripheral */
|
||||
|
||||
#define LP_FLEXCOMM_RSTS \
|
||||
{ \
|
||||
kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
|
||||
kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for FLEXCOMM peripheral */
|
||||
#define GPIO_RSTS_N \
|
||||
{ \
|
||||
kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \
|
||||
kGPIO4_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for GPIO peripheral */
|
||||
#define INPUTMUX_RSTS \
|
||||
{ \
|
||||
kMUX_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for INPUTMUX peripheral */
|
||||
#define FLASH_RSTS \
|
||||
{ \
|
||||
kFMC_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for Flash peripheral */
|
||||
#define MRT_RSTS \
|
||||
{ \
|
||||
kMRT_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for MRT peripheral */
|
||||
#define PINT_RSTS \
|
||||
{ \
|
||||
kPINT_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for PINT peripheral */
|
||||
#define TRNG_RSTS \
|
||||
{ \
|
||||
kTRNG_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for TRNG peripheral */
|
||||
#define SCT_RSTS \
|
||||
{ \
|
||||
kSCT_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for SCT peripheral */
|
||||
#define UTICK_RSTS \
|
||||
{ \
|
||||
kUTICK_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for UTICK peripheral */
|
||||
#define PLU_RSTS_N \
|
||||
{ \
|
||||
kPLU_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for PLU peripheral */
|
||||
#define OSTIMER_RSTS \
|
||||
{ \
|
||||
kOSTIMER_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for OSTIMER peripheral */
|
||||
#define POWERQUAD_RSTS \
|
||||
{ \
|
||||
kPOWERQUAD_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for Powerquad peripheral */
|
||||
#define I3C_RSTS \
|
||||
{ \
|
||||
kI3C0_RST_SHIFT_RSTn, kI3C1_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for I3C peripheral */
|
||||
typedef SYSCON_RSTn_t reset_ip_name_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Assert reset to peripheral.
|
||||
*
|
||||
* Asserts reset signal to specified peripheral module.
|
||||
*
|
||||
* @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
|
||||
* and reset bit position in the reset register.
|
||||
*/
|
||||
void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
|
||||
|
||||
/*!
|
||||
* @brief Clear reset to peripheral.
|
||||
*
|
||||
* Clears reset signal to specified peripheral module, allows it to operate.
|
||||
*
|
||||
* @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
|
||||
* and reset bit position in the reset register.
|
||||
*/
|
||||
void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
|
||||
|
||||
/*!
|
||||
* @brief Reset peripheral module.
|
||||
*
|
||||
* Reset peripheral module.
|
||||
*
|
||||
* @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
|
||||
* and reset bit position in the reset register.
|
||||
*/
|
||||
void RESET_PeripheralReset(reset_ip_name_t peripheral);
|
||||
|
||||
/*!
|
||||
* @brief Release peripheral module.
|
||||
*
|
||||
* Release peripheral module.
|
||||
*
|
||||
* @param peripheral Peripheral to release. The enum argument contains encoding of reset register
|
||||
* and reset bit position in the reset register.
|
||||
*/
|
||||
static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)
|
||||
{
|
||||
RESET_ClearPeripheralReset(peripheral);
|
||||
}
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_RESET_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,106 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="com.crt.dsfdebug.crtmcu.launchType">
|
||||
<stringAttribute key=".gdbinit" value=""/>
|
||||
<booleanAttribute key="attach" value="false"/>
|
||||
<booleanAttribute key="boot.config.enable" value="false"/>
|
||||
<stringAttribute key="boot.configuration.control" value=""/>
|
||||
<stringAttribute key="bootrom.stall" value="0x50000040"/>
|
||||
<stringAttribute key="com.crt.ctrlcenter.OFSemuDetails" value="LinkServer"/>
|
||||
<booleanAttribute key="com.crt.ctrlcenter.crtInit" value="true"/>
|
||||
<stringAttribute key="com.crt.ctrlcenter.currentWireType" value="SWD"/>
|
||||
<booleanAttribute key="com.crt.ctrlcenter.mainBreakIsHardware" value="true"/>
|
||||
<booleanAttribute key="com.crt.ctrlcenter.saveState" value="true"/>
|
||||
<stringAttribute key="com.crt.ctrlcenter.serialNumber" value="LinkServerNXP SemiconductorsMCU-LINK FRDM-MCXN947 (r0E7) CMSIS-DAP V3.128NNF4LOKTTTMAC"/>
|
||||
<mapAttribute key="com.crt.ctrlcenter.symbolsGroupSettings"/>
|
||||
<intAttribute key="com.crt.ctrlcenter.version" value="6"/>
|
||||
<stringAttribute key="com.nxp.mcuxpresso.flash.base.address" value="0x0"/>
|
||||
<booleanAttribute key="com.nxp.mcuxpresso.flash.clear.console" value="true"/>
|
||||
<booleanAttribute key="com.nxp.mcuxpresso.flash.confirm" value="false"/>
|
||||
<stringAttribute key="com.nxp.mcuxpresso.flash.erase.algorithm" value="Mass erase"/>
|
||||
<stringAttribute key="com.nxp.mcuxpresso.flash.executable" value="axf"/>
|
||||
<stringAttribute key="com.nxp.mcuxpresso.flash.program.action" value="Program"/>
|
||||
<booleanAttribute key="com.nxp.mcuxpresso.flash.reset.target" value="true"/>
|
||||
<stringAttribute key="com.nxp.mcuxpresso.ide.probe.manufacturer" value="NXP Semiconductors"/>
|
||||
<stringAttribute key="com.nxp.mcuxpresso.ide.probe.name" value="MCU-LINK FRDM-MCXN947 (r0E7) CMSIS-DAP V3.128"/>
|
||||
<stringAttribute key="com.nxp.mcuxpresso.ide.probe.type" value="LinkServer"/>
|
||||
<stringAttribute key="debug.level" value="2"/>
|
||||
<stringAttribute key="emu.speed" value=""/>
|
||||
<stringAttribute key="flash.driver.reset" value=""/>
|
||||
<stringAttribute key="gdbserver.host" value="localhost"/>
|
||||
<stringAttribute key="gdbserver.port" value="10989"/>
|
||||
<booleanAttribute key="gdbserver.start" value="true"/>
|
||||
<booleanAttribute key="internal.attach.slave" value="false"/>
|
||||
<booleanAttribute key="internal.cache" value="false"/>
|
||||
<stringAttribute key="internal.connect.script" value=""/>
|
||||
<stringAttribute key="internal.core.index" value=""/>
|
||||
<booleanAttribute key="internal.has_swo" value="true"/>
|
||||
<booleanAttribute key="internal.multi.swd" value="true"/>
|
||||
<stringAttribute key="internal.prelaunch.command" value=""/>
|
||||
<stringAttribute key="internal.reset.script" value=""/>
|
||||
<stringAttribute key="internal.resethandling" value=""/>
|
||||
<stringAttribute key="internal.semihost" value="On"/>
|
||||
<stringAttribute key="internal.wirespeed" value=""/>
|
||||
<stringAttribute key="internal.wiretype" value="SWD"/>
|
||||
<stringAttribute key="isp.control" value="xxxx"/>
|
||||
<stringAttribute key="launch.config.handler" value="com.crt.ctrlcenter.launch.CRTLaunchConfigHandler"/>
|
||||
<booleanAttribute key="mem.access" value="false"/>
|
||||
<stringAttribute key="misc.options" value=" --romstalldelay 600"/>
|
||||
<stringAttribute key="ondisconnect" value="cont"/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="0"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set non-stop on set pagination off set mi-async set remotetimeout 60000 ##target_extended_remote## set mem inaccessible-by-default ${mem.access} mon ondisconnect ${ondisconnect} set arm force-mode thumb ${load}"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="10989"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value="${run}"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_ON_FORK" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.EXTERNAL_CONSOLE" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.GDB_INIT" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE_MODE" value="UseSoftTrace"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.TRACEPOINT_MODE" value="TP_NORMAL_ONLY"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="gdb"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/frdm-mcxn947-xpresso-baremetal-builtin.axf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="frdm-mcxn947-xpresso-baremetal-builtin"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.crt.advproject.config.exe.debug.1734776104"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="false"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/frdm-mcxn947-xpresso-baremetal-builtin"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<mapAttribute key="org.eclipse.debug.core.preferred_launchers">
|
||||
<mapEntry key="[debug]" value="com.nxp.mcuxpresso.core.debug.support.linkserver.launch.LinkServerGdbLaunch"/>
|
||||
</mapAttribute>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <sourceLookupDirector> <sourceContainers duplicates="false"> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;default/&gt;&#10;" typeId="org.eclipse.debug.core.containerType.default"/> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;mapping backend_enabled=&quot;true&quot; name=&quot;Found Mappings&quot;&gt;&#10; &lt;mapEntry memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#10;&amp;lt;mapEntry backendPath=&amp;quot;/root/Documents/MCUXpresso_11.8.1_1197/workspace/frdmmcxn947_enet_txrx_rxpoll/Debug/src/&amp;quot; localPath=&amp;quot;/home/scaprile/work/cesanta/mongoose/src/&amp;quot;/&amp;gt;&amp;#10;&quot;/&gt;&#10;&lt;/mapping&gt;&#10;" typeId="org.eclipse.cdt.debug.core.containerType.mapping"/> </sourceContainers> </sourceLookupDirector> "/>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><memoryBlockExpressionList context="reserved-for-future-use"/>"/>
|
||||
<stringAttribute key="process_factory_id" value="com.nxp.mcuxpresso.core.debug.override.MCXProcessFactory"/>
|
||||
<booleanAttribute key="redlink.disable.preconnect.script" value="false"/>
|
||||
<booleanAttribute key="redlink.enable.flashhashing" value="true"/>
|
||||
<booleanAttribute key="redlink.enable.rangestepping" value="true"/>
|
||||
<stringAttribute key="run" value="cont"/>
|
||||
<booleanAttribute key="vector.catch" value="false"/>
|
||||
</launchConfiguration>
|
||||
@ -1 +0,0 @@
|
||||
Component middleware.baremetal has no real source. Its main purpose is to provide baremetal condition corresponding to RTOS condition.
|
||||
@ -1,187 +0,0 @@
|
||||
// Copyright (c) 2024 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
static volatile uint64_t s_ticks; // Milliseconds since boot
|
||||
void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
|
||||
s_ticks++;
|
||||
}
|
||||
|
||||
#if 0
|
||||
bool mg_random(void *buf, size_t len) { // Use on-board RNG
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
uint64_t mg_millis(void) { // Let Mongoose use our uptime function
|
||||
return s_ticks; // Return number of milliseconds since boot
|
||||
}
|
||||
|
||||
void hal_init(void) {
|
||||
clock_init(); // Set system clock to SYS_FREQUENCY
|
||||
SystemCoreClock = SYS_FREQUENCY; // Update SystemCoreClock global var
|
||||
SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
|
||||
// rng_init(); // TRNG is part of ELS and there is no info on that
|
||||
|
||||
uart_init(UART_DEBUG, 115200); // Initialise UART
|
||||
gpio_output(LED1); // Initialise LED1
|
||||
gpio_write(LED1, 1);
|
||||
gpio_output(LED2); // Initialise LED2
|
||||
gpio_write(LED2, 1);
|
||||
gpio_output(LED3); // Initialise LED3
|
||||
gpio_write(LED3, 1);
|
||||
ethernet_init(); // Initialise Ethernet pins
|
||||
}
|
||||
|
||||
#if defined(__ARMCC_VERSION)
|
||||
// Keil specific - implement IO printf redirection
|
||||
int fputc(int c, FILE *stream) {
|
||||
if (stream == stdout || stream == stderr) uart_write_byte(UART_DEBUG, c);
|
||||
return c;
|
||||
}
|
||||
#elif defined(__GNUC__)
|
||||
// ARM GCC specific. ARM GCC is shipped with Newlib C library.
|
||||
// Implement newlib syscalls:
|
||||
// _sbrk() for malloc
|
||||
// _write() for printf redirection
|
||||
// the rest are just stubs
|
||||
#include <sys/stat.h> // For _fstat()
|
||||
|
||||
#if !defined(__MCUXPRESSO)
|
||||
uint32_t SystemCoreClock;
|
||||
// evaluate your use of Secure/non-Secure and modify accordingly
|
||||
void SystemInit(void) { // Called automatically by startup code
|
||||
SCB->CPACR |=
|
||||
#if 0
|
||||
(3UL << 0 * 2) | (3UL << 1 * 2) | // Enable PowerQuad (CPO/CP1)
|
||||
#endif
|
||||
(3UL << 10 * 2) | (3UL << 11 * 2); // Enable FPU
|
||||
__DSB();
|
||||
__ISB();
|
||||
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; // enable LPCAC
|
||||
// Read TRM 36.1 and decide whether you really want to enable aGDET and dGDET
|
||||
#if 1
|
||||
// Disable aGDET and dGDET
|
||||
ITRC0->OUT_SEL[4][0] =
|
||||
(ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) |
|
||||
(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
|
||||
ITRC0->OUT_SEL[4][1] =
|
||||
(ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) |
|
||||
(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2));
|
||||
SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK;
|
||||
SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK;
|
||||
SPC0->GLITCH_DETECT_SC = 0x3C;
|
||||
SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK;
|
||||
ITRC0->OUT_SEL[4][0] =
|
||||
(ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) |
|
||||
(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
|
||||
ITRC0->OUT_SEL[4][1] =
|
||||
(ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) |
|
||||
(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2));
|
||||
GDET0->GDET_ENABLE1 = 0;
|
||||
GDET1->GDET_ENABLE1 = 0;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
int _fstat(int fd, struct stat *st) {
|
||||
(void) fd, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if !defined(__MCUXPRESSO)
|
||||
extern unsigned char _end[]; // End of data section, start of heap. See link.ld
|
||||
static unsigned char *s_current_heap_end = _end;
|
||||
|
||||
size_t hal_ram_used(void) {
|
||||
return (size_t) (s_current_heap_end - _end);
|
||||
}
|
||||
|
||||
size_t hal_ram_free(void) {
|
||||
unsigned char endofstack;
|
||||
return (size_t) (&endofstack - s_current_heap_end);
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
unsigned char *prev_heap;
|
||||
unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
|
||||
prev_heap = s_current_heap_end;
|
||||
// Check how much space we got from the heap end to the stack end
|
||||
if (s_current_heap_end + incr > heap_end) return (void *) -1;
|
||||
s_current_heap_end += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
#endif
|
||||
|
||||
int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int mkdir(const char *path, mode_t mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _init(void) {
|
||||
}
|
||||
#endif // __GNUC__
|
||||
@ -1,223 +0,0 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#define LED1 PIN(0, 10)
|
||||
#define LED2 PIN(0, 27)
|
||||
#define LED3 PIN(1, 2)
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG LPUART4
|
||||
#endif
|
||||
|
||||
#include "MCXN947_cm33_core0.h"
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
|
||||
#define PIN(bank, num) ((bank << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
void hal_init(void);
|
||||
size_t hal_ram_free(void);
|
||||
size_t hal_ram_used(void);
|
||||
|
||||
static inline void spin(volatile uint32_t count) {
|
||||
while (count--) (void) 0;
|
||||
}
|
||||
|
||||
#define SYS_FREQUENCY 150000000UL
|
||||
|
||||
enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT };
|
||||
enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { GPIO_SPEED_LOW, GPIO_SPEED_HIGH };
|
||||
enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP };
|
||||
static inline GPIO_Type *gpio_bank(uint16_t pin) {
|
||||
static GPIO_Type *const g[] = GPIO_BASE_PTRS;
|
||||
return g[PINBANK(pin)];
|
||||
}
|
||||
|
||||
static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull, uint8_t af) {
|
||||
static PORT_Type *const p[] = PORT_BASE_PTRS;
|
||||
PORT_Type *port = p[PINBANK(pin)];
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
bool dopull = pull > 0;
|
||||
if (dopull) --pull;
|
||||
if (gpio != GPIO5) {
|
||||
SYSCON->AHBCLKCTRL0 |=
|
||||
(1 << (SYSCON_AHBCLKCTRL0_GPIO0_SHIFT + PINBANK(pin))) |
|
||||
(1 << (SYSCON_AHBCLKCTRL0_PORT0_SHIFT + PINBANK(pin)));
|
||||
};
|
||||
port->PCR[PINNO(pin)] = PORT_PCR_IBE(1) | PORT_PCR_MUX(af) | PORT_PCR_DSE(1) |
|
||||
PORT_PCR_ODE(type) |
|
||||
PORT_PCR_SRE(speed != GPIO_SPEED_HIGH) |
|
||||
PORT_PCR_PE(dopull) | PORT_PCR_PS(pull);
|
||||
gpio->ICR[PINNO(pin)] = GPIO_ICR_ISF_MASK;
|
||||
if (mode == GPIO_MODE_INPUT) {
|
||||
gpio->PDDR &= ~mask;
|
||||
} else {
|
||||
gpio->PDDR |= mask;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void gpio_input(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
|
||||
GPIO_PULL_NONE, 0);
|
||||
}
|
||||
static inline void gpio_output(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
|
||||
GPIO_PULL_NONE, 0);
|
||||
}
|
||||
|
||||
static inline bool gpio_read(uint16_t pin) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
return gpio->PDR[PINNO(pin)];
|
||||
}
|
||||
|
||||
static inline void gpio_write(uint16_t pin, bool value) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
if (value) {
|
||||
gpio->PDR[PINNO(pin)] = 1;
|
||||
} else {
|
||||
gpio->PDR[PINNO(pin)] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void gpio_toggle(uint16_t pin) {
|
||||
GPIO_Type *gpio = gpio_bank(pin);
|
||||
uint32_t mask = (uint32_t) BIT(PINNO(pin));
|
||||
gpio->PTOR = mask;
|
||||
}
|
||||
|
||||
// MCU-Link UART (P1_9/8; FC4_P1/0)
|
||||
// Arduino J1_2/4 UART (P4_3/2; FC2_P3/2)
|
||||
// 33.3.23 LP_FLEXCOMM clocking
|
||||
// 66.2.4 LP_FLEXCOMM init
|
||||
// 66.5 LPUART
|
||||
static inline void uart_init(LPUART_Type *uart, unsigned long baud) {
|
||||
static LP_FLEXCOMM_Type *const f[] = LP_FLEXCOMM_BASE_PTRS;
|
||||
uint8_t af = 2, fc = 0; // Alternate function, FlexComm instance
|
||||
uint16_t pr = 0, pt = 0; // pins
|
||||
uint32_t freq = 12000000; // fro_12_m
|
||||
if (uart == LPUART2) fc = 2, pt = PIN(4, 3), pr = PIN(4, 2);
|
||||
if (uart == LPUART4) fc = 4, pt = PIN(1, 9), pr = PIN(1, 8);
|
||||
|
||||
SYSCON->AHBCLKCTRL1 |= (1 << (SYSCON_AHBCLKCTRL1_FC0_SHIFT + fc));
|
||||
SYSCON->PRESETCTRL1 |= (1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc));
|
||||
SYSCON->PRESETCTRL1 &= ~(1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc));
|
||||
SYSCON->FCCLKSEL[fc] = SYSCON_FCCLKSEL_SEL(2); // clock from FRO_12M / 1
|
||||
SYSCON->FLEXCOMMCLKDIV[fc] = SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(0);
|
||||
LP_FLEXCOMM_Type *flexcomm = f[fc];
|
||||
flexcomm->PSELID = LP_FLEXCOMM_PSELID_PERSEL(1); // configure as UART
|
||||
gpio_init(pt, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
|
||||
GPIO_PULL_UP, af);
|
||||
gpio_init(pr, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
|
||||
GPIO_PULL_UP, af);
|
||||
|
||||
uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
|
||||
uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
|
||||
// use a weird oversample ratio of 26x to fit specs, standard 16x won't do
|
||||
CLRSET(uart->BAUD,
|
||||
LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK,
|
||||
LPUART_BAUD_OSR(26 - 1) | LPUART_BAUD_SBR(freq / (26 * baud)));
|
||||
CLRSET(uart->CTRL,
|
||||
LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
|
||||
LPUART_CTRL_IDLECFG_MASK,
|
||||
LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) |
|
||||
LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit
|
||||
uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
|
||||
}
|
||||
|
||||
static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
|
||||
uart->DATA = byte;
|
||||
while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1);
|
||||
}
|
||||
static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
|
||||
static inline void rng_init(void) {
|
||||
}
|
||||
static inline uint32_t rng_read(void) {
|
||||
return 42;
|
||||
}
|
||||
|
||||
// - PHY and MAC clocked via a 50MHz oscillator, P1_4 (ENET0_TXCLK)
|
||||
// - 33.3.30 ENET clocking
|
||||
// - SMI clocked from AHB module clock (CSR)
|
||||
// - PHY RST connected to P5_8
|
||||
// - PHY RXD0,1,DV = 1 on RST enable autonegotiation, no hw pull-ups
|
||||
static inline void ethernet_init(void) {
|
||||
// '0' in clk_rmii, set for RMII mode
|
||||
SYSCON->ENETRMIICLKSEL = SYSCON_ENETRMIICLKSEL_SEL(0);
|
||||
SYSCON->ENETRMIICLKDIV = SYSCON_ENETRMIICLKDIV_DIV(0);
|
||||
SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_ENET_MASK; // enable bus clk
|
||||
SYSCON0->PRESETCTRL2 = SYSCON_PRESETCTRL2_ENET_RST_MASK; // reset MAC
|
||||
SYSCON0->PRESETCTRL2 &= ~SYSCON_PRESETCTRL2_ENET_RST_MASK; // then set RMII
|
||||
SYSCON0->ENET_PHY_INTF_SEL |= SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_MASK;
|
||||
gpio_init(PIN(5, 8), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW,
|
||||
GPIO_PULL_NONE, 0); // set P5_8 as GPIO (PHY \RST)
|
||||
gpio_write(PIN(5, 8), 0); // reset PHY
|
||||
gpio_init(PIN(1, 4), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 9); // set P1_4 as ENET0_TXCLK
|
||||
gpio_init(PIN(1, 5), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 9); // set P1_5 as ENET0_TXEN
|
||||
gpio_init(PIN(1, 6), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 9); // set P1_6 as ENET0_TXD0
|
||||
gpio_init(PIN(1, 7), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 9); // set P1_7 as ENET0_TXD1
|
||||
gpio_init(PIN(1, 13), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_UP, 9); // set P1_13 as ENET0_RXDV
|
||||
gpio_init(PIN(1, 14), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_UP, 9); // set P1_14 as ENET0_RXD0
|
||||
gpio_init(PIN(1, 15), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_UP, 9); // set P1_15 as ENET0_RXD1
|
||||
gpio_init(PIN(1, 20), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 9); // set P1_20 as ENET0_MDC
|
||||
gpio_init(PIN(1, 21), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 9); // set P1_21 as ENET0_MDIO
|
||||
spin(10000); // keep PHY RST low for a while
|
||||
gpio_write(PIN(5, 8), 1); // deassert RST
|
||||
NVIC_EnableIRQ(ETHERNET_IRQn); // Setup Ethernet IRQ handler
|
||||
}
|
||||
|
||||
#include "fsl_clock.h"
|
||||
#include "fsl_spc.h"
|
||||
|
||||
// 33.2 Figure 127 SCG main clock
|
||||
static inline void clock_init(void) {
|
||||
SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_SCG_MASK; // enable SCG clk
|
||||
CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(2)); // clock main_clock
|
||||
spc_active_mode_dcdc_option_t dcdc = {
|
||||
.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
|
||||
.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength};
|
||||
SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdc); // Set DCDC to 1.2 V
|
||||
spc_active_mode_core_ldo_option_t ldo = {
|
||||
.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
|
||||
.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength};
|
||||
SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo); // Set LDO_CORE to 1.2 V
|
||||
CLRSET(FMU0->FCTRL, FMU_FCTRL_RWSC_MASK, FMU_FCTRL_RWSC(3)); // Set Flash WS
|
||||
spc_sram_voltage_config_t sram = {.operateVoltage = kSPC_sramOperateAt1P2V,
|
||||
.requestVoltageUpdate = true};
|
||||
SPC_SetSRAMOperateVoltage(SPC0, &sram); // Set SRAM timing for 1.2V
|
||||
CLOCK_SetupFROHFClocking(48000000U); // Enable FRO HF
|
||||
const pll_setup_t pll0 = {.pllctrl = SCG_APLLCTRL_SOURCE(1U) |
|
||||
SCG_APLLCTRL_SELI(27U) |
|
||||
SCG_APLLCTRL_SELP(13U),
|
||||
.pllndiv = SCG_APLLNDIV_NDIV(8U),
|
||||
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
|
||||
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
|
||||
.pllRate = 150000000U};
|
||||
CLOCK_SetPLL0Freq(&pll0); // Setup PLL0 (APLL),
|
||||
CLOCK_SetPll0MonitorMode(0); // disable monitor mode
|
||||
CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(5)); // clock main_clock
|
||||
SYSCON->AHBCLKDIV = SYSCON_AHBCLKDIV_DIV(0); // /1
|
||||
}
|
||||
@ -1,62 +0,0 @@
|
||||
/*
|
||||
* Copyright 2016-2024 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file MCXN947_Project.c
|
||||
* @brief Application entry point.
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include "board.h"
|
||||
#include "peripherals.h"
|
||||
#include "pin_mux.h"
|
||||
#include "clock_config.h"
|
||||
#include "MCXN947_cm33_core0.h"
|
||||
#include "fsl_debug_console.h"
|
||||
/* TODO: insert other include files here. */
|
||||
#include "hal.h"
|
||||
#include "mongoose.h"
|
||||
#include "net.h"
|
||||
|
||||
/* TODO: insert other definitions and declarations here. */
|
||||
#define BLINK_PERIOD_MS 1000
|
||||
|
||||
static void timer_fn(void *arg) {
|
||||
gpio_toggle(LED1); // Blink LED
|
||||
(void) arg; // Unused
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Application entry point.
|
||||
*/
|
||||
int main(void) {
|
||||
|
||||
/* Init board hardware. */
|
||||
BOARD_InitBootPins();
|
||||
BOARD_InitBootClocks();
|
||||
BOARD_InitBootPeripherals();
|
||||
#ifndef BOARD_INIT_DEBUG_CONSOLE_PERIPHERAL
|
||||
/* Init FSL debug console. */
|
||||
BOARD_InitDebugConsole();
|
||||
#endif
|
||||
|
||||
struct mg_mgr mgr; // Mongoose event manager
|
||||
|
||||
hal_init(); // Cross-platform hardware init
|
||||
|
||||
mg_mgr_init(&mgr); // Initialise it
|
||||
mg_log_set(MG_LL_DEBUG); // Set log level to debug
|
||||
mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mgr);
|
||||
|
||||
MG_INFO(("Initialising application..."));
|
||||
web_init(&mgr);
|
||||
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1 +0,0 @@
|
||||
../../../../mongoose.c
|
||||
@ -1 +0,0 @@
|
||||
../../../../mongoose.h
|
||||
@ -1,25 +0,0 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_NEWLIB
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_DRIVER_MCXN 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
//#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
|
||||
// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
|
||||
// By default, those are set to zero, meaning that DHCP is used
|
||||
//
|
||||
// #define MG_TCPIP_IP MG_IPV4(192, 168, 1, 10)
|
||||
// #define MG_TCPIP_GW MG_IPV4(192, 168, 1, 1)
|
||||
// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)
|
||||
|
||||
// Set custom MAC address. By default, it is randomly generated
|
||||
// Using a build-time constant:
|
||||
// #define MG_SET_MAC_ADDRESS(mac) do { uint8_t buf_[6] = {2,3,4,5,6,7}; memmove(mac, buf_, sizeof(buf_)); } while (0)
|
||||
//
|
||||
// Using custom function:
|
||||
// extern void my_function(unsigned char *mac);
|
||||
// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)
|
||||
@ -1 +0,0 @@
|
||||
../../../../examples/device-dashboard/net.c
|
||||
@ -1 +0,0 @@
|
||||
../../../../examples/device-dashboard/net.h
|
||||
@ -1 +0,0 @@
|
||||
../../../../examples/device-dashboard/packed_fs.c
|
||||
@ -1,48 +0,0 @@
|
||||
//*****************************************************************************
|
||||
// boot_multicore_slave.c
|
||||
//
|
||||
// Provides functions to allow booting of secondary core in multicore system
|
||||
//
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Copyright 2016-2022 NXP
|
||||
// All rights reserved.
|
||||
//
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
//*****************************************************************************
|
||||
|
||||
#if defined(__MULTICORE_MASTER)
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define SYSCON_BASE ((uint32_t)0x50000000)
|
||||
|
||||
#define CPBOOT (((volatile uint32_t *)(SYSCON_BASE + 0x804)))
|
||||
#define CPUCTRL (((volatile uint32_t *)(SYSCON_BASE + 0x800)))
|
||||
|
||||
#define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16))
|
||||
#define CORE1_CLK_ENA (1 << 3)
|
||||
#define CORE1_RESET_ENA (1 << 5)
|
||||
|
||||
extern uint8_t __core_m33slave_START__;
|
||||
|
||||
void boot_multicore_slave(void)
|
||||
{
|
||||
volatile uint32_t *u32REG, u32Val;
|
||||
|
||||
unsigned int *slavevectortable_ptr = (unsigned int *)&__core_m33slave_START__;
|
||||
|
||||
// Set CPU1 boot address in SYSCON->CPBoot
|
||||
*CPBOOT = (uint32_t)slavevectortable_ptr;
|
||||
|
||||
// Read SYSCON->CPUCTRL and set key value in bits 31:16
|
||||
u32REG = (uint32_t *)CPUCTRL;
|
||||
u32Val = *u32REG | CPUCTRL_KEY;
|
||||
|
||||
// Enable CPU1 clock and reset in SYSCON->CPUCTRL
|
||||
*u32REG = u32Val | CORE1_CLK_ENA | CORE1_RESET_ENA;
|
||||
|
||||
// Clear CPU1 reset in SYSCON->CPUCTRL
|
||||
*u32REG = (u32Val | CORE1_CLK_ENA) & (~CORE1_RESET_ENA);
|
||||
}
|
||||
#endif // defined (__MULTICORE_MASTER)
|
||||
@ -1,26 +0,0 @@
|
||||
//*****************************************************************************
|
||||
// boot_multicore_slave.h
|
||||
//
|
||||
// Header for functions used for booting of secondary core in multicore system
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Copyright 2016-2022 NXP
|
||||
// All rights reserved.
|
||||
//
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef BOOT_MULTICORE_SLAVE_H_
|
||||
#define BOOT_MULTICORE_SLAVE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void boot_multicore_slave(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* BOOT_MULTICORE_SLAVE_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,66 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_debug_console.h"
|
||||
|
||||
#ifndef NDEBUG
|
||||
#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__))
|
||||
void __aeabi_assert(const char *failedExpr, const char *file, int line)
|
||||
{
|
||||
#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE
|
||||
PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
|
||||
#else
|
||||
(void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
|
||||
#endif
|
||||
|
||||
for (;;)
|
||||
{
|
||||
__BKPT(0);
|
||||
}
|
||||
}
|
||||
#elif (defined(__GNUC__))
|
||||
#if defined(__REDLIB__)
|
||||
void __assertion_failed(char *failedExpr)
|
||||
{
|
||||
(void)PRINTF("ASSERT ERROR \" %s \n", failedExpr);
|
||||
for (;;)
|
||||
{
|
||||
__BKPT(0);
|
||||
}
|
||||
}
|
||||
#else
|
||||
void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
|
||||
{
|
||||
(void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line,
|
||||
func);
|
||||
for (;;)
|
||||
{
|
||||
__BKPT(0);
|
||||
}
|
||||
}
|
||||
#endif /* defined(__REDLIB__) */
|
||||
#else /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */
|
||||
|
||||
#if (defined(__DSC__) && defined(__CW__))
|
||||
|
||||
void __msl_assertion_failed(char const *failedExpr, char const *file, char const *func, int line)
|
||||
{
|
||||
PRINTF("\r\nASSERT ERROR\r\n");
|
||||
PRINTF(" File : %s\r\n", file);
|
||||
PRINTF(" Function : %s\r\n", func); /*compiler not support func name yet*/
|
||||
PRINTF(" Line : %u\r\n", (uint32_t)line);
|
||||
PRINTF(" failedExpr: %s\r\n", failedExpr);
|
||||
asm(DEBUGHLT);
|
||||
}
|
||||
|
||||
#endif /* (defined(__DSC__) && defined (__CW__)) */
|
||||
|
||||
#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */
|
||||
#endif /* NDEBUG */
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,317 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018, 2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Debug console shall provide input and output functions to scan and print formatted data.
|
||||
* o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
|
||||
* - [flags] :'-', '+', '#', ' ', '0'
|
||||
* - [width]: number (0,1...)
|
||||
* - [.precision]: number (0,1...)
|
||||
* - [length]: do not support
|
||||
* - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
|
||||
* o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
|
||||
* - [*]: is supported.
|
||||
* - [width]: number (0,1...)
|
||||
* - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
|
||||
* - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
|
||||
*/
|
||||
|
||||
#ifndef _FSL_DEBUGCONSOLE_H_
|
||||
#define _FSL_DEBUGCONSOLE_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_component_serial_manager.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup debugconsole
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
extern serial_handle_t g_serialHandle; /*!< serial manager handle */
|
||||
|
||||
/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
|
||||
#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
|
||||
#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */
|
||||
#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */
|
||||
|
||||
/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support
|
||||
* to be redefined in project setting.
|
||||
*/
|
||||
#ifndef SDK_DEBUGCONSOLE
|
||||
#define SDK_DEBUGCONSOLE DEBUGCONSOLE_REDIRECT_TO_SDK
|
||||
#endif
|
||||
|
||||
#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
|
||||
#include <stdio.h>
|
||||
#else
|
||||
#include <stdarg.h>
|
||||
#endif
|
||||
|
||||
/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
|
||||
*
|
||||
* if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
|
||||
* if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.
|
||||
* if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.
|
||||
*/
|
||||
#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
|
||||
static inline int DbgConsole_Disabled(void)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
#define PRINTF(...) DbgConsole_Disabled()
|
||||
#define SCANF(...) DbgConsole_Disabled()
|
||||
#define PUTCHAR(...) DbgConsole_Disabled()
|
||||
#define GETCHAR() DbgConsole_Disabled()
|
||||
#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
|
||||
#define PRINTF DbgConsole_Printf
|
||||
#define SCANF DbgConsole_Scanf
|
||||
#define PUTCHAR DbgConsole_Putchar
|
||||
#define GETCHAR DbgConsole_Getchar
|
||||
#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \
|
||||
*/
|
||||
#define PRINTF printf
|
||||
#define SCANF scanf
|
||||
#define PUTCHAR putchar
|
||||
#define GETCHAR getchar
|
||||
#endif /* SDK_DEBUGCONSOLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*! @name Initialization*/
|
||||
/* @{ */
|
||||
|
||||
#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
|
||||
/*!
|
||||
* @brief Initializes the peripheral used for debug messages.
|
||||
*
|
||||
* Call this function to enable debug log messages to be output via the specified peripheral
|
||||
* initialized by the serial manager module.
|
||||
* After this function has returned, stdout and stdin are connected to the selected peripheral.
|
||||
*
|
||||
* @param instance The instance of the module.If the device is kSerialPort_Uart,
|
||||
* the instance is UART peripheral instance. The UART hardware peripheral
|
||||
* type is determined by UART adapter. For example, if the instance is 1,
|
||||
* if the lpuart_adapter.c is added to the current project, the UART periheral
|
||||
* is LPUART1.
|
||||
* If the uart_adapter.c is added to the current project, the UART periheral
|
||||
* is UART1.
|
||||
* @param baudRate The desired baud rate in bits per second.
|
||||
* @param device Low level device type for the debug console, can be one of the following.
|
||||
* @arg kSerialPort_Uart,
|
||||
* @arg kSerialPort_UsbCdc
|
||||
* @param clkSrcFreq Frequency of peripheral source clock.
|
||||
*
|
||||
* @return Indicates whether initialization was successful or not.
|
||||
* @retval kStatus_Success Execution successfully
|
||||
*/
|
||||
status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
|
||||
|
||||
/*!
|
||||
* @brief De-initializes the peripheral used for debug messages.
|
||||
*
|
||||
* Call this function to disable debug log messages to be output via the specified peripheral
|
||||
* initialized by the serial manager module.
|
||||
*
|
||||
* @return Indicates whether de-initialization was successful or not.
|
||||
*/
|
||||
status_t DbgConsole_Deinit(void);
|
||||
/*!
|
||||
* @brief Prepares to enter low power consumption.
|
||||
*
|
||||
* This function is used to prepare to enter low power consumption.
|
||||
*
|
||||
* @return Indicates whether de-initialization was successful or not.
|
||||
*/
|
||||
status_t DbgConsole_EnterLowpower(void);
|
||||
|
||||
/*!
|
||||
* @brief Restores from low power consumption.
|
||||
*
|
||||
* This function is used to restore from low power consumption.
|
||||
*
|
||||
* @return Indicates whether de-initialization was successful or not.
|
||||
*/
|
||||
status_t DbgConsole_ExitLowpower(void);
|
||||
|
||||
#else
|
||||
/*!
|
||||
* Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
|
||||
* SDK_DEBUGCONSOLE_UART is not defined.
|
||||
*/
|
||||
static inline status_t DbgConsole_Init(uint8_t instance,
|
||||
uint32_t baudRate,
|
||||
serial_port_type_t device,
|
||||
uint32_t clkSrcFreq)
|
||||
{
|
||||
(void)instance;
|
||||
(void)baudRate;
|
||||
(void)device;
|
||||
(void)clkSrcFreq;
|
||||
return (status_t)kStatus_Fail;
|
||||
}
|
||||
/*!
|
||||
* Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
|
||||
* SDK_DEBUGCONSOLE_UART is not defined.
|
||||
*/
|
||||
static inline status_t DbgConsole_Deinit(void)
|
||||
{
|
||||
return (status_t)kStatus_Fail;
|
||||
}
|
||||
|
||||
/*!
|
||||
* Use an error to replace the DbgConsole_EnterLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
|
||||
* SDK_DEBUGCONSOLE_UART is not defined.
|
||||
*/
|
||||
static inline status_t DbgConsole_EnterLowpower(void)
|
||||
{
|
||||
return (status_t)kStatus_Fail;
|
||||
}
|
||||
|
||||
/*!
|
||||
* Use an error to replace the DbgConsole_ExitLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
|
||||
* SDK_DEBUGCONSOLE_UART is not defined.
|
||||
*/
|
||||
static inline status_t DbgConsole_ExitLowpower(void)
|
||||
{
|
||||
return (status_t)kStatus_Fail;
|
||||
}
|
||||
|
||||
#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */
|
||||
|
||||
#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK))
|
||||
/*!
|
||||
* @brief Writes formatted output to the standard output stream.
|
||||
*
|
||||
* Call this function to write a formatted output to the standard output stream.
|
||||
*
|
||||
* @param fmt_s Format control string.
|
||||
* @return Returns the number of characters printed or a negative value if an error occurs.
|
||||
*/
|
||||
int DbgConsole_Printf(const char *fmt_s, ...);
|
||||
|
||||
/*!
|
||||
* @brief Writes formatted output to the standard output stream.
|
||||
*
|
||||
* Call this function to write a formatted output to the standard output stream.
|
||||
*
|
||||
* @param fmt_s Format control string.
|
||||
* @param formatStringArg Format arguments.
|
||||
* @return Returns the number of characters printed or a negative value if an error occurs.
|
||||
*/
|
||||
int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg);
|
||||
|
||||
/*!
|
||||
* @brief Writes a character to stdout.
|
||||
*
|
||||
* Call this function to write a character to stdout.
|
||||
*
|
||||
* @param ch Character to be written.
|
||||
* @return Returns the character written.
|
||||
*/
|
||||
int DbgConsole_Putchar(int ch);
|
||||
|
||||
/*!
|
||||
* @brief Reads formatted data from the standard input stream.
|
||||
*
|
||||
* Call this function to read formatted data from the standard input stream.
|
||||
*
|
||||
* @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
|
||||
* other tasks will not be scheduled), the function cannot be used when the
|
||||
* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
|
||||
* And an error is returned when the function called in this case. The suggestion
|
||||
* is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
|
||||
*
|
||||
* @param fmt_s Format control string.
|
||||
* @return Returns the number of fields successfully converted and assigned.
|
||||
*/
|
||||
int DbgConsole_Scanf(char *fmt_s, ...);
|
||||
|
||||
/*!
|
||||
* @brief Reads a character from standard input.
|
||||
*
|
||||
* Call this function to read a character from standard input.
|
||||
*
|
||||
* @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
|
||||
* other tasks will not be scheduled), the function cannot be used when the
|
||||
* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
|
||||
* And an error is returned when the function called in this case. The suggestion
|
||||
* is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
|
||||
*
|
||||
* @return Returns the character read.
|
||||
*/
|
||||
int DbgConsole_Getchar(void);
|
||||
|
||||
/*!
|
||||
* @brief Writes formatted output to the standard output stream with the blocking mode.
|
||||
*
|
||||
* Call this function to write a formatted output to the standard output stream with the blocking mode.
|
||||
* The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set
|
||||
* or not.
|
||||
* The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set.
|
||||
*
|
||||
* @param fmt_s Format control string.
|
||||
* @return Returns the number of characters printed or a negative value if an error occurs.
|
||||
*/
|
||||
int DbgConsole_BlockingPrintf(const char *fmt_s, ...);
|
||||
|
||||
/*!
|
||||
* @brief Writes formatted output to the standard output stream with the blocking mode.
|
||||
*
|
||||
* Call this function to write a formatted output to the standard output stream with the blocking mode.
|
||||
* The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set
|
||||
* or not.
|
||||
* The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set.
|
||||
*
|
||||
* @param fmt_s Format control string.
|
||||
* @param formatStringArg Format arguments.
|
||||
* @return Returns the number of characters printed or a negative value if an error occurs.
|
||||
*/
|
||||
int DbgConsole_BlockingVprintf(const char *fmt_s, va_list formatStringArg);
|
||||
|
||||
/*!
|
||||
* @brief Debug console flush.
|
||||
*
|
||||
* Call this function to wait the tx buffer empty.
|
||||
* If interrupt transfer is using, make sure the global IRQ is enable before call this function
|
||||
* This function should be called when
|
||||
* 1, before enter power down mode
|
||||
* 2, log is required to print to terminal immediately
|
||||
* @return Indicates whether wait idle was successful or not.
|
||||
*/
|
||||
status_t DbgConsole_Flush(void);
|
||||
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
/*!
|
||||
* @brief Debug console try to get char
|
||||
* This function provides a API which will not block current task, if character is
|
||||
* available return it, otherwise return fail.
|
||||
* @param ch the address of char to receive
|
||||
* @return Indicates get char was successful or not.
|
||||
*/
|
||||
status_t DbgConsole_TryGetchar(char *ch);
|
||||
#endif
|
||||
|
||||
#endif /* SDK_DEBUGCONSOLE */
|
||||
|
||||
/*! @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_DEBUGCONSOLE_H_ */
|
||||
@ -1,149 +0,0 @@
|
||||
/*
|
||||
* Copyright 2017 - 2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
|
||||
#define _FSL_DEBUG_CONSOLE_CONF_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup debug_console_config
|
||||
* @ingroup debugconsole
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************Debug console configuration********************/
|
||||
|
||||
/*! @brief If Non-blocking mode is needed, please define it at project setting,
|
||||
* otherwise blocking mode is the default transfer mode.
|
||||
* Warning: If you want to use non-blocking transfer,please make sure the corresponding
|
||||
* IO interrupt is enable, otherwise there is no output.
|
||||
* And non-blocking is combine with buffer, no matter bare-metal or rtos.
|
||||
* Below shows how to configure in your project if you want to use non-blocking mode.
|
||||
* For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".
|
||||
* For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".
|
||||
* For ARMGCC, open CmakeLists.txt and add the following lines,
|
||||
* "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.
|
||||
* "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.
|
||||
* For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C
|
||||
* Complier->Preprocessor".
|
||||
*
|
||||
*/
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
|
||||
* when
|
||||
* non-blocking transfer is using,
|
||||
* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
|
||||
* If it is configured too small, log maybe missed , because the log will not be
|
||||
* buffered if the buffer is full, and the print will return immediately with -1.
|
||||
* And this value should be multiple of 4 to meet memory alignment.
|
||||
*
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
|
||||
#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
|
||||
#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
|
||||
|
||||
/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
|
||||
* non-blocking transfer is using,
|
||||
* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
|
||||
* If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
|
||||
* And this value should be multiple of 4 to meet memory alignment.
|
||||
*
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
|
||||
#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)
|
||||
#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
|
||||
|
||||
/*!@brief Whether enable the reliable TX function
|
||||
* If the macro is zero, the reliable TX function of the debug console is disabled.
|
||||
* When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE
|
||||
#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)
|
||||
#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
|
||||
|
||||
#else
|
||||
#define DEBUG_CONSOLE_TRANSFER_BLOCKING
|
||||
#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
|
||||
|
||||
/*!@brief Whether enable the RX function
|
||||
* If the macro is zero, the receive function of the debug console is disabled.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_RX_ENABLE
|
||||
#define DEBUG_CONSOLE_RX_ENABLE (1U)
|
||||
#endif /* DEBUG_CONSOLE_RX_ENABLE */
|
||||
|
||||
/*!@brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
|
||||
* length can not bigger than this value.
|
||||
* This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
|
||||
* the buffer is too big and current task stack size not big enough.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
|
||||
#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
|
||||
#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
|
||||
|
||||
/*!@brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
|
||||
* length can not bigger than this value.
|
||||
* As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
|
||||
#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
|
||||
#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
|
||||
|
||||
/*! @brief Debug console synchronization
|
||||
* User should not change these macro for synchronization mode, but add the
|
||||
* corresponding synchronization mechanism per different software environment.
|
||||
* Such as, if another RTOS is used,
|
||||
* add:
|
||||
* \#define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
|
||||
* in this configuration file and implement the synchronization in fsl.log.c.
|
||||
*/
|
||||
/*! @brief synchronization for baremetal software */
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
|
||||
/*! @brief synchronization for freertos software */
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
|
||||
|
||||
/*! @brief RTOS synchronization mechanism disable
|
||||
* If not defined, default is enable, to avoid multitask log print mess.
|
||||
* If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
|
||||
* If synchronization is disabled, log maybe messed on terminal.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
#ifdef SDK_OS_FREE_RTOS
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
|
||||
#else
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
|
||||
#endif /* SDK_OS_FREE_RTOS */
|
||||
#else
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
|
||||
#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
|
||||
#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
|
||||
|
||||
/*! @brief echo function support
|
||||
* If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
|
||||
* at your project setting.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_ENABLE_ECHO
|
||||
#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
|
||||
#else
|
||||
#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
|
||||
#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
|
||||
|
||||
/*********************************************************************/
|
||||
|
||||
/***************Debug console other configuration*********************/
|
||||
|
||||
/*! @brief Definition to select virtual com(USB CDC) as the debug console. */
|
||||
#ifndef BOARD_USE_VIRTUALCOM
|
||||
#define BOARD_USE_VIRTUALCOM 0U
|
||||
#endif
|
||||
/*******************************************************************/
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,129 +0,0 @@
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _FSL_STR_H
|
||||
#define _FSL_STR_H
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup debugconsole
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Definition to printf the float number. */
|
||||
#ifndef PRINTF_FLOAT_ENABLE
|
||||
#define PRINTF_FLOAT_ENABLE 0U
|
||||
#endif /* PRINTF_FLOAT_ENABLE */
|
||||
|
||||
/*! @brief Definition to scanf the float number. */
|
||||
#ifndef SCANF_FLOAT_ENABLE
|
||||
#define SCANF_FLOAT_ENABLE 0U
|
||||
#endif /* SCANF_FLOAT_ENABLE */
|
||||
|
||||
/*! @brief Definition to support advanced format specifier for printf. */
|
||||
#ifndef PRINTF_ADVANCED_ENABLE
|
||||
#define PRINTF_ADVANCED_ENABLE 0U
|
||||
#endif /* PRINTF_ADVANCED_ENABLE */
|
||||
|
||||
/*! @brief Definition to support advanced format specifier for scanf. */
|
||||
#ifndef SCANF_ADVANCED_ENABLE
|
||||
#define SCANF_ADVANCED_ENABLE 0U
|
||||
#endif /* SCANF_ADVANCED_ENABLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
#if (defined(PRINTF_ADVANCED_ENABLE) && (PRINTF_ADVANCED_ENABLE > 0U))
|
||||
/*! @brief Specification modifier flags for printf. */
|
||||
enum _debugconsole_printf_flag
|
||||
{
|
||||
kPRINTF_Minus = 0x01U, /*!< Minus FLag. */
|
||||
kPRINTF_Plus = 0x02U, /*!< Plus Flag. */
|
||||
kPRINTF_Space = 0x04U, /*!< Space Flag. */
|
||||
kPRINTF_Zero = 0x08U, /*!< Zero Flag. */
|
||||
kPRINTF_Pound = 0x10U, /*!< Pound Flag. */
|
||||
kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */
|
||||
kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */
|
||||
kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */
|
||||
kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
|
||||
};
|
||||
#endif /* PRINTF_ADVANCED_ENABLE */
|
||||
|
||||
/*! @brief Specification modifier flags for scanf. */
|
||||
enum _debugconsole_scanf_flag
|
||||
{
|
||||
kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */
|
||||
kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */
|
||||
kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */
|
||||
kSCANF_DestString = 0x8U, /*!< Destination String FLag. */
|
||||
kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */
|
||||
kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */
|
||||
kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */
|
||||
kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
|
||||
#if (defined(SCANF_ADVANCED_ENABLE) && (SCANF_ADVANCED_ENABLE > 0U))
|
||||
kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */
|
||||
kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */
|
||||
kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */
|
||||
kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
|
||||
#endif /* SCANF_ADVANCED_ENABLE */
|
||||
#if (defined(SCANF_FLOAT_ENABLE) && (SCANF_FLOAT_ENABLE > 0))
|
||||
kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
|
||||
#endif /*PRINTF_FLOAT_ENABLE */
|
||||
kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*!
|
||||
* @brief A function pointer which is used when format printf log.
|
||||
*/
|
||||
typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
|
||||
|
||||
/*!
|
||||
* @brief This function outputs its parameters according to a formatted string.
|
||||
*
|
||||
* @note I/O is performed by calling given function pointer using following
|
||||
* (*func_ptr)(c);
|
||||
*
|
||||
* @param[in] fmt Format string for printf.
|
||||
* @param[in] ap Arguments to printf.
|
||||
* @param[in] buf pointer to the buffer
|
||||
* @param cb print callbck function pointer
|
||||
*
|
||||
* @return Number of characters to be print
|
||||
*/
|
||||
int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
|
||||
|
||||
/*!
|
||||
* @brief Converts an input line of ASCII characters based upon a provided
|
||||
* string format.
|
||||
*
|
||||
* @param[in] line_ptr The input line of ASCII data.
|
||||
* @param[in] format Format first points to the format string.
|
||||
* @param[in] args_ptr The list of parameters.
|
||||
*
|
||||
* @return Number of input items converted and assigned.
|
||||
* @retval IO_EOF When line_ptr is empty string "".
|
||||
*/
|
||||
int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_STR_H */
|
||||
@ -1,735 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
<cconfiguration id="com.crt.advproject.config.exe.debug.1992514917">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.1992514917" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.1992514917" name="Debug" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size "${BuildArtifactFileName}"; # arm-none-eabi-objcopy -v -O binary "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.bin" ; # checksum -p ${TargetChip} -d "${BuildArtifactFileBaseName}.bin"; ">
|
||||
<folderInfo id="com.crt.advproject.config.exe.debug.1992514917." name="/" resourcePath="">
|
||||
<toolChain id="com.crt.advproject.toolchain.exe.debug.806652998" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
|
||||
<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1969731363" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
|
||||
<builder buildPath="${workspace_loc:/frdm-mcxn947-xpresso-freertos-builtin}/Debug" id="com.crt.advproject.builder.exe.debug.700225415" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
|
||||
<tool id="com.crt.advproject.cpp.exe.debug.768837141" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug">
|
||||
<option id="com.crt.advproject.cpp.hdrlib.973640395" name="Library headers" superClass="com.crt.advproject.cpp.hdrlib" useByScannerDiscovery="false"/>
|
||||
<option id="com.crt.advproject.cpp.fpu.1073922403" name="Floating point" superClass="com.crt.advproject.cpp.fpu" useByScannerDiscovery="true" value="com.crt.advproject.cpp.fpu.fpv5sp.hard" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.cpp.arch.2106989233" name="Architecture" superClass="com.crt.advproject.cpp.arch" useByScannerDiscovery="true" value="com.crt.advproject.cpp.target.cm33" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.cpp.misc.dialect.533519572" name="Language standard" superClass="com.crt.advproject.cpp.misc.dialect" useByScannerDiscovery="true"/>
|
||||
<option id="gnu.cpp.compiler.option.dialect.flags.1473738793" name="Other dialect flags" superClass="gnu.cpp.compiler.option.dialect.flags" useByScannerDiscovery="true"/>
|
||||
<option id="gnu.cpp.compiler.option.preprocessor.nostdinc.131152477" name="Do not search system directories (-nostdinc)" superClass="gnu.cpp.compiler.option.preprocessor.nostdinc" useByScannerDiscovery="false"/>
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
<option id="com.crt.advproject.link.ecrp.202532127" name="Enhanced CRP" superClass="com.crt.advproject.link.ecrp"/>
|
||||
<option id="com.crt.advproject.link.gcc.hdrlib.1358111247" name="Library" superClass="com.crt.advproject.link.gcc.hdrlib" value="com.crt.advproject.gcc.link.hdrlib.newlibnano.nohost" valueType="enumerated"/>
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||||
<option id="com.crt.advproject.link.gcc.nanofloat.1098707676" name="Enable printf float " superClass="com.crt.advproject.link.gcc.nanofloat"/>
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||||
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|
||||
<option id="com.crt.advproject.link.toram.564447782" name="Link application to RAM" superClass="com.crt.advproject.link.toram"/>
|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
<option id="com.crt.advproject.link.nonsecureobject.1065261932" name="Secure Gateway Import Library" superClass="com.crt.advproject.link.nonsecureobject"/>
|
||||
<option id="com.crt.advproject.link.inimplib.321692015" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.inimplib"/>
|
||||
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|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
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|
||||
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|
||||
<tool id="com.crt.advproject.tool.debug.release.990517564" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.release">
|
||||
<option id="com.crt.advproject.miscellaneous.end_of_heap.1264230676" name="Last used address of the heap" superClass="com.crt.advproject.miscellaneous.end_of_heap"/>
|
||||
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|
||||
<option id="com.crt.advproject.miscellaneous.pvHeapLimit.129716228" name="Maximum extent of heap" superClass="com.crt.advproject.miscellaneous.pvHeapLimit"/>
|
||||
<option id="com.crt.advproject.debugger.security.nonsecureimageenable.60247837" name="Enable pre-programming of Non-Secure Image" superClass="com.crt.advproject.debugger.security.nonsecureimageenable"/>
|
||||
<option id="com.crt.advproject.debugger.security.nonsecureimage.1109530766" name="Non-Secure Project" superClass="com.crt.advproject.debugger.security.nonsecureimage"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="CMSIS"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="source"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="utilities"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="drivers"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="device"/>
|
||||
<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="board"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
<boardId>frdmmcxn947</boardId>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<chip>
|
||||
<name>MCXN947</name>
|
||||
<family>MCXN9XX</family>
|
||||
<vendor>NXP</vendor>
|
||||
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|
||||
<memory id="RAM" size="512" type="RAM"/>
|
||||
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|
||||
<memoryInstance derived_from="Flash" driver="MCXNxxx.cfx" edited="true" id="PROGRAM_FLASH1" location="0x100000" size="0x100000"/>
|
||||
<memoryInstance derived_from="RAM" edited="true" id="SRAM" location="0x20000000" size="0x60000"/>
|
||||
<memoryInstance derived_from="RAM" edited="true" id="SRAMX" location="0x4000000" size="0x18000"/>
|
||||
<memoryInstance derived_from="RAM" edited="true" id="SRAMH" location="0x20060000" size="0x8000"/>
|
||||
<memoryInstance derived_from="RAM" edited="true" id="USB_RAM" location="0x400ba000" size="0x1000"/>
|
||||
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|
||||
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|
||||
<name gcc_name="cortex-m33">Cortex-M33</name>
|
||||
<family>Cortex-M</family>
|
||||
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|
||||
<processor>
|
||||
<name gcc_name="cortex-m33-nodsp">Cortex-M33 (No DSP)</name>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
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|
||||
@ -1,27 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
@ -1,25 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
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||||
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|
||||
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|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="com.crt.advproject.GCCBuildCommandParser" keep-relative-paths="false" name="MCU GCC Build Output Parser" parameter="(arm-none-eabi-gcc)|(arm-none-eabi-[gc]\+\+)|(gcc)|([gc]\+\+)|(clang)" prefer-non-shared="true"/>
|
||||
<provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="883575258906360803" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
<configuration id="com.crt.advproject.config.exe.release.1380682132" name="Release">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
|
||||
<provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="889295433132188739" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
@ -1,2 +0,0 @@
|
||||
eclipse.preferences.version=1
|
||||
encoding/<project>=UTF-8
|
||||
@ -1,283 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,39 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.4
|
||||
* @date 23. July 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,352 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.3
|
||||
* @date 03. February 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,70 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
28
examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/Makefile
Normal file
28
examples/nxp/frdm-mcxn947-xpresso-freertos-builtin/Makefile
Normal file
@ -0,0 +1,28 @@
|
||||
BOARD = mcxn947
|
||||
IDE = MCUXpresso
|
||||
RTOS = FreeRTOS
|
||||
WIZARD_URL ?= http://mongoose.ws/wizard
|
||||
|
||||
TARGET ?= Debug
|
||||
DOCKER = docker run --rm -v $(CURDIR):/root -w /root
|
||||
IMAGE ?= scaprile/xpresso
|
||||
HEADLESS_BUILD = /usr/local/mcuxpressoide/ide/mcuxpressoide --launcher.suppressErrors -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild
|
||||
|
||||
all build example: firmware.axf
|
||||
|
||||
firmware.axf: wizard
|
||||
mkdir -p workspace
|
||||
PROJNAME=`xq -r .projectDescription.name wizard/.project` && \
|
||||
($(DOCKER) $(IMAGE) $(HEADLESS_BUILD) -data workspace -import wizard -cleanBuild $$PROJNAME/$(TARGET) || true) && \
|
||||
cp wizard/$(TARGET)/$$PROJNAME.axf firmware.axf
|
||||
|
||||
wizard:
|
||||
hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \
|
||||
&& curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip
|
||||
unzip wizard.zip
|
||||
cd wizard/source ; rm mongoose.[ch] ; cp -rL ../../../../../mongoose.[ch] .
|
||||
|
||||
|
||||
clean:
|
||||
sudo rm -rf firmware.* wizard* workspace mcuxpresso .cache .eclipse .p2
|
||||
|
||||
@ -0,0 +1 @@
|
||||
See [Wizard](https://mongoose.ws/wizard/#/output?board=f429&ide=CubeIDE&rtos=baremetal&file=README.md)
|
||||
@ -1,245 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_debug_console.h"
|
||||
#include "board.h"
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
#include "fsl_lpi2c.h"
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER
|
||||
#include "fsl_lpflexcomm.h"
|
||||
#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
|
||||
#include "fsl_spc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/* Initialize debug console. */
|
||||
void BOARD_InitDebugConsole(void)
|
||||
{
|
||||
/* attach 12 MHz clock to FLEXCOMM0 (debug console) */
|
||||
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
|
||||
|
||||
RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
|
||||
|
||||
uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
|
||||
|
||||
#if defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER
|
||||
LP_FLEXCOMM_Init(BOARD_DEBUG_UART_INSTANCE, LP_FLEXCOMM_PERIPH_LPUART);
|
||||
#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
|
||||
}
|
||||
|
||||
void BOARD_InitDebugConsole_Core1(void)
|
||||
{
|
||||
/* attach 12 MHz clock to FLEXCOMM1 (debug console) */
|
||||
// CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH_CORE1);
|
||||
|
||||
RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST_CORE1);
|
||||
|
||||
uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ_CORE1;
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE_CORE1, BOARD_DEBUG_UART_BAUDRATE_CORE1, BOARD_DEBUG_UART_TYPE_CORE1,
|
||||
uartClkSrcFreq);
|
||||
}
|
||||
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
|
||||
{
|
||||
lpi2c_master_config_t lpi2cConfig = {0};
|
||||
|
||||
/*
|
||||
* lpi2cConfig.debugEnable = false;
|
||||
* lpi2cConfig.ignoreAck = false;
|
||||
* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
|
||||
* lpi2cConfig.baudRate_Hz = 100000U;
|
||||
* lpi2cConfig.busIdleTimeout_ns = 0;
|
||||
* lpi2cConfig.pinLowTimeout_ns = 0;
|
||||
* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
|
||||
* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
|
||||
*/
|
||||
LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
|
||||
LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize)
|
||||
{
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Write;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = txBuff;
|
||||
xfer.dataSize = txBuffSize;
|
||||
|
||||
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize)
|
||||
{
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Read;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = rxBuff;
|
||||
xfer.dataSize = rxBuffSize;
|
||||
|
||||
return LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize)
|
||||
{
|
||||
status_t status;
|
||||
lpi2c_master_transfer_t xfer;
|
||||
|
||||
xfer.flags = kLPI2C_TransferDefaultFlag;
|
||||
xfer.slaveAddress = deviceAddress;
|
||||
xfer.direction = kLPI2C_Write;
|
||||
xfer.subaddress = subAddress;
|
||||
xfer.subaddressSize = subAddressSize;
|
||||
xfer.data = NULL;
|
||||
xfer.dataSize = 0;
|
||||
|
||||
status = LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
|
||||
if (kStatus_Success == status)
|
||||
{
|
||||
xfer.subaddressSize = 0;
|
||||
xfer.direction = kLPI2C_Read;
|
||||
xfer.data = rxBuff;
|
||||
xfer.dataSize = rxBuffSize;
|
||||
|
||||
status = LPI2C_MasterTransferBlocking(base, &xfer);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void BOARD_Accel_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
|
||||
{
|
||||
uint8_t data = (uint8_t)txBuff;
|
||||
|
||||
return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
|
||||
void BOARD_Codec_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
|
||||
void BOARD_Camera_I2C_Init(void)
|
||||
{
|
||||
LP_FLEXCOMM_Init(BOARD_CAMERA_I2C_INSTANCE, LP_FLEXCOMM_PERIPH_LPI2C);
|
||||
BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
|
||||
rxBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_SendSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_ReceiveSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
|
||||
rxBuffSize);
|
||||
}
|
||||
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
|
||||
/* Update Active mode voltage for OverDrive mode. */
|
||||
void BOARD_PowerMode_OD(void)
|
||||
{
|
||||
spc_active_mode_dcdc_option_t opt = {
|
||||
.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
|
||||
.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
|
||||
};
|
||||
SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
|
||||
|
||||
spc_sram_voltage_config_t cfg = {
|
||||
.operateVoltage = kSPC_sramOperateAt1P2V,
|
||||
.requestVoltageUpdate = true,
|
||||
};
|
||||
SPC_SetSRAMOperateVoltage(SPC0, &cfg);
|
||||
}
|
||||
@ -1,261 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_gpio.h"
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief The board name */
|
||||
#define BOARD_NAME "FRDM-MCXN947"
|
||||
|
||||
/*! @brief The UART to use for debug messages. */
|
||||
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART4
|
||||
#define BOARD_DEBUG_UART_INSTANCE 4U
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ 12000000U
|
||||
#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM4
|
||||
#define BOARD_DEBUG_UART_RST kFC4_RST_SHIFT_RSTn
|
||||
#define BOARD_DEBUG_UART_CLKSRC kCLOCK_FlexComm4
|
||||
#define BOARD_UART_IRQ_HANDLER LP_FLEXCOMM4_IRQHandler
|
||||
#define BOARD_UART_IRQ LP_FLEXCOMM4_IRQn
|
||||
|
||||
#define BOARD_DEBUG_UART_TYPE_CORE1 kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR_CORE1 (uint32_t) USART1
|
||||
#define BOARD_DEBUG_UART_INSTANCE_CORE1 1U
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ_CORE1 12000000U
|
||||
#define BOARD_DEBUG_UART_CLK_ATTACH_CORE1 kFRO12M_to_FLEXCOMM1
|
||||
#define BOARD_DEBUG_UART_RST_CORE1 kFC1_RST_SHIFT_RSTn
|
||||
#define BOARD_DEBUG_UART_CLKSRC_CORE1 kCLOCK_Flexcomm1
|
||||
#define BOARD_UART_IRQ_HANDLER_CORE1 FLEXCOMM1_IRQHandler
|
||||
#define BOARD_UART_IRQ_CORE1 FLEXCOMM1_IRQn
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE
|
||||
#define BOARD_DEBUG_UART_BAUDRATE 115200U
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE */
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE_CORE1
|
||||
#define BOARD_DEBUG_UART_BAUDRATE_CORE1 115200U
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE_CORE1 */
|
||||
|
||||
/*! @brief The UART to use for Bluetooth M.2 interface. */
|
||||
#define BOARD_BT_UART_INSTANCE 2
|
||||
#define BOARD_BT_UART_BAUDRATE 3000000
|
||||
#define BOARD_BT_UART_CLK_FREQ 12000000U
|
||||
#define BOARD_BT_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM2
|
||||
|
||||
/*! @brief The ENET PHY address. */
|
||||
#define BOARD_ENET0_PHY_ADDRESS (0x00U) /* Phy address of enet port 0. */
|
||||
|
||||
/*! @brief Memory ranges not usable by the ENET DMA. */
|
||||
#ifndef BOARD_ENET_NON_DMA_MEMORY_ARRAY
|
||||
#define BOARD_ENET_NON_DMA_MEMORY_ARRAY \
|
||||
{ \
|
||||
{0x00000000U, 0x0007FFFFU}, {0x10000000U, 0x17FFFFFFU}, {0x80000000U, 0xDFFFFFFFU}, \
|
||||
{0x00000000U, 0x00000000U}, \
|
||||
}
|
||||
#endif /* BOARD_ENET_NON_DMA_MEMORY_ARRAY */
|
||||
|
||||
#define BOARD_ACCEL_I2C_BASEADDR LPI2C2
|
||||
#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
|
||||
|
||||
#define BOARD_CODEC_I2C_BASEADDR LPI2C2
|
||||
#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
|
||||
#define BOARD_CODEC_I2C_INSTANCE 2
|
||||
|
||||
/*! @brief Indexes of the TSI channels for on-board electrodes */
|
||||
#ifndef BOARD_TSI_ELECTRODE_1
|
||||
#define BOARD_TSI_ELECTRODE_1 3U
|
||||
#endif
|
||||
|
||||
/*! @brief Indexes of the TSI mutual channels for FRDM-TOUCH board */
|
||||
#define BOARD_TSI_MUTUAL_TX_ELECTRODE_1 0U
|
||||
#define BOARD_TSI_MUTUAL_RX_ELECTRODE_1 14U
|
||||
|
||||
#ifndef BOARD_LED_RED_GPIO
|
||||
#define BOARD_LED_RED_GPIO GPIO0
|
||||
#endif
|
||||
#ifndef BOARD_LED_RED_GPIO_PIN
|
||||
#define BOARD_LED_RED_GPIO_PIN 10U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_LED_BLUE_GPIO
|
||||
#define BOARD_LED_BLUE_GPIO GPIO1
|
||||
#endif
|
||||
#ifndef BOARD_LED_BLUE_GPIO_PIN
|
||||
#define BOARD_LED_BLUE_GPIO_PIN 2U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_LED_GREEN_GPIO
|
||||
#define BOARD_LED_GREEN_GPIO GPIO0
|
||||
#endif
|
||||
#ifndef BOARD_LED_GREEN_GPIO_PIN
|
||||
#define BOARD_LED_GREEN_GPIO_PIN 27U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_SW2_GPIO
|
||||
#define BOARD_SW2_GPIO GPIO0
|
||||
#endif
|
||||
#ifndef BOARD_SW2_GPIO_PIN
|
||||
#define BOARD_SW2_GPIO_PIN 23U
|
||||
#endif
|
||||
#define BOARD_SW2_NAME "SW2"
|
||||
#define BOARD_SW2_IRQ GPIO00_IRQn
|
||||
#define BOARD_SW2_IRQ_HANDLER GPIO00_IRQHandler
|
||||
|
||||
#ifndef BOARD_SW3_GPIO
|
||||
#define BOARD_SW3_GPIO GPIO0
|
||||
#endif
|
||||
#ifndef BOARD_SW3_GPIO_PIN
|
||||
#define BOARD_SW3_GPIO_PIN 6U
|
||||
#endif
|
||||
#define BOARD_SW3_NAME "SW3"
|
||||
#define BOARD_SW3_IRQ GPIO00_IRQn
|
||||
#define BOARD_SW3_IRQ_HANDLER GPIO00_IRQHandler
|
||||
|
||||
/* USB PHY condfiguration */
|
||||
#define BOARD_USB_PHY_D_CAL (0x04U)
|
||||
#define BOARD_USB_PHY_TXCAL45DP (0x07U)
|
||||
#define BOARD_USB_PHY_TXCAL45DM (0x07U)
|
||||
|
||||
#define BOARD_HAS_NO_CTIMER_OUTPUT_PIN_CONNECTED_TO_LED (1)
|
||||
|
||||
/* Board led color mapping */
|
||||
#define LOGIC_LED_ON 0U
|
||||
#define LOGIC_LED_OFF 1U
|
||||
|
||||
#define LED_RED_INIT(output) \
|
||||
GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \
|
||||
BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */
|
||||
#define LED_RED_ON() GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */
|
||||
#define LED_RED_OFF() GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */
|
||||
#define LED_RED_TOGGLE() GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
|
||||
|
||||
#define LED_BLUE_INIT(output) \
|
||||
GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \
|
||||
BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Enable target LED_BLUE */
|
||||
#define LED_BLUE_ON() GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */
|
||||
#define LED_BLUE_OFF() GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */
|
||||
#define LED_BLUE_TOGGLE() GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
|
||||
|
||||
#define LED_GREEN_INIT(output) \
|
||||
GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \
|
||||
BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */
|
||||
#define LED_GREEN_ON() GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */
|
||||
#define LED_GREEN_OFF() GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */
|
||||
#define LED_GREEN_TOGGLE() GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
|
||||
|
||||
/* Display. */
|
||||
#define BOARD_LCD_DC_GPIO GPIO0
|
||||
#define BOARD_LCD_DC_GPIO_PORT 0U
|
||||
#define BOARD_LCD_DC_GPIO_PIN 10U
|
||||
|
||||
/* Camera */
|
||||
#define BOARD_CAMERA_I2C_BASEADDR LPI2C7
|
||||
#define BOARD_CAMERA_I2C_INSTANCE 7
|
||||
#define BOARD_CAMERA_I2C_CLOCK_FREQ CLOCK_GetLPFlexCommClkFreq(BOARD_CAMERA_I2C_INSTANCE)
|
||||
|
||||
/* Serial MWM WIFI */
|
||||
#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
|
||||
#define BOARD_SERIAL_MWM_PORT USART2
|
||||
#define BOARD_SERIAL_MWM_PORT_IRQn FLEXCOMM2_IRQn
|
||||
#define BOARD_SERIAL_MWM_RST_WRITE(output)
|
||||
|
||||
/*! @brief The EMVSIM SMARTCARD PHY configuration. */
|
||||
#define BOARD_SMARTCARD_MODULE (EMVSIM0) /*!< SMARTCARD communicational module instance */
|
||||
#define BOARD_SMARTCARD_MODULE_IRQ (EMVSIM0_IRQn) /*!< SMARTCARD communicational module IRQ handler */
|
||||
#define BOARD_SMARTCARD_CLOCK_MODULE_CLK_FREQ (CLOCK_GetEmvsimClkFreq(0U))
|
||||
#define BOARD_SMARTCARD_CLOCK_VALUE (4000000U) /*!< SMARTCARD clock frequency */
|
||||
|
||||
/* ERPC LPSPI configuration */
|
||||
#define ERPC_BOARD_LPSPI_SLAVE_READY_USE_GPIO (1)
|
||||
#define ERPC_BOARD_LPSPI_BASEADDR LPSPI3
|
||||
#define ERPC_BOARD_LPSPI_BAUDRATE 500000U
|
||||
#define ERPC_BOARD_LPSPI_CLKSRC kCLOCK_Flexcomm3
|
||||
#define ERPC_BOARD_LPSPI_CLK_FREQ 12000000 // CLOCK_GetFlexCommClkFreq(1)
|
||||
#define ERPC_BOARD_LPSPI_INT_GPIO GPIO0
|
||||
#define ERPC_BOARD_LPSPI_INT_PIN 16U
|
||||
#define ERPC_BOARD_LPSPI_INT_PIN_IRQ PIN_INT0_IRQn
|
||||
#define ERPC_BOARD_LPSPI_INT_PIN_IRQ_HANDLER PIN_INT0_IRQHandler
|
||||
|
||||
/* ERPC LPI2C configuration */
|
||||
#define ERPC_BOARD_LPI2C_BASEADDR LPI2C0_BASE
|
||||
#define ERPC_BOARD_LPI2C_BAUDRATE 100000U
|
||||
#define ERPC_BOARD_LPI2C_CLKSRC kCLOCK_Flexcomm0
|
||||
#define ERPC_BOARD_LPI2C_CLK_FREQ 12000000 // CLOCK_GetFlexCommClkFreq(2)
|
||||
#define ERPC_BOARD_LPI2C_INT_GPIO GPIO1
|
||||
#define ERPC_BOARD_LPI2C_INT_PIN 0U
|
||||
#define ERPC_BOARD_LPI2C_INT_PIN_IRQ PIN_INT1_IRQn
|
||||
#define ERPC_BOARD_LPI2C_INT_PIN_IRQ_HANDLER PIN_INT1_IRQHandler
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
void BOARD_InitDebugConsole(void);
|
||||
void BOARD_InitDebugConsole_Core1(void);
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
|
||||
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
void BOARD_Accel_I2C_Init(void);
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Codec_I2C_Init(void);
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Camera_I2C_Init(void);
|
||||
status_t BOARD_Camera_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Camera_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
|
||||
status_t BOARD_Camera_I2C_SendSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Camera_I2C_ReceiveSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
|
||||
void BOARD_PowerMode_OD(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
@ -1,354 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. Setup clock sources.
|
||||
*
|
||||
* 2. Set up wait states of the flash.
|
||||
*
|
||||
* 3. Set up all dividers.
|
||||
*
|
||||
* 4. Set up all selectors to provide selected clocks.
|
||||
*
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v11.0
|
||||
processor: MCXN947
|
||||
package_id: MCXN947VDF
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.13.10
|
||||
board: FRDM-MCXN947
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_clock.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockPLL150M();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockFRO12M
|
||||
outputs:
|
||||
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
|
||||
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
||||
- {id: MAIN_clock.outFreq, value: 12 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 3 MHz}
|
||||
- {id: System_clock.outFreq, value: 12 MHz}
|
||||
- {id: gdet_clock.outFreq, value: 48 MHz}
|
||||
- {id: trng_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: RunPowerMode, value: OD}
|
||||
- {id: SCGMode, value: SIRC}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
|
||||
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
|
||||
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockFRO12M(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
|
||||
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(12000000U, kOD_Mode); /*!< Set the additional number of flash wait-states */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF48M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockFROHF48M
|
||||
outputs:
|
||||
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
|
||||
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
||||
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
|
||||
- {id: MAIN_clock.outFreq, value: 48 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 12 MHz}
|
||||
- {id: System_clock.outFreq, value: 48 MHz}
|
||||
- {id: gdet_clock.outFreq, value: 48 MHz}
|
||||
- {id: trng_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: RunPowerMode, value: OD}
|
||||
- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
|
||||
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockFROHF48M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockFROHF48M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockFROHF48M(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
|
||||
|
||||
/* FRO OSC setup - begin, enable the FRO for safety switching */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(48000000U, kOD_Mode); /*!< Set the additional number of flash wait-states */
|
||||
|
||||
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF144M ********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockFROHF144M
|
||||
outputs:
|
||||
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
|
||||
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
||||
- {id: FRO_HF_clock.outFreq, value: 144 MHz}
|
||||
- {id: MAIN_clock.outFreq, value: 144 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 36 MHz}
|
||||
- {id: System_clock.outFreq, value: 144 MHz}
|
||||
- {id: gdet_clock.outFreq, value: 48 MHz}
|
||||
- {id: trng_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: RunPowerMode, value: OD}
|
||||
- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
|
||||
- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
|
||||
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
sources:
|
||||
- {id: SCG.FIRC.outFreq, value: 144 MHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockFROHF144M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockFROHF144M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockFROHF144M(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
|
||||
|
||||
/* FRO OSC setup - begin, enable the FRO for safety switching */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(144000000U, kOD_Mode); /*!< Set the additional number of flash wait-states */
|
||||
|
||||
CLOCK_SetupFROHFClocking(144000000U); /*!< Enable FRO HF(144MHz) output */
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL150M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL150M
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
|
||||
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
||||
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
|
||||
- {id: MAIN_clock.outFreq, value: 150 MHz}
|
||||
- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 37.5 MHz}
|
||||
- {id: System_clock.outFreq, value: 150 MHz}
|
||||
- {id: gdet_clock.outFreq, value: 48 MHz}
|
||||
- {id: trng_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: PLL0_Mode, value: Normal}
|
||||
- {id: RunPowerMode, value: OD}
|
||||
- {id: SCGMode, value: PLL0}
|
||||
- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
|
||||
- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
|
||||
- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
|
||||
- {id: SYSCON.FLEXSPICLKSEL.sel, value: NO_CLOCK}
|
||||
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL150M(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
|
||||
|
||||
/* FRO OSC setup - begin, enable the FRO for safety switching */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(150000000U, kOD_Mode); /*!< Set the additional number of flash wait-states */
|
||||
|
||||
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
|
||||
/*!< Set up PLL0 */
|
||||
const pll_setup_t pll0Setup = {
|
||||
.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
|
||||
.pllndiv = SCG_APLLNDIV_NDIV(8U),
|
||||
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
|
||||
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
|
||||
.pllRate = 150000000U
|
||||
};
|
||||
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
|
||||
CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL100M
|
||||
outputs:
|
||||
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
|
||||
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
- {id: CLK_IN_clock.outFreq, value: 24 MHz}
|
||||
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
||||
- {id: MAIN_clock.outFreq, value: 100 MHz}
|
||||
- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 25 MHz}
|
||||
- {id: System_clock.outFreq, value: 100 MHz}
|
||||
- {id: gdet_clock.outFreq, value: 48 MHz}
|
||||
- {id: trng_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: PLL1_Mode, value: Normal}
|
||||
- {id: RunPowerMode, value: OD}
|
||||
- {id: SCGMode, value: PLL1}
|
||||
- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
|
||||
- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
|
||||
- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
|
||||
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
|
||||
- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
|
||||
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
sources:
|
||||
- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL100M(void)
|
||||
{
|
||||
CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
|
||||
|
||||
/* FRO OSC setup - begin, enable the FRO for safety switching */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(100000000U, kOD_Mode); /*!< Set the additional number of flash wait-states */
|
||||
|
||||
CLOCK_SetupExtClocking(24000000U);
|
||||
CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */
|
||||
|
||||
/*!< Set up PLL1 */
|
||||
const pll_setup_t pll1Setup = {
|
||||
.pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
|
||||
.pllndiv = SCG_SPLLNDIV_NDIV(6U),
|
||||
.pllpdiv = SCG_SPLLPDIV_PDIV(2U),
|
||||
.pllmdiv = SCG_SPLLMDIV_MDIV(100U),
|
||||
.pllRate = 100000000U
|
||||
};
|
||||
CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
|
||||
CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
|
||||
}
|
||||
|
||||
@ -1,177 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
|
||||
#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO12M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF48M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFROHF48M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFROHF48M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFROHF48M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF144M ********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFROHF144M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */
|
||||
#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFROHF144M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFROHF144M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL150M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
|
||||
#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockPLL150M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
|
||||
#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockPLL100M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
@ -1,23 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Peripherals v1.0
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Included files
|
||||
******************************************************************************/
|
||||
#include "peripherals.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* BOARD_InitBootPeripherals function
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootPeripherals(void)
|
||||
{
|
||||
}
|
||||
@ -1,23 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _PERIPHERALS_H_
|
||||
#define _PERIPHERALS_H_
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /*_cplusplus. */
|
||||
/*******************************************************************************
|
||||
* BOARD_InitBootPeripherals function
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootPeripherals(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /*_cplusplus. */
|
||||
|
||||
#endif /* _PERIPHERALS_H_ */
|
||||
@ -1,705 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022-2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v14.0
|
||||
processor: MCXN947
|
||||
package_id: MCXN947VDF
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.14.19
|
||||
board: FRDM-MCXN947
|
||||
expansion_headers:
|
||||
- id: micro_bus
|
||||
name: mikroBUS(TM)
|
||||
connectors:
|
||||
- id: C1
|
||||
name: J6
|
||||
pins:
|
||||
- {id: 1, name: AN, pin_num: T2, pin_signal: ADC1_A0}
|
||||
- {id: 2, name: RST, pin_num: B4, pin_signal: PIO1_3/WUU0_IN7/TRIG_OUT1/FC3_P3/CT1_MAT1/SCT0_IN7/FLEXIO0_D11/ENET0_MDIO/SAI1_RXD0/CAN0_RXD/TSI0_CH3/ADC0_A19/CMP0_IN1}
|
||||
- {id: 3, name: CS, pin_num: M15, pin_signal: PIO3_23/FC6_P3/CT_INP11/PWM1_X3/FLEXIO0_D31/SAI1_TXD1}
|
||||
- {id: 4, name: SCK, pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0}
|
||||
- {id: 5, name: MISO, pin_num: M16, pin_signal: PIO3_22/FC8_P6/FC6_P2/CT_INP10/PWM1_X2/FLEXIO0_D30/SIM0_VCCEN/SAI1_RXD1}
|
||||
- {id: 6, name: MOSI, pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0}
|
||||
- id: C2
|
||||
name: J5
|
||||
pins:
|
||||
- {id: 1, name: PWM, pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS}
|
||||
- {id: 2, name: INT, pin_num: L13, pin_signal: PIO5_7/TRIG_IN11/TAMPER5/ADC1_B15}
|
||||
- {id: 3, name: RX, pin_num: F6, pin_signal: PIO1_16/WUU0_IN14/FC5_P0/FC3_P4/CT_INP12/SCT0_OUT6/FLEXIO0_D24/PLU_OUT4/ENET0_RXD2/I3C1_SDA/ADC1_A16}
|
||||
- {id: 4, name: TX, pin_num: F4, pin_signal: PIO1_17/FC5_P1/FC3_P5/CT_INP13/SCT0_OUT7/FLEXIO0_D25/PLU_OUT5/ENET0_RXD3/I3C1_SCL/ADC1_A17}
|
||||
- {id: 5, name: SCL, pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0}
|
||||
- {id: 6, name: SDA, pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0}
|
||||
- id: frdm_arduino
|
||||
name: LPCXpresso V3 (Arduino compatible)
|
||||
connectors:
|
||||
- id: C1
|
||||
name: J3
|
||||
pins:
|
||||
- {id: 1, pin_num: H2, pin_signal: PIO2_0/TRIG_IN5/FC9_P6/SDHC0_D5/SCT0_IN0/PWM1_A3/FLEXIO0_D8/FLEXSPI0_B_SS1_b/SAI0_RX_BCLK}
|
||||
- {id: 2, pin_num: U2, pin_signal: DAC2_OUT/ADC0_A3/ADC1_A3}
|
||||
- {id: 3, pin_num: L4, pin_signal: PIO1_22/TRIG_IN3/FC5_P6/FC4_P2/CT_INP14/SCT0_OUT4/FLEXIO0_D30/ADC1_A22}
|
||||
- {id: 5, pin_num: J3, pin_signal: PIO2_3/FC9_P1/SDHC0_D0/SCT0_OUT1/PWM1_B2/FLEXIO0_D11/FLEXSPI0_B_SCLK/SINC0_MBIT0/SAI0_RXD0}
|
||||
- {id: 6, pin_num: F3, pin_signal: RESET_B}
|
||||
- {id: 7, pin_num: H3, pin_signal: PIO2_2/WUU0_IN16/CLKOUT/FC9_P3/SDHC0_D1/SCT0_OUT0/PWM1_A2/FLEXIO0_D10/FLEXSPI0_B_SS0_b/SINC0_MCLK0/SAI0_TXD0}
|
||||
- {id: 9, pin_num: K1, pin_signal: PIO2_5/TRIG_OUT3/FC9_P2/SDHC0_CMD/SCT0_OUT3/PWM1_B1/FLEXIO0_D13/FLEXSPI0_B_DATA1/SINC0_MBIT1/SAI0_TXD1}
|
||||
- {id: 11, pin_num: K3, pin_signal: PIO2_4/WUU0_IN17/FC9_P0/SDHC0_CLK/SCT0_OUT2/PWM1_A1/FLEXIO0_D12/FLEXSPI0_B_DATA0/SINC0_MCLK1/SAI0_RXD1}
|
||||
- {id: 13, pin_num: L2, pin_signal: PIO2_7/TRIG_IN5/FC9_P5/SDHC0_D2/SCT0_OUT5/PWM1_B0/FLEXIO0_D15/FLEXSPI0_B_DATA3/SINC0_MBIT2/SAI0_TX_FS}
|
||||
- {id: 15, pin_num: K2, pin_signal: PIO2_6/TRIG_IN4/FC9_P4/SDHC0_D3/SCT0_OUT4/PWM1_A0/FLEXIO0_D14/FLEXSPI0_B_DATA2/SINC0_MCLK2/SAI0_TX_BCLK}
|
||||
- id: C2
|
||||
name: J2
|
||||
pins:
|
||||
- {id: 1, pin_num: T3, pin_signal: ADC1_B0}
|
||||
- {id: 2, pin_num: E8, pin_signal: PIO0_28/FC1_P4/FC0_P4/CT_INP0/ADC0_B20}
|
||||
- {id: 3, pin_num: M10, pin_signal: PIO5_2/VBAT_WAKEUP_b/SPC_LPREQ/TAMPER0/ADC1_B10}
|
||||
- {id: 4, pin_num: B12, pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10}
|
||||
- {id: 5, pin_num: N11, pin_signal: PIO5_3/TRIG_IN11/RTC_CLKOUT/TAMPER1/ADC1_B11}
|
||||
- {id: 6, pin_num: E10, pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19}
|
||||
- {id: 7, pin_num: M12, pin_signal: PIO5_4/TRIG_OUT7/SPC_LPREQ/TAMPER2/ADC1_B12}
|
||||
- {id: 8, pin_num: B6, pin_signal: PIO0_24/FC1_P0/CT0_MAT0/ADC0_B16}
|
||||
- {id: 9, pin_num: B15, pin_signal: PIO0_3/TDI/FC1_P3/CT0_MAT1/UTICK_CAP1/HSCMP0_OUT/CMP1_IN1}
|
||||
- {id: 10, pin_num: F10, pin_signal: PIO0_26/FC1_P2/CT0_MAT2/ADC0_B18}
|
||||
- {id: 11, pin_num: C10, pin_signal: PIO0_18/EWM0_IN/FC0_P2/CT0_MAT2/FLEXIO0_D2/HSCMP0_OUT/PDM0_DATA1/TSI0_CH13/ADC0_A10}
|
||||
- {id: 12, pin_num: A6, pin_signal: PIO0_25/FC1_P1/CT0_MAT1/ADC0_B17}
|
||||
- {id: 13, pin_num: C9, pin_signal: PIO0_19/WUU0_IN3/EWM0_OUT_b/FC0_P3/CT0_MAT3/FLEXIO0_D3/HSCMP1_OUT/TSI0_CH14/ADC0_A11}
|
||||
- {id: 15, pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0}
|
||||
- {id: 17, pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0}
|
||||
- {id: 18, pin_num: P1, pin_signal: PIO4_0/WUU0_IN18/TRIG_IN6/FC2_P0/CT_INP16/PLU_IN0/SINC0_MCLK3}
|
||||
- {id: 20, pin_num: P2, pin_signal: PIO4_1/TRIG_IN7/FC2_P1/CT_INP17/PLU_IN1}
|
||||
- id: C3
|
||||
name: J1
|
||||
pins:
|
||||
- {id: 1, pin_num: J15, pin_signal: PIO3_16/FC8_P2/CT_INP8/PWM1_A2/FLEXIO0_D24/SIM0_CLK/SAI1_TX_BCLK}
|
||||
- {id: 2, pin_num: U1, pin_signal: PIO4_3/WUU0_IN19/TRIG_IN7/FC2_P3/CT_INP13/PLU_IN3/DAC1_OUT/ADC0_B4/ADC1_B4/CMP0_IN5N/CMP1_IN5N/CMP2_IN5N}
|
||||
- {id: 3, pin_num: T7, pin_signal: PIO4_13/TRIG_IN8/FC2_P1/USB1_ID/CT4_MAT1/FLEXIO0_D21/PLU_OUT1/SINC0_MBIT0/CAN0_TXD/OPAMP0_INP1/ADC0_B5/ADC1_B5}
|
||||
- {id: 4, pin_num: T1, pin_signal: PIO4_2/TRIG_IN6/FC2_P2/CT_INP12/PLU_IN2/SINC0_MBIT3/DAC0_OUT/ADC0_A4/ADC1_A4/CMP0_IN4N/CMP1_IN4N/CMP2_IN4N}
|
||||
- {id: 5, pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0}
|
||||
- {id: 6, pin_num: F8, pin_signal: PIO0_29/FC1_P5/FC0_P5/CT_INP1/ADC0_B21}
|
||||
- {id: 7, pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3}
|
||||
- {id: 8, pin_num: M4, pin_signal: PIO1_23/FC4_P3/CT_INP15/SCT0_OUT5/FLEXIO0_D31/ADC1_A23}
|
||||
- {id: 9, pin_num: K16, pin_signal: PIO3_18/FC6_P6/CT2_MAT0/PWM1_X0/FLEXIO0_D26/SAI1_RX_BCLK}
|
||||
- {id: 10, pin_num: E7, pin_signal: PIO0_30/FC1_P6/FC0_P6/CT_INP2/ADC0_B22}
|
||||
- {id: 11, pin_num: K15, pin_signal: PIO3_17/WUU0_IN26/FC8_P3/CT_INP9/PWM1_B2/FLEXIO0_D25/SIM0_IO/SAI1_TX_FS}
|
||||
- {id: 12, pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3}
|
||||
- {id: 13, pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS}
|
||||
- {id: 14, pin_num: C4, pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0}
|
||||
- {id: 15, pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0}
|
||||
- {id: 16, pin_num: D7, pin_signal: PIO0_31/CT_INP3/ADC0_B23}
|
||||
- id: C4
|
||||
name: J4
|
||||
pins:
|
||||
- {id: 1, pin_num: T6, pin_signal: PIO4_12/WUU0_IN20/USB0_VBUS_DET/FC2_P0/CT4_MAT0/FLEXIO0_D20/PLU_OUT0/SINC0_MCLK0/CAN0_RXD/OPAMP0_INP0/ADC0_A5/ADC1_A5}
|
||||
- {id: 2, pin_num: P3, pin_signal: ADC0_A0}
|
||||
- {id: 3, pin_num: U6, pin_signal: OPAMP0_INN}
|
||||
- {id: 4, pin_num: R3, pin_signal: ADC0_B0}
|
||||
- {id: 5, pin_num: R8, pin_signal: PIO4_16/FC2_P2/USB1_OTG_PWR/CT3_MAT0/FLEXIO0_D24/PLU_OUT4/SINC0_MCLK1/CAN1_TXD/OPAMP1_INP0/ADC0_A6}
|
||||
- {id: 6, pin_num: E11, pin_signal: PIO0_14/FC1_P6/FC0_P2/CT_INP2/UTICK_CAP0/FLEXIO0_D6/ADC0_B14}
|
||||
- {id: 7, pin_num: U8, pin_signal: OPAMP1_INN}
|
||||
- {id: 8, pin_num: B8, pin_signal: PIO0_22/EWM0_IN/FC0_P6/FC1_P2/CT_INP2/FLEXIO0_D6/I3C0_PUR/ADC0_A14/CMP1_IN2}
|
||||
- {id: 9, pin_num: T10, pin_signal: PIO4_20/TRIG_IN8/FC2_P4/CT2_MAT0/FLEXIO0_D28/SINC0_MCLK2/OPAMP2_INP0/ADC1_A6}
|
||||
- {id: 10, pin_num: G13, pin_signal: PIO0_15/FC0_P3/CT_INP3/UTICK_CAP1/FLEXIO0_D7/ADC0_B15}
|
||||
- {id: 11, pin_num: U10, pin_signal: OPAMP2_INN}
|
||||
- {id: 12, pin_num: B7, pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2}
|
||||
- {id: frdm_arduino, name: LPCXpressoV2/V3 Expansion Header}
|
||||
- {id: micro_bus, name: mikroBUS Click Header}
|
||||
external_user_signals: {}
|
||||
pin_labels:
|
||||
- {pin_num: A1, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8, label: 'P1_8/J9[32]',
|
||||
identifier: DEBUG_UART_RX}
|
||||
- {pin_num: B1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9, label: 'P1_9/J9[30]', identifier: DEBUG_UART_TX}
|
||||
- {pin_num: D1, pin_signal: PIO1_13/TRIG_IN3/FC4_P5/FC3_P1/CT2_MAT3/SCT0_OUT5/FLEXIO0_D21/PLU_OUT3/ENET0_RXDV/CAN1_TXD/TSI0_CH22/ADC1_A13, label: 'P1_13/J9[27]'}
|
||||
- {pin_num: F1, pin_signal: PIO1_30/TRIG_OUT3/CT_INP16/SCT0_OUT8/SAI0_MCLK/XTAL48M, label: 'P1_30/XTAL/Y1[1]'}
|
||||
- {pin_num: H1, pin_signal: PIO2_1/TRACE_CLK/SDHC0_D4/SCT0_IN1/PWM1_B3/FLEXIO0_D9/FLEXSPI0_B_DQS/SINC0_MCLK_OUT0/SAI0_RX_FS, label: 'P2_1/TP27/J12[9]'}
|
||||
- {pin_num: K1, pin_signal: PIO2_5/TRIG_OUT3/FC9_P2/SDHC0_CMD/SCT0_OUT3/PWM1_B1/FLEXIO0_D13/FLEXSPI0_B_DATA1/SINC0_MBIT1/SAI0_TXD1, label: 'P2_5/TP25/J12[3]/J3[9]/SJ6[3]'}
|
||||
- {pin_num: M1, pin_signal: PIO2_9/TRACE_DATA1/SDHC0_D6/SCT0_IN3/PWM1_X1/FLEXIO0_D17/FLEXSPI0_B_DATA5/SINC0_MBIT3/SAI1_RXD0, label: 'P2_9/J8[14]'}
|
||||
- {pin_num: P1, pin_signal: PIO4_0/WUU0_IN18/TRIG_IN6/FC2_P0/CT_INP16/PLU_IN0/SINC0_MCLK3, label: 'P4_0/J8[4]/SJ14[1]'}
|
||||
- {pin_num: T1, pin_signal: PIO4_2/TRIG_IN6/FC2_P2/CT_INP12/PLU_IN2/SINC0_MBIT3/DAC0_OUT/ADC0_A4/ADC1_A4/CMP0_IN4N/CMP1_IN4N/CMP2_IN4N, label: 'P4_2/J1[4]'}
|
||||
- {pin_num: U1, pin_signal: PIO4_3/WUU0_IN19/TRIG_IN7/FC2_P3/CT_INP13/PLU_IN3/DAC1_OUT/ADC0_B4/ADC1_B4/CMP0_IN5N/CMP1_IN5N/CMP2_IN5N, label: 'P4_3/J1[2]'}
|
||||
- {pin_num: A2, pin_signal: PIO1_7/WUU0_IN9/TRIG_OUT2/FC5_P3/CT_INP7/SCT0_IN1/FLEXIO0_D15/PLU_CLK/ENET0_TXD1/SAI1_RX_FS/CAN1_RXD/TSI0_CH7/ADC0_A23, label: 'P1_7/J9[9]'}
|
||||
- {pin_num: B2, pin_signal: PIO1_6/TRIG_IN2/FC3_P6/FC5_P2/CT_INP6/SCT0_IN0/FLEXIO0_D14/ENET0_TXD0/SAI1_RX_BCLK/CAN1_TXD/TSI0_CH6/ADC0_A22, label: 'P1_6/J9[10]'}
|
||||
- {pin_num: D2, pin_signal: PIO1_12/WUU0_IN12/TRACE_CLK/FC4_P4/FC3_P0/CT2_MAT2/SCT0_OUT4/FLEXIO0_D20/PLU_OUT2/ENET0_RXER/CAN1_RXD/TSI0_CH21/ADC1_A12, label: 'P1_12/J2[11]/J9[28]'}
|
||||
- {pin_num: F2, pin_signal: PIO1_31/TRIG_IN4/CT_INP17/SCT0_OUT9/EXTAL48M, label: 'P1_31/EXTAL/Y1[3]'}
|
||||
- {pin_num: G2, pin_signal: VSS0, label: GND}
|
||||
- {pin_num: H2, pin_signal: PIO2_0/TRIG_IN5/FC9_P6/SDHC0_D5/SCT0_IN0/PWM1_A3/FLEXIO0_D8/FLEXSPI0_B_SS1_b/SAI0_RX_BCLK, label: 'P2_0/J3[1]/SJ8[3]'}
|
||||
- {pin_num: K2, pin_signal: PIO2_6/TRIG_IN4/FC9_P4/SDHC0_D3/SCT0_OUT4/PWM1_A0/FLEXIO0_D14/FLEXSPI0_B_DATA2/SINC0_MCLK2/SAI0_TX_BCLK, label: 'P2_6/TP24/J12[2]/J3[15]/SJ1[3]'}
|
||||
- {pin_num: L2, pin_signal: PIO2_7/TRIG_IN5/FC9_P5/SDHC0_D2/SCT0_OUT5/PWM1_B0/FLEXIO0_D15/FLEXSPI0_B_DATA3/SINC0_MBIT2/SAI0_TX_FS, label: 'P2_7/TP23/J12[1]/J3[13]/SJ3[3]'}
|
||||
- {pin_num: M2, pin_signal: PIO2_8/TRACE_DATA0/SDHC0_D7/SCT0_IN2/PWM1_X0/FLEXIO0_D16/FLEXSPI0_B_DATA4/SINC0_MCLK3/SAI1_TXD0, label: 'P2_8/J8[13]'}
|
||||
- {pin_num: P2, pin_signal: PIO4_1/TRIG_IN7/FC2_P1/CT_INP17/PLU_IN1, label: 'P4_1/J8[3]/SJ15[1]'}
|
||||
- {pin_num: T2, pin_signal: ADC1_A0, label: 'ANA_4/ADC1_A0/J6[1]'}
|
||||
- {pin_num: U2, pin_signal: DAC2_OUT/ADC0_A3/ADC1_A3, label: 'ANA_6/ADC0_A3/J3[2]'}
|
||||
- {pin_num: B3, pin_signal: PIO1_5/FREQME_CLK_IN1/FC3_P5/FC5_P1/CT1_MAT3/SCT0_OUT1/FLEXIO0_D13/ENET0_TXEN/SAI0_RXD1/TSI0_CH5/ADC0_A21/CMP0_IN3, label: 'P1_5/J9[7]'}
|
||||
- {pin_num: C3, pin_signal: PIO1_10/TRACE_DATA2/FC4_P2/FC5_P6/CT2_MAT0/SCT0_IN2/FLEXIO0_D18/PLU_IN0/ENET0_TXER/CAN0_TXD/TSI0_CH19/ADC1_A10, label: 'P1_10/SJ20[3]/SJ16[2]'}
|
||||
- {pin_num: D3, pin_signal: PIO1_11/WUU0_IN11/TRACE_DATA3/FC4_P3/CT2_MAT1/SCT0_IN3/FLEXIO0_D19/PLU_IN1/ENET0_RX_CLK/I3C1_PUR/CAN0_RXD/TSI0_CH20/ADC1_A11, label: 'P1_11/SJ26[2]'}
|
||||
- {pin_num: F3, pin_signal: RESET_B, label: 'RESET_B/J23[10]/D16[1]/SW1[3]/SW1[4]/J3[6]', identifier: SW1}
|
||||
- {pin_num: H3, pin_signal: PIO2_2/WUU0_IN16/CLKOUT/FC9_P3/SDHC0_D1/SCT0_OUT0/PWM1_A2/FLEXIO0_D10/FLEXSPI0_B_SS0_b/SINC0_MCLK0/SAI0_TXD0, label: 'P2_2/TP5/J12[8]/J3[7]/SJ7[3]'}
|
||||
- {pin_num: J3, pin_signal: PIO2_3/FC9_P1/SDHC0_D0/SCT0_OUT1/PWM1_B2/FLEXIO0_D11/FLEXSPI0_B_SCLK/SINC0_MBIT0/SAI0_RXD0, label: 'P2_3/TP4/J12[7]/J3[5]/SJ4[3]'}
|
||||
- {pin_num: K3, pin_signal: PIO2_4/WUU0_IN17/FC9_P0/SDHC0_CLK/SCT0_OUT2/PWM1_A1/FLEXIO0_D12/FLEXSPI0_B_DATA0/SINC0_MCLK1/SAI0_RXD1, label: 'P2_4/TP26/J12[5]/J3[11]/SJ5[3]'}
|
||||
- {pin_num: M3, pin_signal: PIO2_10/TRACE_DATA2/SCT0_IN4/PWM1_X2/FLEXIO0_D18/FLEXSPI0_B_DATA6/SINC0_MCLK4/SAI1_RXD1, label: 'P2_10/J8[15]'}
|
||||
- {pin_num: P3, pin_signal: ADC0_A0, label: 'ADC0_A0/ARD_A0/J4[2]'}
|
||||
- {pin_num: R3, pin_signal: ADC0_B0, label: 'ADC0_B0/ARD_A1/J4[4]'}
|
||||
- {pin_num: T3, pin_signal: ADC1_B0, label: 'ADC1_B0/MC_BEMF_A/J2[1]'}
|
||||
- {pin_num: A4, pin_signal: PIO1_4/WUU0_IN8/FREQME_CLK_IN0/FC3_P4/FC5_P0/CT1_MAT2/SCT0_OUT0/FLEXIO0_D12/ENET0_TX_CLK/SAI0_TXD1/TSI0_CH4/ADC0_A20/CMP0_IN2, label: 'P1_4/SJ27[2]'}
|
||||
- {pin_num: B4, pin_signal: PIO1_3/WUU0_IN7/TRIG_OUT1/FC3_P3/CT1_MAT1/SCT0_IN7/FLEXIO0_D11/ENET0_MDIO/SAI1_RXD0/CAN0_RXD/TSI0_CH3/ADC0_A19/CMP0_IN1, label: 'P1_3/J6[2]'}
|
||||
- {pin_num: C4, pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0, label: 'P1_2/SJ4[1]',
|
||||
identifier: LED_BLUE}
|
||||
- {pin_num: D4, pin_signal: PIO1_14/FC4_P6/FC3_P2/CT_INP10/SCT0_IN4/FLEXIO0_D22/PLU_IN2/ENET0_RXD0/TSI0_CH23/ADC1_A14, label: 'P1_14/J9[2]'}
|
||||
- {pin_num: E4, pin_signal: PIO1_15/WUU0_IN13/FC3_P3/CT_INP11/SCT0_IN5/FLEXIO0_D23/PLU_IN3/ENET0_RXD1/I3C1_PUR/TSI0_CH24/ADC1_A15, label: 'P1_15/J9[1]'}
|
||||
- {pin_num: F4, pin_signal: PIO1_17/FC5_P1/FC3_P5/CT_INP13/SCT0_OUT7/FLEXIO0_D25/PLU_OUT5/ENET0_RXD3/I3C1_SCL/ADC1_A17, label: 'P1_17/SJ15[3]/J5[4]/J9[3]'}
|
||||
- {pin_num: G4, pin_signal: PIO1_18/FREQME_CLK_IN0/FC5_P2/FC3_P6/CT3_MAT0/SCT0_IN6/FLEXIO0_D26/PLU_IN4/ENET0_COL/CAN0_TXD/ADC1_A18, label: 'P1_18/J9[6]'}
|
||||
- {pin_num: J4, pin_signal: VSS1, label: GND}
|
||||
- {pin_num: L4, pin_signal: PIO1_22/TRIG_IN3/FC5_P6/FC4_P2/CT_INP14/SCT0_OUT4/FLEXIO0_D30/ADC1_A22, label: 'P1_22/J9[24]/J3[3]/SJ9[3]'}
|
||||
- {pin_num: M4, pin_signal: PIO1_23/FC4_P3/CT_INP15/SCT0_OUT5/FLEXIO0_D31/ADC1_A23, label: 'P1_23/J9[23]/SJ1[1]'}
|
||||
- {pin_num: N4, pin_signal: PIO2_11/TRACE_DATA3/SCT0_IN5/PWM1_X3/FLEXIO0_D19/FLEXSPI0_B_DATA7/SINC0_MBIT4/SAI1_TXD1, label: 'P2_11/J8[16]'}
|
||||
- {pin_num: P4, pin_signal: VDD_P40, label: VDD_P4}
|
||||
- {pin_num: R4, pin_signal: VDD_ANA, label: 'VDD_ANA/J2[16]'}
|
||||
- {pin_num: T4, pin_signal: PIO4_7/CT_INP19, label: 'P4_7/J8[7]'}
|
||||
- {pin_num: U4, pin_signal: VREFO/ADC0_A7/ADC1_A7, label: VREFO/TP1}
|
||||
- {pin_num: C5, pin_signal: PIO1_1/TRIG_IN1/FC3_P1/FC4_P5/CT_INP5/SCT0_OUT7/FLEXIO0_D9/SAI1_TX_FS/TSI0_CH1/ADC0_A17/CMP1_IN0, label: 'P1_1/J5[5]/J2[15]'}
|
||||
- {pin_num: E5, pin_signal: VSS3, label: GND}
|
||||
- {pin_num: G5, pin_signal: PIO1_19/WUU0_IN15/FREQME_CLK_IN1/FC5_P3/CT3_MAT1/SCT0_IN7/FLEXIO0_D27/PLU_IN5/ENET0_CRS/CAN0_RXD/ADC1_A19, label: 'P1_19/J9[5]'}
|
||||
- {pin_num: H5, pin_signal: VSS2, label: GND}
|
||||
- {pin_num: K5, pin_signal: PIO1_20/TRIG_IN2/FC5_P4/FC4_P0/CT3_MAT2/SCT0_OUT8/FLEXIO0_D28/PLU_OUT6/ENET0_MDC/CAN1_TXD/ADC1_A20/CMP1_IN3, label: P1_20}
|
||||
- {pin_num: L5, pin_signal: PIO1_21/TRIG_OUT2/FC5_P5/FC4_P1/CT3_MAT3/SCT0_OUT9/FLEXIO0_D29/PLU_OUT7/ENET0_MDIO/SAI1_MCLK/CAN1_RXD/ADC1_A21/CMP2_IN3, label: 'P1_21/SJ3[1]/J1[7]'}
|
||||
- {pin_num: N5, pin_signal: VDD_P41, label: VDD_P4}
|
||||
- {pin_num: R5, pin_signal: VREFH, label: VREFH}
|
||||
- {pin_num: A6, pin_signal: PIO0_25/FC1_P1/CT0_MAT1/ADC0_B17, label: 'P0_25/J2[12]'}
|
||||
- {pin_num: B6, pin_signal: PIO0_24/FC1_P0/CT0_MAT0/ADC0_B16, label: 'P0_24/SJ7[1]'}
|
||||
- {pin_num: C6, pin_signal: PIO1_0/WUU0_IN6/LPTMR0_ALT3/TRIG_IN0/FC3_P0/FC4_P4/CT_INP4/SCT0_OUT6/FLEXIO0_D8/SAI1_TX_BCLK/TSI0_CH0/ADC0_A16/CMP0_IN0, label: 'P1_0/J5[6]/J2[17]'}
|
||||
- {pin_num: N13, pin_signal: VSS4, label: GND}
|
||||
- {pin_num: F6, pin_signal: PIO1_16/WUU0_IN14/FC5_P0/FC3_P4/CT_INP12/SCT0_OUT6/FLEXIO0_D24/PLU_OUT4/ENET0_RXD2/I3C1_SDA/ADC1_A16, label: 'P1_16/SJ14[3]/J5[3]/J9[4]'}
|
||||
- {pin_num: H6, pin_signal: VDD1, label: VDD_P0/1}
|
||||
- {pin_num: K6, pin_signal: VDD_LDO_CORE, label: VDD_LDO_CORE_IN}
|
||||
- {pin_num: M6, pin_signal: PIO4_4/FC2_P4/CT_INP14/PLU_IN4/SINC0_MCLK4, label: 'P4_4/J9[26]'}
|
||||
- {pin_num: P6, pin_signal: VSS_P41, label: GND}
|
||||
- {pin_num: R6, pin_signal: VREFL, label: AGND}
|
||||
- {pin_num: T6, pin_signal: PIO4_12/WUU0_IN20/USB0_VBUS_DET/FC2_P0/CT4_MAT0/FLEXIO0_D20/PLU_OUT0/SINC0_MCLK0/CAN0_RXD/OPAMP0_INP0/ADC0_A5/ADC1_A5, label: 'P4_12/SJ25[1]/J8[17]'}
|
||||
- {pin_num: U6, pin_signal: OPAMP0_INN, label: 'OPAMP0_INN/RSHUNT_CURA_N/SJ24[1]'}
|
||||
- {pin_num: B7, pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, label: 'P0_23/SJ9[1]/SW2[3]/SW2[4]', identifier: SW2}
|
||||
- {pin_num: D7, pin_signal: PIO0_31/CT_INP3/ADC0_B23, label: 'P0_31/J1[16]'}
|
||||
- {pin_num: E7, pin_signal: PIO0_30/FC1_P6/FC0_P6/CT_INP2/ADC0_B22, label: 'P0_30/SJ2[1]'}
|
||||
- {pin_num: G7, pin_signal: VDD0, label: VDD_P0/1}
|
||||
- {pin_num: L7, pin_signal: VDD_P20, label: VDD_P2}
|
||||
- {pin_num: N7, pin_signal: PIO4_6/TRIG_OUT4/FC2_P6/CT_INP18/PLU_CLK, label: 'P4_6/J8[5]'}
|
||||
- {pin_num: P7, pin_signal: VSS_P42, label: GND}
|
||||
- {pin_num: T7, pin_signal: PIO4_13/TRIG_IN8/FC2_P1/USB1_ID/CT4_MAT1/FLEXIO0_D21/PLU_OUT1/SINC0_MBIT0/CAN0_TXD/OPAMP0_INP1/ADC0_B5/ADC1_B5, label: 'P4_13/SJ10[1]/SJ2[3]/J8[18]'}
|
||||
- {pin_num: A8, pin_signal: PIO0_21/FC0_P5/FC1_P1/CT_INP1/FLEXIO0_D5/I3C0_SCL/TSI0_CH16/ADC0_A13, label: 'P0_21/SJ25[3]'}
|
||||
- {pin_num: B8, pin_signal: PIO0_22/EWM0_IN/FC0_P6/FC1_P2/CT_INP2/FLEXIO0_D6/I3C0_PUR/ADC0_A14/CMP1_IN2, label: 'P0_22/J4[8]/SJ18[3]'}
|
||||
- {pin_num: C8, pin_signal: PIO0_20/WUU0_IN4/FC0_P4/FC1_P0/CT_INP0/FLEXIO0_D4/I3C0_SDA/TSI0_CH15/ADC0_A12, label: 'P0_20/SJ24[3]/J7[2]'}
|
||||
- {pin_num: E8, pin_signal: PIO0_28/FC1_P4/FC0_P4/CT_INP0/ADC0_B20, label: 'P0_28/J2[2]'}
|
||||
- {pin_num: F8, pin_signal: PIO0_29/FC1_P5/FC0_P5/CT_INP1/ADC0_B21, label: 'P0_29/J1[6]'}
|
||||
- {pin_num: H8, pin_signal: VDD2, label: VDD_P0/1}
|
||||
- {pin_num: H13, pin_signal: VSS10, label: GND}
|
||||
- {pin_num: K8, pin_signal: VDD_P21, label: VDD_P2}
|
||||
- {pin_num: M8, pin_signal: PIO4_5/FC2_P5/CT_INP15/PLU_IN5/SINC0_MBIT4, label: 'P4_5/SJ11[3]/J8[6]'}
|
||||
- {pin_num: N8, pin_signal: PIO4_14/CT4_MAT2/FLEXIO0_D22/PLU_OUT2, label: 'P4_14/J8[19]'}
|
||||
- {pin_num: R8, pin_signal: PIO4_16/FC2_P2/USB1_OTG_PWR/CT3_MAT0/FLEXIO0_D24/PLU_OUT4/SINC0_MCLK1/CAN1_TXD/OPAMP1_INP0/ADC0_A6, label: 'P4_16/SJ23[1]/J8[21]'}
|
||||
- {pin_num: T8, pin_signal: PIO4_15/WUU0_IN21/TRIG_OUT4/USB1_VBUS_DIG/CT4_MAT3/FLEXIO0_D23/PLU_OUT3/SINC0_MCLK_OUT0/CAN1_RXD/OPAMP0_OUT/ADC0_A1/CMP0_IN4P, label: 'P4_15/J8[20]'}
|
||||
- {pin_num: U8, pin_signal: OPAMP1_INN, label: 'OPAMP1_INN/RSHUNT_CURB_N/SJ22[1]'}
|
||||
- {pin_num: C9, pin_signal: PIO0_19/WUU0_IN3/EWM0_OUT_b/FC0_P3/CT0_MAT3/FLEXIO0_D3/HSCMP1_OUT/TSI0_CH14/ADC0_A11, label: 'P0_19/J2[13]/J7[1]'}
|
||||
- {pin_num: D6, pin_signal: VSS5, label: GND}
|
||||
- {pin_num: E13, pin_signal: VSS8, label: GND}
|
||||
- {pin_num: J14, pin_signal: VSS13, label: GND}
|
||||
- {pin_num: P9, pin_signal: VSS_P40, label: GND}
|
||||
- {pin_num: R9, pin_signal: PIO4_17/TRIG_IN9/FC2_P3/USB1_OTG_OC/CT3_MAT1/FLEXIO0_D25/PLU_OUT5/SINC0_MBIT1/OPAMP1_INP1/ADC0_B6, label: 'P4_17/J8[22]'}
|
||||
- {pin_num: A10, pin_signal: PIO0_17/FC0_P1/CT0_MAT1/UTICK_CAP3/FLEXIO0_D1/PDM0_DATA0/I3C0_SCL/TSI0_CH12/ADC0_A9, label: 'P0_17/J7[7]'}
|
||||
- {pin_num: B10, pin_signal: PIO0_16/WUU0_IN2/FC0_P0/CT0_MAT0/UTICK_CAP2/FLEXIO0_D0/PDM0_CLK/I3C0_SDA/TSI0_CH11/ADC0_A8, label: 'P0_16/J7[3]'}
|
||||
- {pin_num: C10, pin_signal: PIO0_18/EWM0_IN/FC0_P2/CT0_MAT2/FLEXIO0_D2/HSCMP0_OUT/PDM0_DATA1/TSI0_CH13/ADC0_A10, label: 'P0_18/SJ23[3]/J7[5]'}
|
||||
- {pin_num: E10, pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19, label: 'P0_27/SJ6[1]', identifier: LED_GREEN}
|
||||
- {pin_num: F10, pin_signal: PIO0_26/FC1_P2/CT0_MAT2/ADC0_B18, label: 'P0_26/J2[10]'}
|
||||
- {pin_num: H10, pin_signal: VDD_P31, label: VDD_P3}
|
||||
- {pin_num: J8, pin_signal: VSS11, label: GND}
|
||||
- {pin_num: K10, pin_signal: VDD_CORE/VOUT_CORE, label: 'VDD_CORE/L2[2]'}
|
||||
- {pin_num: M10, pin_signal: PIO5_2/VBAT_WAKEUP_b/SPC_LPREQ/TAMPER0/ADC1_B10, label: 'P5_2/SJ19[1]'}
|
||||
- {pin_num: N10, pin_signal: PIO4_18/CT3_MAT2/FLEXIO0_D26/PLU_OUT6, label: 'P4_18/J8[23]'}
|
||||
- {pin_num: R10, pin_signal: PIO4_19/TRIG_OUT5/CT3_MAT3/FLEXIO0_D27/PLU_OUT7/SINC0_MCLK_OUT1/OPAMP1_OUT/ADC0_B1/CMP1_IN4P, label: 'P4_19/J8[24]'}
|
||||
- {pin_num: T10, pin_signal: PIO4_20/TRIG_IN8/FC2_P4/CT2_MAT0/FLEXIO0_D28/SINC0_MCLK2/OPAMP2_INP0/ADC1_A6, label: 'P4_20/SJ21[1]/J8[25]'}
|
||||
- {pin_num: U10, pin_signal: OPAMP2_INN, label: 'OPAMP2_INN/RSHUNT_CURC_N/SJ20[1]'}
|
||||
- {pin_num: B11, pin_signal: PIO0_11/CT0_MAT1/FLEXIO0_D3/HSCMP2_OUT/ADC0_B11, label: 'P0_11/J9[18]'}
|
||||
- {pin_num: D11, pin_signal: PIO0_12/FC1_P4/FC0_P0/CT0_MAT2/FLEXIO0_D4/ADC0_B12, label: 'P0_12/J8[9]'}
|
||||
- {pin_num: E11, pin_signal: PIO0_14/FC1_P6/FC0_P2/CT_INP2/UTICK_CAP0/FLEXIO0_D6/ADC0_B14, label: 'P0_14/J4[6]/SJ19[3]'}
|
||||
- {pin_num: G11, pin_signal: VDD_P30, label: VDD_P3}
|
||||
- {pin_num: L11, pin_signal: VDD_CORE, label: 'VDD_CORE/L2[2]'}
|
||||
- {pin_num: N11, pin_signal: PIO5_3/TRIG_IN11/RTC_CLKOUT/TAMPER1/ADC1_B11, label: 'P5_3/SJ18[1]'}
|
||||
- {pin_num: P11, pin_signal: USB1_ID, label: 'HS_USB_ID/Q1[2]'}
|
||||
- {pin_num: T11, pin_signal: PIO4_21/TRIG_IN9/FC2_P5/CT2_MAT1/FLEXIO0_D29/SINC0_MBIT2/OPAMP2_INP1/ADC1_B6, label: 'P4_21/J8[26]'}
|
||||
- {pin_num: A12, pin_signal: PIO0_9/FC0_P5/CT_INP1/FLEXIO0_D1/ADC0_B9, label: 'P0_9/J8[10]'}
|
||||
- {pin_num: B12, pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10, label: 'P0_10/SJ5[1]', identifier: LED_RED}
|
||||
- {pin_num: C12, pin_signal: PIO0_8/FC0_P4/CT_INP0/FLEXIO0_D0/ADC0_B8, label: 'P0_8/J8[11]'}
|
||||
- {pin_num: D9, pin_signal: VSS6, label: GND}
|
||||
- {pin_num: F12, pin_signal: PIO0_13/FC1_P5/FC0_P1/CT0_MAT3/FLEXIO0_D5/ADC0_B13, label: 'P0_13/J8[12]'}
|
||||
- {pin_num: H12, pin_signal: VDD_P42, label: VDD_P3}
|
||||
- {pin_num: K12, pin_signal: PIO5_5/TRIG_IN10/LPTMR0_ALT2/TAMPER3/ADC1_B13, label: 'P5_5/SJ17[3]'}
|
||||
- {pin_num: M12, pin_signal: PIO5_4/TRIG_OUT7/SPC_LPREQ/TAMPER2/ADC1_B12, label: 'P5_4/J2[7]'}
|
||||
- {pin_num: P14, pin_signal: VDD3, label: GND}
|
||||
- {pin_num: R12, pin_signal: VDD_USB, label: VDD_USB}
|
||||
- {pin_num: T12, pin_signal: PIO4_22/CT2_MAT2/FLEXIO0_D30, label: 'P4_22/J8[27]'}
|
||||
- {pin_num: U12, pin_signal: PIO4_23/TRIG_OUT5/FC2_P6/CT2_MAT3/FLEXIO0_D31/SINC0_MCLK_OUT2/OPAMP2_OUT/ADC0_A2/ADC0_B2/ADC1_B3/CMP2_IN4P, label: 'P4_23/J8[28]'}
|
||||
- {pin_num: C13, pin_signal: PIO0_7/WUU0_IN1/FC0_P3/CT_INP3/CMP2_IN1, label: 'P0_7/J8[8]'}
|
||||
- {pin_num: D12, pin_signal: VSS7, label: GND}
|
||||
- {pin_num: G13, pin_signal: PIO0_15/FC0_P3/CT_INP3/UTICK_CAP1/FLEXIO0_D7/ADC0_B15, label: 'P0_15/SJ8[1]'}
|
||||
- {pin_num: H9, pin_signal: VSS9, label: GND}
|
||||
- {pin_num: K13, pin_signal: PIO5_6/TRIG_OUT6/LPTMR1_ALT2/TAMPER4/ADC1_B14, label: 'P5_6/SJ13[1]'}
|
||||
- {pin_num: L13, pin_signal: PIO5_7/TRIG_IN11/TAMPER5/ADC1_B15, label: 'P5_7/J5[2]'}
|
||||
- {pin_num: R13, pin_signal: USB1_DP, label: 'MCX_USB1_DP/L13[3]'}
|
||||
- {pin_num: A14, pin_signal: PIO0_5/EWM0_OUT_b/FC0_P1/FC1_P5/CT0_MAT3/UTICK_CAP3/PDM0_DATA0/TSI0_CH9, label: 'P0_5/SJ13[3]/J9[15]/SJ21[3]'}
|
||||
- {pin_num: B14, pin_signal: PIO0_4/WUU0_IN0/EWM0_IN/FC0_P0/FC1_P4/CT0_MAT2/UTICK_CAP2/HSCMP1_OUT/PDM0_CLK/TSI0_CH8, label: 'P0_4/SJ12[3]/J9[17]/SJ22[3]'}
|
||||
- {pin_num: C14, pin_signal: PIO0_6/ISPMODE_N/FC0_P2/FC1_P6/CT_INP2/HSCMP2_OUT/PDM0_DATA1/CLKOUT/TSI0_CH10, label: 'P0_6/J23[7]/SW3[3]/SW3[4]', identifier: SW3}
|
||||
- {pin_num: D14, pin_signal: PIO3_7/FC6_P6/FC7_P1/CT4_MAT3/PWM0_B1/FLEXIO0_D15/FLEXSPI0_A_SCLK/SIM0_VCCEN/SAI0_MCLK, label: 'P3_7/TP18/U8[6]/U7[B2]'}
|
||||
- {pin_num: E14, pin_signal: PIO3_8/WUU0_IN23/FC6_P4/FC7_P0/CT_INP4/PWM0_A2/FLEXIO0_D16/FLEXSPI0_A_DATA0/SIM0_PD/SAI0_TX_BCLK, label: 'P3_8/TP16/U8[5]/U7[D3]'}
|
||||
- {pin_num: F14, pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, label: 'P3_4/J9[12]'}
|
||||
- {pin_num: G14, pin_signal: PIO3_5/FC7_P3/CT_INP19/PWM0_X3/FLEXIO0_D13/SIM1_IO, label: 'P3_5/J9[11]'}
|
||||
- {pin_num: J10, pin_signal: VSS12, label: GND}
|
||||
- {pin_num: L14, pin_signal: PIO5_8/TRIG_OUT7/TAMPER6/ADC1_B16, label: 'P5_8/U9[19]/J9[31]'}
|
||||
- {pin_num: M14, pin_signal: PIO5_9/TAMPER7/ADC1_B17, label: 'P5_9/J9[29]'}
|
||||
- {pin_num: N14, pin_signal: VDD_SYS, label: VDD_SYS}
|
||||
- {pin_num: T16, pin_signal: VDD4, label: GND}
|
||||
- {pin_num: R14, pin_signal: USB1_DM, label: 'MCX_USB1_DM/L13[2]'}
|
||||
- {pin_num: T14, pin_signal: USB0_DM/WUU0_IN28, label: TP2}
|
||||
- {pin_num: U14, pin_signal: USB1_VBUS, label: MCX_USB1_VBUS}
|
||||
- {pin_num: B15, pin_signal: PIO0_3/TDI/FC1_P3/CT0_MAT1/UTICK_CAP1/HSCMP0_OUT/CMP1_IN1, label: 'P0_3/J23[8]/D16[3]/SJ17[1]'}
|
||||
- {pin_num: C15, pin_signal: PIO3_1/TRIG_IN1/FC6_P0/FC7_P6/CT_INP17/PWM0_B0/FLEXIO0_D9/FLEXSPI0_A_SS1_b/FREQME_CLK_OUT0, label: P3_1/TP31}
|
||||
- {pin_num: D15, pin_signal: PIO3_2/FC7_P0/CT4_MAT0/PWM0_X0/FLEXIO0_D10/SIM1_PD, label: 'P3_2/J9[20]/J7[8]'}
|
||||
- {pin_num: F15, pin_signal: PIO3_9/FC6_P5/FC7_P2/CT_INP5/PWM0_B2/FLEXIO0_D17/FLEXSPI0_A_DATA1/SIM0_RST/SAI0_TX_FS, label: 'P3_9/TP15/U8[2]/U7[D2]'}
|
||||
- {pin_num: H15, pin_signal: PIO3_15/FC8_P1/CT_INP7/PWM1_B1/FLEXIO0_D23/FLEXSPI0_A_DATA7/SAI0_RX_FS, label: 'P3_15/TP9/U7[E1]'}
|
||||
- {pin_num: J15, pin_signal: PIO3_16/FC8_P2/CT_INP8/PWM1_A2/FLEXIO0_D24/SIM0_CLK/SAI1_TX_BCLK, label: 'P3_16/SJ11[1]'}
|
||||
- {pin_num: K15, pin_signal: PIO3_17/WUU0_IN26/FC8_P3/CT_INP9/PWM1_B2/FLEXIO0_D25/SIM0_IO/SAI1_TX_FS, label: 'P3_17/J1[11]/SJ10[3]'}
|
||||
- {pin_num: M15, pin_signal: PIO3_23/FC6_P3/CT_INP11/PWM1_X3/FLEXIO0_D31/SAI1_TXD1, label: 'P3_23/J6[3]'}
|
||||
- {pin_num: P15, pin_signal: VDD_LDO_SYS/VOUT_SYS, label: VDD_LDO_SYS_IN}
|
||||
- {pin_num: R15, pin_signal: VDD_DCDC, label: VDD_DCDC}
|
||||
- {pin_num: T15, pin_signal: USB0_DP/WUU0_IN29, label: TP3}
|
||||
- {pin_num: A16, pin_signal: PIO0_1/TCLK/SWCLK/FC1_P1/CT_INP1, label: 'P0_1/SWCLK/J23[4]/D16[5]/J22[2]', identifier: DEBUG_SWD_SWDCLK}
|
||||
- {pin_num: B16, pin_signal: PIO0_2/TDO/SWO/FC1_P2/CT0_MAT0/UTICK_CAP0/I3C0_PUR, label: 'P0_2/SWO/J23[6]/D16[4]', identifier: DEBUG_SWD_SWO}
|
||||
- {pin_num: D16, pin_signal: PIO3_3/FC7_P1/CT4_MAT1/PWM0_X1/FLEXIO0_D11/SIM1_RST, label: 'P3_3/J9[19]/SJ12[1]'}
|
||||
- {pin_num: F16, pin_signal: PIO3_11/WUU0_IN24/FC6_P3/FC7_P5/CT1_MAT1/PWM0_B3/FLEXIO0_D19/FLEXSPI0_A_DATA3/SIM0_IO/SAI0_RXD0, label: 'P3_11/TP14/U8[7]/U7[D4]'}
|
||||
- {pin_num: G16, pin_signal: PIO3_12/FC7_P4/FC6_P4/CT1_MAT2/PWM1_A0/FLEXIO0_D20/FLEXSPI0_A_DATA4/SAI0_RXD1, label: 'P3_12/TP17/U7[D5]'}
|
||||
- {pin_num: H16, pin_signal: PIO3_13/FC7_P5/FC6_P5/CT1_MAT3/PWM1_B0/FLEXIO0_D21/FLEXSPI0_A_DATA5/SAI0_TXD1, label: 'P3_13/TP11/U7[E3]'}
|
||||
- {pin_num: K16, pin_signal: PIO3_18/FC6_P6/CT2_MAT0/PWM1_X0/FLEXIO0_D26/SAI1_RX_BCLK, label: 'P3_18/J1[9]'}
|
||||
- {pin_num: L16, pin_signal: PIO3_21/TRIG_OUT1/FC8_P5/FC6_P1/CT2_MAT3/PWM1_B3/FLEXIO0_D29/SIM0_RST/SAI1_RXD0, label: 'P3_21/J6[4]/J1[15]'}
|
||||
- {pin_num: M16, pin_signal: PIO3_22/FC8_P6/FC6_P2/CT_INP10/PWM1_X2/FLEXIO0_D30/SIM0_VCCEN/SAI1_RXD1, label: 'P3_22/J6[5]'}
|
||||
- {pin_num: P16, pin_signal: VSS_DCDC, label: GND}
|
||||
- {pin_num: U16, pin_signal: PIO5_0/TRIG_IN10/LPTMR0_ALT2/EXTAL32K/ADC1_B8, label: 'P5_0/EXTAL32K/Y2[2]'}
|
||||
- {pin_num: A17, pin_signal: PIO0_0/TMS/SWDIO/FC1_P0/CT_INP0, label: 'P0_0/SWDIO/J23[2]/D16[6]', identifier: DEBUG_SWD_SWDIO}
|
||||
- {pin_num: B17, pin_signal: PIO3_0/WUU0_IN22/TRIG_IN0/FC7_P3/CT_INP16/PWM0_A0/FLEXIO0_D8/FLEXSPI0_A_SS0_b, label: 'P3_0/TP12/U8[1]/U7[C2]/U7[A3]'}
|
||||
- {pin_num: D17, pin_signal: PIO3_6/CLKOUT/FC6_P1/CT4_MAT2/PWM0_A1/FLEXIO0_D14/FLEXSPI0_A_DQS/SIM1_VCCEN/SAI1_MCLK/FREQME_CLK_OUT1, label: 'P3_6/TP8/U7[C3]'}
|
||||
- {pin_num: F17, pin_signal: PIO3_10/FC6_P2/FC7_P4/CT1_MAT0/PWM0_A3/FLEXIO0_D18/FLEXSPI0_A_DATA2/SIM0_CLK/SAI0_TXD0, label: 'P3_10/TP13/U8[3]/U7[C4]'}
|
||||
- {pin_num: H17, pin_signal: PIO3_14/WUU0_IN25/FC8_P0/CT_INP6/PWM1_A1/FLEXIO0_D22/FLEXSPI0_A_DATA6/SAI0_RX_BCLK, label: 'P3_14/TP10/U7[E2]'}
|
||||
- {pin_num: K17, pin_signal: PIO3_19/FC7_P6/CT2_MAT1/PWM1_X1/FLEXIO0_D27/SAI1_RX_FS, label: 'P3_19/J5[1]/J1[13]'}
|
||||
- {pin_num: M17, pin_signal: PIO3_20/WUU0_IN27/TRIG_OUT0/FC8_P4/FC6_P0/CT2_MAT2/PWM1_A3/FLEXIO0_D28/SIM0_PD/SAI1_TXD0, label: 'P3_20/J6[6]/J1[5]'}
|
||||
- {pin_num: P17, pin_signal: DCDC_LX, label: DCDC_LX}
|
||||
- {pin_num: T17, pin_signal: VDD_BAT, label: 'VDD_BAT/J27[2]'}
|
||||
- {pin_num: U17, pin_signal: PIO5_1/TRIG_OUT6/LPTMR1_ALT2/XTAL32K/ADC1_B9, label: 'P5_1/XTAL32K/Y2[1]'}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_port.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void)
|
||||
{
|
||||
BOARD_InitDEBUG_UARTPins();
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitDEBUG_UARTPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: A1, peripheral: LP_FLEXCOMM4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
|
||||
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
|
||||
invert_input: normal}
|
||||
- {pin_num: B1, peripheral: LP_FLEXCOMM4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
|
||||
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitDEBUG_UARTPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitDEBUG_UARTPins(void)
|
||||
{
|
||||
/* Enables the clock for PORT1: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port1);
|
||||
|
||||
const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as FC4_P0 */
|
||||
kPORT_MuxAlt2,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT1_8 (pin A1) is configured as FC4_P0 */
|
||||
PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
|
||||
|
||||
const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as FC4_P1 */
|
||||
kPORT_MuxAlt2,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT1_9 (pin B1) is configured as FC4_P1 */
|
||||
PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitSWD_DEBUGPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: A16, peripheral: SWD, signal: SWCLK, pin_signal: PIO0_1/TCLK/SWCLK/FC1_P1/CT_INP1, slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down,
|
||||
pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: A17, peripheral: SWD, signal: SWDIO, pin_signal: PIO0_0/TMS/SWDIO/FC1_P0/CT_INP0, slew_rate: fast, open_drain: disable, drive_strength: high, pull_select: up,
|
||||
pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: B16, peripheral: SWD, signal: SWO, pin_signal: PIO0_2/TDO/SWO/FC1_P2/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable, drive_strength: high,
|
||||
pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitSWD_DEBUGPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitSWD_DEBUGPins(void)
|
||||
{
|
||||
/* Enables the clock for PORT0 controller: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port0);
|
||||
|
||||
const port_pin_config_t DEBUG_SWD_SWDIO = {/* Internal pull-up resistor is enabled */
|
||||
kPORT_PullUp,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* High drive strength is configured */
|
||||
kPORT_HighDriveStrength,
|
||||
/* Pin is configured as SWDIO */
|
||||
kPORT_MuxAlt1,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_0 (pin A17) is configured as SWDIO */
|
||||
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, &DEBUG_SWD_SWDIO);
|
||||
|
||||
const port_pin_config_t DEBUG_SWD_SWDCLK = {/* Internal pull-down resistor is enabled */
|
||||
kPORT_PullDown,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as SWCLK */
|
||||
kPORT_MuxAlt1,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_1 (pin A16) is configured as SWCLK */
|
||||
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, &DEBUG_SWD_SWDCLK);
|
||||
|
||||
const port_pin_config_t DEBUG_SWD_SWO = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* High drive strength is configured */
|
||||
kPORT_HighDriveStrength,
|
||||
/* Pin is configured as SWO */
|
||||
kPORT_MuxAlt1,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_2 (pin B16) is configured as SWO */
|
||||
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, &DEBUG_SWD_SWO);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitLEDsPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: C4, peripheral: GPIO1, signal: 'GPIO, 2', pin_signal: PIO1_2/TRIG_OUT0/FC3_P2/FC4_P6/CT1_MAT0/SCT0_IN6/FLEXIO0_D10/ENET0_MDC/SAI1_TXD0/CAN0_TXD/TSI0_CH2/ADC0_A18/CMP2_IN0,
|
||||
direction: OUTPUT, slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: B12, peripheral: GPIO0, signal: 'GPIO, 10', pin_signal: PIO0_10/FC0_P6/CT0_MAT0/FLEXIO0_D2/ADC0_B10, direction: OUTPUT, slew_rate: fast, open_drain: disable,
|
||||
drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: E10, peripheral: GPIO0, signal: 'GPIO, 27', pin_signal: PIO0_27/FC1_P3/CT0_MAT3/ADC0_B19, direction: OUTPUT, slew_rate: fast, open_drain: disable, drive_strength: low,
|
||||
pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitLEDsPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitLEDsPins(void)
|
||||
{
|
||||
/* Enables the clock for GPIO0: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Gpio0);
|
||||
/* Enables the clock for GPIO1: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Gpio1);
|
||||
/* Enables the clock for PORT0 controller: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port0);
|
||||
/* Enables the clock for PORT1: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port1);
|
||||
|
||||
gpio_pin_config_t LED_RED_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_10 (pin B12) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config);
|
||||
|
||||
gpio_pin_config_t LED_GREEN_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_27 (pin E10) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config);
|
||||
|
||||
gpio_pin_config_t LED_BLUE_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO1_2 (pin C4) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config);
|
||||
|
||||
const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as PIO0_10 */
|
||||
kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_10 (pin B12) is configured as PIO0_10 */
|
||||
PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED);
|
||||
|
||||
const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as PIO0_27 */
|
||||
kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_27 (pin E10) is configured as PIO0_27 */
|
||||
PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN);
|
||||
|
||||
const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as PIO1_2 */
|
||||
kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT1_2 (pin C4) is configured as PIO1_2 */
|
||||
PORT_SetPinConfig(BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitBUTTONsPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: C14, peripheral: GPIO0, signal: 'GPIO, 6', pin_signal: PIO0_6/ISPMODE_N/FC0_P2/FC1_P6/CT_INP2/HSCMP2_OUT/PDM0_DATA1/CLKOUT/TSI0_CH10, direction: INPUT,
|
||||
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: B7, peripheral: GPIO0, signal: 'GPIO, 23', pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, direction: INPUT, slew_rate: fast,
|
||||
open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBUTTONsPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBUTTONsPins(void)
|
||||
{
|
||||
/* Enables the clock for GPIO0: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Gpio0);
|
||||
/* Enables the clock for PORT0 controller: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port0);
|
||||
|
||||
gpio_pin_config_t SW3_config = {
|
||||
.pinDirection = kGPIO_DigitalInput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_6 (pin C14) */
|
||||
GPIO_PinInit(BOARD_INITBUTTONSPINS_SW3_GPIO, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3_config);
|
||||
|
||||
gpio_pin_config_t SW2_config = {
|
||||
.pinDirection = kGPIO_DigitalInput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_23 (pin B7) */
|
||||
GPIO_PinInit(BOARD_INITBUTTONSPINS_SW2_GPIO, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2_config);
|
||||
|
||||
const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as PIO0_23 */
|
||||
kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_23 (pin B7) is configured as PIO0_23 */
|
||||
PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW2_PORT, BOARD_INITBUTTONSPINS_SW2_PIN, &SW2);
|
||||
|
||||
const port_pin_config_t SW3 = {/* Internal pull-up resistor is enabled */
|
||||
kPORT_PullUp,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as PIO0_6 */
|
||||
kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT0_6 (pin C14) is configured as PIO0_6 */
|
||||
PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW3_PORT, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@ -1,184 +0,0 @@
|
||||
/*
|
||||
* Copyright 2022-2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/*! @name PORT1_8 (coord A1), P1_8/J9[32]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT PORT1 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 8U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 8U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT1_9 (coord B1), P1_9/J9[30]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT PORT1 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 9U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 9U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitDEBUG_UARTPins(void);
|
||||
|
||||
/*! @name PORT0_1 (coord A16), P0_1/SWCLK/J23[4]/D16[5]/J22[2]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 1U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 1U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_0 (coord A17), P0_0/SWDIO/J23[2]/D16[6]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 0U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_2 (coord B16), P0_2/SWO/J23[6]/D16[4]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 2U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitSWD_DEBUGPins(void);
|
||||
|
||||
/*! @name PORT1_2 (coord C4), P1_2/SJ4[1]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO1 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN 2U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 2U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_PORT PORT1 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_PIN 2U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_10 (coord B12), P0_10/SJ5[1]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO0 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 10U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 10U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PIN 10U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 10U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_27 (coord E10), P0_27/SJ6[1]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO0 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN 27U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 27U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PIN 27U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 27U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitLEDsPins(void);
|
||||
|
||||
/*! @name PORT0_6 (coord C14), P0_6/J23[7]/SW3[3]/SW3[4]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_GPIO GPIO0 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN 6U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_PIN 6U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW3_PIN_MASK (1U << 6U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PORT0_23 (coord B7), P0_23/SJ9[1]/SW2[3]/SW2[4]
|
||||
@{ */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_GPIO GPIO0 /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_GPIO_PIN 23U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_GPIO_PIN_MASK (1U << 23U) /*!<@brief GPIO pin mask */
|
||||
|
||||
/* Symbols to be used with PORT driver */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_PORT PORT0 /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_PIN 23U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITBUTTONSPINS_SW2_PIN_MASK (1U << 23U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBUTTONsPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@ -1,499 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018-2019, 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*! *********************************************************************************
|
||||
*************************************************************************************
|
||||
* Include
|
||||
*************************************************************************************
|
||||
********************************************************************************** */
|
||||
#include "fsl_component_generic_list.h"
|
||||
|
||||
#if defined(OSA_USED)
|
||||
#include "fsl_os_abstraction.h"
|
||||
#if (defined(USE_RTOS) && (USE_RTOS > 0U))
|
||||
#define LIST_ENTER_CRITICAL() \
|
||||
OSA_SR_ALLOC(); \
|
||||
OSA_ENTER_CRITICAL()
|
||||
#define LIST_EXIT_CRITICAL() OSA_EXIT_CRITICAL()
|
||||
#else
|
||||
#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ();
|
||||
#define LIST_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask);
|
||||
#endif
|
||||
#else
|
||||
#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ();
|
||||
#define LIST_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask);
|
||||
#endif
|
||||
|
||||
static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement)
|
||||
{
|
||||
list_status_t listStatus = kLIST_Ok;
|
||||
#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U))
|
||||
list_element_handle_t element = list->head;
|
||||
#endif
|
||||
if ((list->max != 0U) && (list->max == list->size))
|
||||
{
|
||||
listStatus = kLIST_Full; /*List is full*/
|
||||
}
|
||||
#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U))
|
||||
else
|
||||
{
|
||||
while (element != NULL) /*Scan list*/
|
||||
{
|
||||
/* Determine if element is duplicated */
|
||||
if (element == newElement)
|
||||
{
|
||||
listStatus = kLIST_DuplicateError;
|
||||
break;
|
||||
}
|
||||
element = element->next;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return listStatus;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
*************************************************************************************
|
||||
* Public functions
|
||||
*************************************************************************************
|
||||
********************************************************************************** */
|
||||
/*! *********************************************************************************
|
||||
* \brief Initializes the list descriptor.
|
||||
*
|
||||
* \param[in] list - LIST_ handle to init.
|
||||
* max - Maximum number of elements in list. 0 for unlimited.
|
||||
*
|
||||
* \return void.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
void LIST_Init(list_handle_t list, uint32_t max)
|
||||
{
|
||||
list->head = NULL;
|
||||
list->tail = NULL;
|
||||
list->max = max;
|
||||
list->size = 0;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets the list that contains the given element.
|
||||
*
|
||||
* \param[in] element - Handle of the element.
|
||||
*
|
||||
* \return NULL if element is orphan.
|
||||
* Handle of the list the element is inserted into.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_handle_t LIST_GetList(list_element_handle_t listElement)
|
||||
{
|
||||
return listElement->list;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Links element to the tail of the list.
|
||||
*
|
||||
* \param[in] list - ID of list to insert into.
|
||||
* element - element to add
|
||||
*
|
||||
* \return kLIST_Full if list is full.
|
||||
* kLIST_Ok if insertion was successful.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement)
|
||||
{
|
||||
LIST_ENTER_CRITICAL();
|
||||
list_status_t listStatus = kLIST_Ok;
|
||||
|
||||
listStatus = LIST_Error_Check(list, listElement);
|
||||
if (listStatus == kLIST_Ok) /* Avoiding list status error */
|
||||
{
|
||||
if (list->size == 0U)
|
||||
{
|
||||
list->head = listElement;
|
||||
}
|
||||
else
|
||||
{
|
||||
list->tail->next = listElement;
|
||||
}
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
#else
|
||||
listElement->prev = list->tail;
|
||||
#endif
|
||||
listElement->list = list;
|
||||
listElement->next = NULL;
|
||||
list->tail = listElement;
|
||||
list->size++;
|
||||
}
|
||||
|
||||
LIST_EXIT_CRITICAL();
|
||||
return listStatus;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Links element to the head of the list.
|
||||
*
|
||||
* \param[in] list - ID of list to insert into.
|
||||
* element - element to add
|
||||
*
|
||||
* \return kLIST_Full if list is full.
|
||||
* kLIST_Ok if insertion was successful.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement)
|
||||
{
|
||||
LIST_ENTER_CRITICAL();
|
||||
list_status_t listStatus = kLIST_Ok;
|
||||
|
||||
listStatus = LIST_Error_Check(list, listElement);
|
||||
if (listStatus == kLIST_Ok) /* Avoiding list status error */
|
||||
{
|
||||
/* Links element to the head of the list */
|
||||
if (list->size == 0U)
|
||||
{
|
||||
list->tail = listElement;
|
||||
}
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
#else
|
||||
else
|
||||
{
|
||||
list->head->prev = listElement;
|
||||
}
|
||||
listElement->prev = NULL;
|
||||
#endif
|
||||
listElement->list = list;
|
||||
listElement->next = list->head;
|
||||
list->head = listElement;
|
||||
list->size++;
|
||||
}
|
||||
|
||||
LIST_EXIT_CRITICAL();
|
||||
return listStatus;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Unlinks element from the head of the list.
|
||||
*
|
||||
* \param[in] list - ID of list to remove from.
|
||||
*
|
||||
* \return NULL if list is empty.
|
||||
* ID of removed element(pointer) if removal was successful.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_element_handle_t LIST_RemoveHead(list_handle_t list)
|
||||
{
|
||||
list_element_handle_t listElement;
|
||||
|
||||
LIST_ENTER_CRITICAL();
|
||||
|
||||
if ((NULL == list) || (list->size == 0U))
|
||||
{
|
||||
listElement = NULL; /*LIST_ is empty*/
|
||||
}
|
||||
else
|
||||
{
|
||||
listElement = list->head;
|
||||
list->size--;
|
||||
if (list->size == 0U)
|
||||
{
|
||||
list->tail = NULL;
|
||||
}
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
#else
|
||||
else
|
||||
{
|
||||
listElement->next->prev = NULL;
|
||||
}
|
||||
#endif
|
||||
listElement->list = NULL;
|
||||
list->head = listElement->next; /*Is NULL if element is head*/
|
||||
}
|
||||
|
||||
LIST_EXIT_CRITICAL();
|
||||
return listElement;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets head element ID.
|
||||
*
|
||||
* \param[in] list - ID of list.
|
||||
*
|
||||
* \return NULL if list is empty.
|
||||
* ID of head element if list is not empty.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_element_handle_t LIST_GetHead(list_handle_t list)
|
||||
{
|
||||
return list->head;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets next element ID.
|
||||
*
|
||||
* \param[in] element - ID of the element.
|
||||
*
|
||||
* \return NULL if element is tail.
|
||||
* ID of next element if exists.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_element_handle_t LIST_GetNext(list_element_handle_t listElement)
|
||||
{
|
||||
return listElement->next;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets previous element ID.
|
||||
*
|
||||
* \param[in] element - ID of the element.
|
||||
*
|
||||
* \return NULL if element is head.
|
||||
* ID of previous element if exists.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_element_handle_t LIST_GetPrev(list_element_handle_t listElement)
|
||||
{
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
return NULL;
|
||||
#else
|
||||
return listElement->prev;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Unlinks an element from its list.
|
||||
*
|
||||
* \param[in] element - ID of the element to remove.
|
||||
*
|
||||
* \return kLIST_OrphanElement if element is not part of any list.
|
||||
* kLIST_Ok if removal was successful.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_status_t LIST_RemoveElement(list_element_handle_t listElement)
|
||||
{
|
||||
list_status_t listStatus = kLIST_Ok;
|
||||
LIST_ENTER_CRITICAL();
|
||||
|
||||
if (listElement->list == NULL)
|
||||
{
|
||||
listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
|
||||
}
|
||||
else
|
||||
{
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
list_element_handle_t element_list = listElement->list->head;
|
||||
list_element_handle_t element_Prev = NULL;
|
||||
while (NULL != element_list)
|
||||
{
|
||||
if (listElement->list->head == listElement)
|
||||
{
|
||||
listElement->list->head = element_list->next;
|
||||
break;
|
||||
}
|
||||
if (element_list->next == listElement)
|
||||
{
|
||||
element_Prev = element_list;
|
||||
element_list->next = listElement->next;
|
||||
break;
|
||||
}
|
||||
element_list = element_list->next;
|
||||
}
|
||||
if (listElement->next == NULL)
|
||||
{
|
||||
listElement->list->tail = element_Prev;
|
||||
}
|
||||
#else
|
||||
if (listElement->prev == NULL) /*Element is head or solo*/
|
||||
{
|
||||
listElement->list->head = listElement->next; /*is null if solo*/
|
||||
}
|
||||
if (listElement->next == NULL) /*Element is tail or solo*/
|
||||
{
|
||||
listElement->list->tail = listElement->prev; /*is null if solo*/
|
||||
}
|
||||
if (listElement->prev != NULL) /*Element is not head*/
|
||||
{
|
||||
listElement->prev->next = listElement->next;
|
||||
}
|
||||
if (listElement->next != NULL) /*Element is not tail*/
|
||||
{
|
||||
listElement->next->prev = listElement->prev;
|
||||
}
|
||||
#endif
|
||||
listElement->list->size--;
|
||||
listElement->list = NULL;
|
||||
}
|
||||
|
||||
LIST_EXIT_CRITICAL();
|
||||
return listStatus;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Links an element in the previous position relative to a given member
|
||||
* of a list.
|
||||
*
|
||||
* \param[in] element - ID of a member of a list.
|
||||
* newElement - new element to insert before the given member.
|
||||
*
|
||||
* \return kLIST_OrphanElement if element is not part of any list.
|
||||
* kLIST_Full if list is full.
|
||||
* kLIST_Ok if insertion was successful.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement)
|
||||
{
|
||||
list_status_t listStatus = kLIST_Ok;
|
||||
LIST_ENTER_CRITICAL();
|
||||
|
||||
if (listElement->list == NULL)
|
||||
{
|
||||
listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
|
||||
}
|
||||
else
|
||||
{
|
||||
listStatus = LIST_Error_Check(listElement->list, newElement);
|
||||
if (listStatus == kLIST_Ok)
|
||||
{
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
list_element_handle_t element_list = listElement->list->head;
|
||||
while (NULL != element_list)
|
||||
{
|
||||
if ((element_list->next == listElement) || (element_list == listElement))
|
||||
{
|
||||
if (element_list == listElement)
|
||||
{
|
||||
listElement->list->head = newElement;
|
||||
}
|
||||
else
|
||||
{
|
||||
element_list->next = newElement;
|
||||
}
|
||||
newElement->list = listElement->list;
|
||||
newElement->next = listElement;
|
||||
listElement->list->size++;
|
||||
break;
|
||||
}
|
||||
element_list = element_list->next;
|
||||
}
|
||||
|
||||
#else
|
||||
if (listElement->prev == NULL) /*Element is list head*/
|
||||
{
|
||||
listElement->list->head = newElement;
|
||||
}
|
||||
else
|
||||
{
|
||||
listElement->prev->next = newElement;
|
||||
}
|
||||
newElement->list = listElement->list;
|
||||
listElement->list->size++;
|
||||
newElement->next = listElement;
|
||||
newElement->prev = listElement->prev;
|
||||
listElement->prev = newElement;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
LIST_EXIT_CRITICAL();
|
||||
return listStatus;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets the current size of a list.
|
||||
*
|
||||
* \param[in] list - ID of the list.
|
||||
*
|
||||
* \return Current size of the list.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
uint32_t LIST_GetSize(list_handle_t list)
|
||||
{
|
||||
return list->size;
|
||||
}
|
||||
|
||||
/*! *********************************************************************************
|
||||
* \brief Gets the number of free places in the list.
|
||||
*
|
||||
* \param[in] list - ID of the list.
|
||||
*
|
||||
* \return Available size of the list.
|
||||
*
|
||||
* \pre
|
||||
*
|
||||
* \post
|
||||
*
|
||||
* \remarks
|
||||
*
|
||||
********************************************************************************** */
|
||||
uint32_t LIST_GetAvailableSize(list_handle_t list)
|
||||
{
|
||||
return (list->max - list->size); /*Gets the number of free places in the list*/
|
||||
}
|
||||
@ -1,219 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018-2020, 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _GENERIC_LIST_H_
|
||||
#define _GENERIC_LIST_H_
|
||||
|
||||
#ifndef SDK_COMPONENT_DEPENDENCY_FSL_COMMON
|
||||
#define SDK_COMPONENT_DEPENDENCY_FSL_COMMON (1U)
|
||||
#endif
|
||||
#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
|
||||
#include "fsl_common.h"
|
||||
#else
|
||||
#endif
|
||||
/*!
|
||||
* @addtogroup GenericList
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**********************************************************************************
|
||||
* Include
|
||||
***********************************************************************************/
|
||||
|
||||
/**********************************************************************************
|
||||
* Public macro definitions
|
||||
***********************************************************************************/
|
||||
/*! @brief Definition to determine whether use list light. */
|
||||
#ifndef GENERIC_LIST_LIGHT
|
||||
#define GENERIC_LIST_LIGHT (1)
|
||||
#endif
|
||||
|
||||
/*! @brief Definition to determine whether enable list duplicated checking. */
|
||||
#ifndef GENERIC_LIST_DUPLICATED_CHECKING
|
||||
#define GENERIC_LIST_DUPLICATED_CHECKING (0)
|
||||
#endif
|
||||
|
||||
/**********************************************************************************
|
||||
* Public type definitions
|
||||
***********************************************************************************/
|
||||
/*! @brief The list status */
|
||||
#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
|
||||
typedef enum _list_status
|
||||
{
|
||||
kLIST_Ok = kStatus_Success, /*!< Success */
|
||||
kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */
|
||||
kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */
|
||||
kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */
|
||||
kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */
|
||||
kLIST_NotSupport = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support */
|
||||
} list_status_t;
|
||||
#else
|
||||
typedef enum _list_status
|
||||
{
|
||||
kLIST_Ok = 0, /*!< Success */
|
||||
kLIST_DuplicateError = 1, /*!< Duplicate Error */
|
||||
kLIST_Full = 2, /*!< FULL */
|
||||
kLIST_Empty = 3, /*!< Empty */
|
||||
kLIST_OrphanElement = 4, /*!< Orphan Element */
|
||||
kLIST_NotSupport = 5, /*!< Not Support */
|
||||
} list_status_t;
|
||||
#endif
|
||||
|
||||
/*! @brief The list structure*/
|
||||
typedef struct list_label
|
||||
{
|
||||
struct list_element_tag *head; /*!< list head */
|
||||
struct list_element_tag *tail; /*!< list tail */
|
||||
uint32_t size; /*!< list size */
|
||||
uint32_t max; /*!< list max number of elements */
|
||||
} list_label_t, *list_handle_t;
|
||||
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
|
||||
/*! @brief The list element*/
|
||||
typedef struct list_element_tag
|
||||
{
|
||||
struct list_element_tag *next; /*!< next list element */
|
||||
struct list_label *list; /*!< pointer to the list */
|
||||
} list_element_t, *list_element_handle_t;
|
||||
#else
|
||||
/*! @brief The list element*/
|
||||
typedef struct list_element_tag
|
||||
{
|
||||
struct list_element_tag *next; /*!< next list element */
|
||||
struct list_element_tag *prev; /*!< previous list element */
|
||||
struct list_label *list; /*!< pointer to the list */
|
||||
} list_element_t, *list_element_handle_t;
|
||||
#endif
|
||||
/**********************************************************************************
|
||||
* Public prototypes
|
||||
***********************************************************************************/
|
||||
/**********************************************************************************
|
||||
* API
|
||||
**********************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
/*!
|
||||
* @brief Initialize the list.
|
||||
*
|
||||
* This function initialize the list.
|
||||
*
|
||||
* @param list - List handle to initialize.
|
||||
* @param max - Maximum number of elements in list. 0 for unlimited.
|
||||
*/
|
||||
void LIST_Init(list_handle_t list, uint32_t max);
|
||||
|
||||
/*!
|
||||
* @brief Gets the list that contains the given element.
|
||||
*
|
||||
*
|
||||
* @param listElement - Handle of the element.
|
||||
* @retval NULL if element is orphan, Handle of the list the element is inserted into.
|
||||
*/
|
||||
list_handle_t LIST_GetList(list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Links element to the head of the list.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
* @param listElement - Handle of the element.
|
||||
* @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
|
||||
*/
|
||||
list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Links element to the tail of the list.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
* @param listElement - Handle of the element.
|
||||
* @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
|
||||
*/
|
||||
list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Unlinks element from the head of the list.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
*
|
||||
* @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
|
||||
*/
|
||||
list_element_handle_t LIST_RemoveHead(list_handle_t list);
|
||||
|
||||
/*!
|
||||
* @brief Gets head element handle.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
*
|
||||
* @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
|
||||
*/
|
||||
list_element_handle_t LIST_GetHead(list_handle_t list);
|
||||
|
||||
/*!
|
||||
* @brief Gets next element handle for given element handle.
|
||||
*
|
||||
* @param listElement - Handle of the element.
|
||||
*
|
||||
* @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
|
||||
*/
|
||||
list_element_handle_t LIST_GetNext(list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Gets previous element handle for given element handle.
|
||||
*
|
||||
* @param listElement - Handle of the element.
|
||||
*
|
||||
* @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
|
||||
*/
|
||||
list_element_handle_t LIST_GetPrev(list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Unlinks an element from its list.
|
||||
*
|
||||
* @param listElement - Handle of the element.
|
||||
*
|
||||
* @retval kLIST_OrphanElement if element is not part of any list.
|
||||
* @retval kLIST_Ok if removal was successful.
|
||||
*/
|
||||
list_status_t LIST_RemoveElement(list_element_handle_t listElement);
|
||||
|
||||
/*!
|
||||
* @brief Links an element in the previous position relative to a given member of a list.
|
||||
*
|
||||
* @param listElement - Handle of the element.
|
||||
* @param newElement - New element to insert before the given member.
|
||||
*
|
||||
* @retval kLIST_OrphanElement if element is not part of any list.
|
||||
* @retval kLIST_Ok if removal was successful.
|
||||
*/
|
||||
list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement);
|
||||
|
||||
/*!
|
||||
* @brief Gets the current size of a list.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
*
|
||||
* @retval Current size of the list.
|
||||
*/
|
||||
uint32_t LIST_GetSize(list_handle_t list);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of free places in the list.
|
||||
*
|
||||
* @param list - Handle of the list.
|
||||
*
|
||||
* @retval Available size of the list.
|
||||
*/
|
||||
uint32_t LIST_GetAvailableSize(list_handle_t list);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/*! @}*/
|
||||
#endif /*_GENERIC_LIST_H_*/
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,856 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_MANAGER_H__
|
||||
#define __SERIAL_MANAGER_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup serialmanager
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE == 0U))
|
||||
#error When SERIAL_MANAGER_NON_BLOCKING_MODE=0, DEBUG_CONSOLE_TRANSFER_NON_BLOCKING can not be set.
|
||||
#else
|
||||
#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
|
||||
#endif
|
||||
#else
|
||||
#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
|
||||
#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or ring buffer flow control (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL
|
||||
#define SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_UART
|
||||
#define SERIAL_PORT_TYPE_UART (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable uart dma port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_UART_DMA
|
||||
#define SERIAL_PORT_TYPE_UART_DMA (0U)
|
||||
#endif
|
||||
/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_USBCDC
|
||||
#define SERIAL_PORT_TYPE_USBCDC (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_SWO
|
||||
#define SERIAL_PORT_TYPE_SWO (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_VIRTUAL
|
||||
#define SERIAL_PORT_TYPE_VIRTUAL (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable rPMSG port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_RPMSG
|
||||
#define SERIAL_PORT_TYPE_RPMSG (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable SPI Master port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_SPI_MASTER
|
||||
#define SERIAL_PORT_TYPE_SPI_MASTER (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable SPI Slave port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_SPI_SLAVE
|
||||
#define SERIAL_PORT_TYPE_SPI_SLAVE (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable BLE WU port (1 - enable, 0 - disable) */
|
||||
#ifndef SERIAL_PORT_TYPE_BLE_WU
|
||||
#define SERIAL_PORT_TYPE_BLE_WU (0U)
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE == 1U))
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE == 0U))
|
||||
#warning When SERIAL_PORT_TYPE_SPI_SLAVE=1, SERIAL_MANAGER_NON_BLOCKING_MODE should be set.
|
||||
#undef SERIAL_MANAGER_NON_BLOCKING_MODE
|
||||
#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! @brief Set the default delay time in ms used by SerialManager_WriteTimeDelay(). */
|
||||
#ifndef SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE
|
||||
#define SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE (1U)
|
||||
#endif
|
||||
|
||||
/*! @brief Set the default delay time in ms used by SerialManager_ReadTimeDelay(). */
|
||||
#ifndef SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE
|
||||
#define SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE (1U)
|
||||
#endif
|
||||
|
||||
/*! @brief Enable or disable SerialManager_Task() handle RX data available notify */
|
||||
#ifndef SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY
|
||||
#define SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY (0U)
|
||||
#endif
|
||||
#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U))
|
||||
#ifndef OSA_USED
|
||||
#error When SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY=1, OSA_USED must be set.
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! @brief Set serial manager write handle size */
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)
|
||||
#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)
|
||||
#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U)
|
||||
#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE (4U)
|
||||
#else
|
||||
#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)
|
||||
#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)
|
||||
#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U)
|
||||
#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE (4U)
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
|
||||
#include "fsl_component_serial_port_uart.h"
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
#include "fsl_component_serial_port_uart.h"
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
|
||||
#include "fsl_component_serial_port_rpmsg.h"
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
|
||||
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#error The serial manager blocking mode cannot be supported for USB CDC.
|
||||
#endif
|
||||
|
||||
#include "fsl_component_serial_port_usb.h"
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
|
||||
#include "fsl_component_serial_port_swo.h"
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
|
||||
#include "fsl_component_serial_port_spi.h"
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
|
||||
#include "fsl_component_serial_port_spi.h"
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
|
||||
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#error The serial manager blocking mode cannot be supported for USB CDC.
|
||||
#endif
|
||||
|
||||
#include "fsl_component_serial_port_virtual.h"
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
|
||||
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#error The serial manager blocking mode cannot be supported for BLE WU.
|
||||
#endif /* SERIAL_MANAGER_NON_BLOCKING_MODE */
|
||||
|
||||
#include "fsl_component_serial_port_ble_wu.h"
|
||||
#endif /* SERIAL_PORT_TYPE_BLE_WU */
|
||||
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U
|
||||
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
|
||||
|
||||
#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
#if (SERIAL_PORT_UART_DMA_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_DMA_HANDLE_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
|
||||
|
||||
#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
|
||||
|
||||
#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))
|
||||
#if (SERIAL_PORT_SPI_MASTER_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SPI_MASTER_HANDLE_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
|
||||
#if (SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
|
||||
|
||||
#if (SERIAL_PORT_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_VIRTUAL_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
|
||||
|
||||
#if (SERIAL_PORT_RPMSG_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_RPMSG_HANDLE_SIZE
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
|
||||
|
||||
#if (SERIAL_PORT_BLE_WU_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
|
||||
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_BLE_WU_HANDLE_SIZE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */
|
||||
#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))
|
||||
#else
|
||||
#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO, SERIAL_PORT_TYPE_VIRTUAL, and SERIAL_PORT_TYPE_BLE_WU should not be cleared at same time.
|
||||
#endif
|
||||
|
||||
/*! @brief Macro to determine whether use common task. */
|
||||
#ifndef SERIAL_MANAGER_USE_COMMON_TASK
|
||||
#define SERIAL_MANAGER_USE_COMMON_TASK (0U)
|
||||
#endif
|
||||
|
||||
#if defined(OSA_USED)
|
||||
#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
|
||||
#include "fsl_component_common_task.h"
|
||||
#endif
|
||||
/*! @brief Enable or disable SerialManager_Task() handle TX to prevent recursive calling */
|
||||
#ifndef SERIAL_MANAGER_TASK_HANDLE_TX
|
||||
#define SERIAL_MANAGER_TASK_HANDLE_TX (1U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)))
|
||||
#include "fsl_os_abstraction.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! @brief Definition of serial manager handle size. */
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)))
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE \
|
||||
(SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U + OSA_TASK_HANDLE_SIZE + OSA_EVENT_HANDLE_SIZE)
|
||||
#else /*defined(OSA_USED)*/
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U)
|
||||
#endif /*defined(OSA_USED)*/
|
||||
#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 16U)
|
||||
#else
|
||||
#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
|
||||
#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Defines the serial manager handle
|
||||
*
|
||||
* This macro is used to define a 4 byte aligned serial manager handle.
|
||||
* Then use "(serial_handle_t)name" to get the serial manager handle.
|
||||
*
|
||||
* The macro should be global and could be optional. You could also define serial manager handle by yourself.
|
||||
*
|
||||
* This is an example,
|
||||
* @code
|
||||
* SERIAL_MANAGER_HANDLE_DEFINE(serialManagerHandle);
|
||||
* @endcode
|
||||
*
|
||||
* @param name The name string of the serial manager handle.
|
||||
*/
|
||||
#define SERIAL_MANAGER_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
#define SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
/*!
|
||||
* @brief Defines the serial manager write handle
|
||||
*
|
||||
* This macro is used to define a 4 byte aligned serial manager write handle.
|
||||
* Then use "(serial_write_handle_t)name" to get the serial manager write handle.
|
||||
*
|
||||
* The macro should be global and could be optional. You could also define serial manager write handle by yourself.
|
||||
*
|
||||
* This is an example,
|
||||
* @code
|
||||
* SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialManagerwriteHandle);
|
||||
* @endcode
|
||||
*
|
||||
* @param name The name string of the serial manager write handle.
|
||||
*/
|
||||
#define SERIAL_MANAGER_WRITE_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
/*!
|
||||
* @brief Defines the serial manager read handle
|
||||
*
|
||||
* This macro is used to define a 4 byte aligned serial manager read handle.
|
||||
* Then use "(serial_read_handle_t)name" to get the serial manager read handle.
|
||||
*
|
||||
* The macro should be global and could be optional. You could also define serial manager read handle by yourself.
|
||||
*
|
||||
* This is an example,
|
||||
* @code
|
||||
* SERIAL_MANAGER_READ_HANDLE_DEFINE(serialManagerReadHandle);
|
||||
* @endcode
|
||||
*
|
||||
* @param name The name string of the serial manager read handle.
|
||||
*/
|
||||
#define SERIAL_MANAGER_READ_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
#define SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
|
||||
/*! @brief Macro to set serial manager task priority. */
|
||||
#ifndef SERIAL_MANAGER_TASK_PRIORITY
|
||||
#define SERIAL_MANAGER_TASK_PRIORITY (2U)
|
||||
#endif
|
||||
|
||||
/*! @brief Macro to set serial manager task stack size. */
|
||||
#ifndef SERIAL_MANAGER_TASK_STACK_SIZE
|
||||
#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)
|
||||
#endif
|
||||
|
||||
/*! @brief The handle of the serial manager module */
|
||||
typedef void *serial_handle_t;
|
||||
|
||||
/*! @brief The write handle of the serial manager module */
|
||||
typedef void *serial_write_handle_t;
|
||||
|
||||
/*! @brief The read handle of the serial manager module */
|
||||
typedef void *serial_read_handle_t;
|
||||
|
||||
#ifndef _SERIAL_PORT_T_
|
||||
#define _SERIAL_PORT_T_
|
||||
/*! @brief serial port type*/
|
||||
typedef enum _serial_port_type
|
||||
{
|
||||
kSerialPort_None = 0U, /*!< Serial port is none */
|
||||
kSerialPort_Uart = 1U, /*!< Serial port UART */
|
||||
kSerialPort_UsbCdc, /*!< Serial port USB CDC */
|
||||
kSerialPort_Swo, /*!< Serial port SWO */
|
||||
kSerialPort_Virtual, /*!< Serial port Virtual */
|
||||
kSerialPort_Rpmsg, /*!< Serial port RPMSG */
|
||||
kSerialPort_UartDma, /*!< Serial port UART DMA*/
|
||||
kSerialPort_SpiMaster, /*!< Serial port SPIMASTER*/
|
||||
kSerialPort_SpiSlave, /*!< Serial port SPISLAVE*/
|
||||
kSerialPort_BleWu, /*!< Serial port BLE WU */
|
||||
} serial_port_type_t;
|
||||
#endif
|
||||
|
||||
/*! @brief serial manager type*/
|
||||
typedef enum _serial_manager_type
|
||||
{
|
||||
kSerialManager_NonBlocking = 0x0U, /*!< None blocking handle*/
|
||||
kSerialManager_Blocking = 0x8F41U, /*!< Blocking handle*/
|
||||
} serial_manager_type_t;
|
||||
/*! @brief serial manager config structure*/
|
||||
typedef struct _serial_manager_config
|
||||
{
|
||||
#if defined(SERIAL_MANAGER_NON_BLOCKING_MODE)
|
||||
uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware.
|
||||
Besides, the memory space cannot be free during the lifetime of the serial
|
||||
manager module. */
|
||||
uint32_t ringBufferSize; /*!< The size of the ring buffer */
|
||||
#endif
|
||||
serial_port_type_t type; /*!< Serial port type */
|
||||
serial_manager_type_t blockType; /*!< Serial manager port type */
|
||||
void *portConfig; /*!< Serial port configuration */
|
||||
} serial_manager_config_t;
|
||||
|
||||
/*! @brief serial manager error code*/
|
||||
typedef enum _serial_manager_status
|
||||
{
|
||||
kStatus_SerialManager_Success = kStatus_Success, /*!< Success */
|
||||
kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */
|
||||
kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */
|
||||
kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */
|
||||
kStatus_SerialManager_Canceled =
|
||||
MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */
|
||||
kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */
|
||||
kStatus_SerialManager_RingBufferOverflow =
|
||||
MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */
|
||||
kStatus_SerialManager_NotConnected = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 7), /*!< The host is not connected */
|
||||
} serial_manager_status_t;
|
||||
|
||||
/*! @brief Callback message structure */
|
||||
typedef struct _serial_manager_callback_message
|
||||
{
|
||||
uint8_t *buffer; /*!< Transferred buffer */
|
||||
uint32_t length; /*!< Transferred data length */
|
||||
} serial_manager_callback_message_t;
|
||||
|
||||
/*! @brief serial manager callback function */
|
||||
typedef void (*serial_manager_callback_t)(void *callbackParam,
|
||||
serial_manager_callback_message_t *message,
|
||||
serial_manager_status_t status);
|
||||
|
||||
/*! @brief serial manager Lowpower Critical callback function */
|
||||
typedef int32_t (*serial_manager_lowpower_critical_callback_t)(int32_t power_mode);
|
||||
typedef struct _serial_manager_lowpower_critical_CBs_t
|
||||
{
|
||||
serial_manager_lowpower_critical_callback_t serialEnterLowpowerCriticalFunc;
|
||||
serial_manager_lowpower_critical_callback_t serialExitLowpowerCriticalFunc;
|
||||
} serial_manager_lowpower_critical_CBs_t;
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
/*!
|
||||
* @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.
|
||||
*
|
||||
* This function configures the Serial Manager module with user-defined settings.
|
||||
* The user can configure the configuration structure.
|
||||
* The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE
|
||||
* allocated by the caller.
|
||||
* The Serial Manager module supports three types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc), USB
|
||||
* CDC and swo.
|
||||
* Please refer to #serial_port_type_t for serial port setting.
|
||||
* These three types can be set by using #serial_manager_config_t.
|
||||
*
|
||||
* Example below shows how to use this API to configure the Serial Manager.
|
||||
* For UART,
|
||||
* @code
|
||||
* #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
|
||||
* static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle);
|
||||
* static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
|
||||
*
|
||||
* serial_manager_config_t config;
|
||||
* serial_port_uart_config_t uartConfig;
|
||||
* config.type = kSerialPort_Uart;
|
||||
* config.ringBuffer = &s_ringBuffer[0];
|
||||
* config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
|
||||
* uartConfig.instance = 0;
|
||||
* uartConfig.clockRate = 24000000;
|
||||
* uartConfig.baudRate = 115200;
|
||||
* uartConfig.parityMode = kSerialManager_UartParityDisabled;
|
||||
* uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
|
||||
* uartConfig.enableRx = 1;
|
||||
* uartConfig.enableTx = 1;
|
||||
* uartConfig.enableRxRTS = 0;
|
||||
* uartConfig.enableTxCTS = 0;
|
||||
* config.portConfig = &uartConfig;
|
||||
* SerialManager_Init((serial_handle_t)s_serialHandle, &config);
|
||||
* @endcode
|
||||
* For USB CDC,
|
||||
* @code
|
||||
* #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
|
||||
* static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle);
|
||||
* static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
|
||||
*
|
||||
* serial_manager_config_t config;
|
||||
* serial_port_usb_cdc_config_t usbCdcConfig;
|
||||
* config.type = kSerialPort_UsbCdc;
|
||||
* config.ringBuffer = &s_ringBuffer[0];
|
||||
* config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
|
||||
* usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
|
||||
* config.portConfig = &usbCdcConfig;
|
||||
* SerialManager_Init((serial_handle_t)s_serialHandle, &config);
|
||||
* @endcode
|
||||
*
|
||||
* @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* You can define the handle in the following two ways:
|
||||
* #SERIAL_MANAGER_HANDLE_DEFINE(serialHandle);
|
||||
* or
|
||||
* uint32_t serialHandle[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
|
||||
* @param serialConfig Pointer to user-defined configuration structure.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
* @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *serialConfig);
|
||||
|
||||
/*!
|
||||
* @brief De-initializes the serial manager module instance.
|
||||
*
|
||||
* This function de-initializes the serial manager module instance. If the opened writing or
|
||||
* reading handle is not closed, the function will return kStatus_SerialManager_Busy.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.
|
||||
* @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);
|
||||
|
||||
/*!
|
||||
* @brief Opens a writing handle for the serial manager module.
|
||||
*
|
||||
* This function Opens a writing handle for the serial manager module. If the serial manager needs to
|
||||
* be used in different tasks, the task should open a dedicated write handle for itself by calling
|
||||
* #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing
|
||||
* handle at the same time, multiple writing handles need to be opened when the multiple transmission
|
||||
* is needed for a task.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* @param writeHandle The serial manager module writing handle pointer.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* You can define the handle in the following two ways:
|
||||
* #SERIAL_MANAGER_WRITE_HANDLE_DEFINE(writeHandle);
|
||||
* or
|
||||
* uint32_t writeHandle[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
* @retval kStatus_SerialManager_HandleConflict The writing handle was opened.
|
||||
* @retval kStatus_SerialManager_Success The writing handle is opened.
|
||||
*
|
||||
* Example below shows how to use this API to write data.
|
||||
* For task 1,
|
||||
* @code
|
||||
* static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle1);
|
||||
* static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n";
|
||||
* SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle1);
|
||||
* SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle1,
|
||||
* Task1_SerialManagerTxCallback,
|
||||
* s_serialWriteHandle1);
|
||||
* SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle1,
|
||||
* s_nonBlockingWelcome1,
|
||||
* sizeof(s_nonBlockingWelcome1) - 1U);
|
||||
* @endcode
|
||||
* For task 2,
|
||||
* @code
|
||||
* static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle2);
|
||||
* static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n";
|
||||
* SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle2);
|
||||
* SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle2,
|
||||
* Task2_SerialManagerTxCallback,
|
||||
* s_serialWriteHandle2);
|
||||
* SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle2,
|
||||
* s_nonBlockingWelcome2,
|
||||
* sizeof(s_nonBlockingWelcome2) - 1U);
|
||||
* @endcode
|
||||
*/
|
||||
serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);
|
||||
|
||||
/*!
|
||||
* @brief Closes a writing handle for the serial manager module.
|
||||
*
|
||||
* This function Closes a writing handle for the serial manager module.
|
||||
*
|
||||
* @param writeHandle The serial manager module writing handle pointer.
|
||||
* @retval kStatus_SerialManager_Success The writing handle is closed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);
|
||||
|
||||
/*!
|
||||
* @brief Opens a reading handle for the serial manager module.
|
||||
*
|
||||
* This function Opens a reading handle for the serial manager module. The reading handle can not be
|
||||
* opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when
|
||||
* the previous reading handle is not closed. And there can only be one buffer for receiving for the
|
||||
* reading handle at the same time.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* @param readHandle The serial manager module reading handle pointer.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* You can define the handle in the following two ways:
|
||||
* #SERIAL_MANAGER_READ_HANDLE_DEFINE(readHandle);
|
||||
* or
|
||||
* uint32_t readHandle[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
* @retval kStatus_SerialManager_Success The reading handle is opened.
|
||||
* @retval kStatus_SerialManager_Busy Previous reading handle is not closed.
|
||||
*
|
||||
* Example below shows how to use this API to read data.
|
||||
* @code
|
||||
* static SERIAL_MANAGER_READ_HANDLE_DEFINE(s_serialReadHandle);
|
||||
* SerialManager_OpenReadHandle((serial_handle_t)serialHandle, (serial_read_handle_t)s_serialReadHandle);
|
||||
* static uint8_t s_nonBlockingBuffer[64];
|
||||
* SerialManager_InstallRxCallback((serial_read_handle_t)s_serialReadHandle,
|
||||
* APP_SerialManagerRxCallback,
|
||||
* s_serialReadHandle);
|
||||
* SerialManager_ReadNonBlocking((serial_read_handle_t)s_serialReadHandle,
|
||||
* s_nonBlockingBuffer,
|
||||
* sizeof(s_nonBlockingBuffer));
|
||||
* @endcode
|
||||
*/
|
||||
serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);
|
||||
|
||||
/*!
|
||||
* @brief Closes a reading for the serial manager module.
|
||||
*
|
||||
* This function Closes a reading for the serial manager module.
|
||||
*
|
||||
* @param readHandle The serial manager module reading handle pointer.
|
||||
* @retval kStatus_SerialManager_Success The reading handle is closed.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);
|
||||
|
||||
/*!
|
||||
* @brief Transmits data with the blocking mode.
|
||||
*
|
||||
* This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.
|
||||
* This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for transmission for the writing handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_WriteBlocking and the function SerialManager_WriteNonBlocking
|
||||
* cannot be used at the same time.
|
||||
* And, the function SerialManager_CancelWriting cannot be used to abort the transmission of this function.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to write.
|
||||
* @param length Length of the data to write.
|
||||
* @retval kStatus_SerialManager_Success Successfully sent all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length);
|
||||
|
||||
/*!
|
||||
* @brief Reads data with the blocking mode.
|
||||
*
|
||||
* This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.
|
||||
* This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for receiving for the reading handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_ReadBlocking and the function SerialManager_ReadNonBlocking
|
||||
* cannot be used at the same time.
|
||||
* And, the function SerialManager_CancelReading cannot be used to abort the transmission of this function.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to store the received data.
|
||||
* @param length The length of the data to be received.
|
||||
* @retval kStatus_SerialManager_Success Successfully received all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
/*!
|
||||
* @brief Transmits data with the non-blocking mode.
|
||||
*
|
||||
* This is a non-blocking function, which returns directly without waiting for all data to be sent.
|
||||
* When all data is sent, the module notifies the upper layer through a TX callback function and passes
|
||||
* the status parameter @ref kStatus_SerialManager_Success.
|
||||
* This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for transmission for the writing handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
|
||||
* cannot be used at the same time. And, the TX callback is mandatory before the function could be used.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to write.
|
||||
* @param length Length of the data to write.
|
||||
* @retval kStatus_SerialManager_Success Successfully sent all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length);
|
||||
|
||||
/*!
|
||||
* @brief Reads data with the non-blocking mode.
|
||||
*
|
||||
* This is a non-blocking function, which returns directly without waiting for all data to be received.
|
||||
* When all data is received, the module driver notifies the upper layer
|
||||
* through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.
|
||||
* This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
|
||||
* And There can only one buffer for receiving for the reading handle at the same time.
|
||||
*
|
||||
* @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
|
||||
* cannot be used at the same time. And, the RX callback is mandatory before the function could be used.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to store the received data.
|
||||
* @param length The length of the data to be received.
|
||||
* @retval kStatus_SerialManager_Success Successfully received all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length);
|
||||
|
||||
/*!
|
||||
* @brief Tries to read data.
|
||||
*
|
||||
* The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be
|
||||
* copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.
|
||||
* After the data is copied, the actual data length is passed by the parameter length.
|
||||
* And There can only one buffer for receiving for the reading handle at the same time.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param buffer Start address of the data to store the received data.
|
||||
* @param length The length of the data to be received.
|
||||
* @param receivedLength Length received from the ring buffer directly.
|
||||
* @retval kStatus_SerialManager_Success Successfully received all data.
|
||||
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t length,
|
||||
uint32_t *receivedLength);
|
||||
|
||||
/*!
|
||||
* @brief Cancels unfinished send transmission.
|
||||
*
|
||||
* The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer
|
||||
* through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
|
||||
*
|
||||
* @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of
|
||||
* the function #SerialManager_WriteBlocking.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Get successfully abort the sending.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);
|
||||
|
||||
/*!
|
||||
* @brief Cancels unfinished receive transmission.
|
||||
*
|
||||
* The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper
|
||||
* layer
|
||||
* through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
|
||||
*
|
||||
* @note The function #SerialManager_CancelReading cannot be used to abort the transmission of
|
||||
* the function #SerialManager_ReadBlocking.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Get successfully abort the receiving.
|
||||
* @retval kStatus_SerialManager_Error An error occurred.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);
|
||||
|
||||
/*!
|
||||
* @brief Installs a TX callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the TX callback and callback parameter for the serial manager module.
|
||||
* When any status of TX transmission changed, the driver will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param writeHandle The serial manager module handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_SerialManager_Success Successfully install the callback.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Installs a RX callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the RX callback and callback parameter for the serial manager module.
|
||||
* When any status of RX transmission changed, the driver will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param readHandle The serial manager module handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_SerialManager_Success Successfully install the callback.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Check if need polling ISR.
|
||||
*
|
||||
* This function is used to check if need polling ISR.
|
||||
*
|
||||
* @retval TRUE if need polling.
|
||||
*/
|
||||
static inline bool SerialManager_needPollingIsr(void)
|
||||
{
|
||||
#if (defined(__DSC__) && defined(__CW__))
|
||||
return !(isIRQAllowed());
|
||||
#elif defined(CPSR_M_Msk)
|
||||
return (0x13 == (__get_CPSR() & CPSR_M_Msk));
|
||||
#elif defined(DAIF_I_BIT)
|
||||
return (__get_DAIF() & DAIF_I_BIT);
|
||||
#elif defined(__XCC__)
|
||||
return (xthal_get_interrupt() & xthal_get_intenable());
|
||||
#else
|
||||
return (0U != __get_IPSR());
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Prepares to enter low power consumption.
|
||||
*
|
||||
* This function is used to prepare to enter low power consumption.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Successful operation.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);
|
||||
|
||||
/*!
|
||||
* @brief Restores from low power consumption.
|
||||
*
|
||||
* This function is used to restore from low power consumption.
|
||||
*
|
||||
* @param serialHandle The serial manager module handle pointer.
|
||||
* @retval kStatus_SerialManager_Success Successful operation.
|
||||
*/
|
||||
serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);
|
||||
|
||||
/*!
|
||||
* @brief This function performs initialization of the callbacks structure used to disable lowpower
|
||||
* when serial manager is active.
|
||||
*
|
||||
*
|
||||
* @param pfCallback Pointer to the function structure used to allow/disable lowpower.
|
||||
*
|
||||
*/
|
||||
void SerialManager_SetLowpowerCriticalCb(const serial_manager_lowpower_critical_CBs_t *pfCallback);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/*! @} */
|
||||
#endif /* __SERIAL_MANAGER_H__ */
|
||||
@ -1,189 +0,0 @@
|
||||
/*
|
||||
* Copyright 2019-2020, 2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_PORT_INTERNAL_H__
|
||||
#define __SERIAL_PORT_INTERNAL_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
|
||||
serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);
|
||||
serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_UartIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle);
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
serial_manager_status_t Serial_UartDmaInit(serial_handle_t serialHandle, void *serialConfig);
|
||||
serial_manager_status_t Serial_UartDmaDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartDmaWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_UartDmaCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartDmaInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_UartDmaInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_UartDmaIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
serial_manager_status_t Serial_UartDmaEnterLowpower(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UartDmaExitLowpower(serial_handle_t serialHandle);
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U))
|
||||
serial_manager_status_t Serial_RpmsgInit(serial_handle_t serialHandle, void *serialConfig);
|
||||
serial_manager_status_t Serial_RpmsgDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_RpmsgWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_RpmsgWriteBlocking(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_RpmsgRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_RpmsgCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_RpmsgInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_RpmsgInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
#endif
|
||||
serial_manager_status_t Serial_RpmsgEnterLowpower(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_RpmsgExitLowpower(serial_handle_t serialHandle);
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
|
||||
serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);
|
||||
serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
|
||||
serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);
|
||||
serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#endif
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_SwoIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U))
|
||||
serial_manager_status_t Serial_PortVirtualInit(serial_handle_t serialHandle, void *config);
|
||||
serial_manager_status_t Serial_PortVirtualDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_PortVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_PortVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_PortVirtualCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_PortVirtualInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_PortVirtualInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_PortVirtualIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && SERIAL_PORT_TYPE_SPI_MASTER > 0U)
|
||||
serial_manager_status_t Serial_SpiMasterInit(serial_handle_t serialHandle, void *serialConfig);
|
||||
serial_manager_status_t Serial_SpiMasterDeinit(serial_handle_t serialHandle);
|
||||
void Serial_SpiMasterTxCallback(hal_spi_master_handle_t handle, hal_spi_status_t status, void *callbackParam);
|
||||
void Serial_SpiMasterRxCallback(hal_spi_master_handle_t handle, hal_spi_status_t status, void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiMasterWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_SpiMasterRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_SpiMasterInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiMasterInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiMasterCancelWrite(serial_handle_t serialHandle);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))
|
||||
serial_manager_status_t Serial_SpiSlaveInit(serial_handle_t serialHandle, void *serialConfig);
|
||||
serial_manager_status_t Serial_SpiSlaveDeinit(serial_handle_t serialHandle);
|
||||
void Serial_SpiSlaveTxCallback(hal_spi_slave_handle_t handle, hal_spi_status_t status, void *callbackParam);
|
||||
void Serial_SpiSlaveRxCallback(hal_spi_slave_handle_t handle, hal_spi_status_t status, void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiSlaveWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_SpiSlaveRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_SpiSlaveInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiSlaveInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_SpiSlaveCancelWrite(serial_handle_t serialHandle);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U))
|
||||
serial_manager_status_t Serial_PortBleWuInit(serial_handle_t serialHandle, void *config);
|
||||
serial_manager_status_t Serial_PortBleWuDeinit(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_PortBleWuWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_PortBleWuRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
|
||||
serial_manager_status_t Serial_PortBleWuCancelWrite(serial_handle_t serialHandle);
|
||||
serial_manager_status_t Serial_PortBleWuInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
serial_manager_status_t Serial_PortBleWuInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam);
|
||||
void Serial_PortBleWuIsrFunction(serial_handle_t serialHandle);
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SERIAL_PORT_INTERNAL_H__ */
|
||||
@ -1,717 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018 -2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_component_serial_manager.h"
|
||||
#include "fsl_component_serial_port_internal.h"
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) || \
|
||||
(defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
#include "fsl_adapter_uart.h"
|
||||
|
||||
#include "fsl_component_serial_port_uart.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#ifndef NDEBUG
|
||||
#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
|
||||
#undef assert
|
||||
#define assert(n)
|
||||
#else
|
||||
/* MISRA C-2012 Rule 17.2 */
|
||||
#undef assert
|
||||
#define assert(n) \
|
||||
while (!(n)) \
|
||||
{ \
|
||||
; \
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U
|
||||
typedef struct _serial_uart_send_state
|
||||
{
|
||||
uint8_t *buffer;
|
||||
uint32_t length;
|
||||
serial_manager_callback_t callback;
|
||||
void *callbackParam;
|
||||
volatile uint8_t busy;
|
||||
} serial_uart_send_state_t;
|
||||
|
||||
typedef struct _serial_uart_recv_state
|
||||
{
|
||||
serial_manager_callback_t callback;
|
||||
void *callbackParam;
|
||||
volatile uint8_t busy;
|
||||
volatile uint8_t rxEnable;
|
||||
uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH];
|
||||
} serial_uart_recv_state_t;
|
||||
|
||||
typedef struct _serial_uart_dma_recv_state
|
||||
{
|
||||
serial_manager_callback_t callback;
|
||||
void *callbackParam;
|
||||
volatile uint8_t busy;
|
||||
volatile uint8_t rxEnable;
|
||||
uint8_t readBuffer[SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH];
|
||||
} serial_uart_dma_recv_state_t;
|
||||
|
||||
typedef struct _serial_uart_block_state
|
||||
{
|
||||
UART_HANDLE_DEFINE(usartHandleBuffer);
|
||||
} serial_uart_block_state_t;
|
||||
#endif
|
||||
|
||||
typedef struct _serial_uart_state
|
||||
{
|
||||
UART_HANDLE_DEFINE(usartHandleBuffer);
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_uart_send_state_t tx;
|
||||
serial_uart_recv_state_t rx;
|
||||
#endif
|
||||
} serial_uart_state_t;
|
||||
#endif
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
typedef struct _serial_uart_dma_state
|
||||
{
|
||||
UART_HANDLE_DEFINE(usartHandleBuffer);
|
||||
UART_DMA_HANDLE_DEFINE(uartDmaHandle);
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_uart_send_state_t tx;
|
||||
serial_uart_dma_recv_state_t rx;
|
||||
#endif
|
||||
} serial_uart_dma_state_t;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
static serial_manager_status_t Serial_UartEnableReceiving(serial_uart_state_t *serialUartHandle)
|
||||
{
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
hal_uart_transfer_t transfer;
|
||||
#endif
|
||||
if (1U == serialUartHandle->rx.rxEnable)
|
||||
{
|
||||
serialUartHandle->rx.busy = 1U;
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
transfer.data = &serialUartHandle->rx.readBuffer[0];
|
||||
transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
|
||||
if (kStatus_HAL_UartSuccess !=
|
||||
HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
|
||||
#else
|
||||
if (kStatus_HAL_UartSuccess !=
|
||||
HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
&serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
|
||||
#endif
|
||||
{
|
||||
serialUartHandle->rx.busy = 0U;
|
||||
return kStatus_SerialManager_Error;
|
||||
}
|
||||
}
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
/* UART user callback */
|
||||
static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
serial_manager_callback_message_t serialMsg;
|
||||
|
||||
assert(userData);
|
||||
serialUartHandle = (serial_uart_state_t *)userData;
|
||||
|
||||
if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status)
|
||||
{
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
(void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#else
|
||||
(void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#endif
|
||||
if ((NULL != serialUartHandle->rx.callback))
|
||||
{
|
||||
serialMsg.buffer = &serialUartHandle->rx.readBuffer[0];
|
||||
serialMsg.length = sizeof(serialUartHandle->rx.readBuffer);
|
||||
serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &serialMsg,
|
||||
kStatus_SerialManager_Success);
|
||||
}
|
||||
}
|
||||
else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status)
|
||||
{
|
||||
if (0U != serialUartHandle->tx.busy)
|
||||
{
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
if ((NULL != serialUartHandle->tx.callback))
|
||||
{
|
||||
serialMsg.buffer = serialUartHandle->tx.buffer;
|
||||
serialMsg.length = serialUartHandle->tx.length;
|
||||
serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg,
|
||||
kStatus_SerialManager_Success);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_port_uart_config_t *uartConfig = (serial_port_uart_config_t *)serialConfig;
|
||||
#endif
|
||||
serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success;
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
#if 0 /* Not used below! */
|
||||
hal_uart_transfer_t transfer;
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
assert(serialConfig);
|
||||
assert(serialHandle);
|
||||
assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t));
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
serialManagerStatus = (serial_manager_status_t)HAL_UartInit(
|
||||
((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), (const hal_uart_config_t *)serialConfig);
|
||||
assert(kStatus_SerialManager_Success == serialManagerStatus);
|
||||
(void)serialManagerStatus;
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serialUartHandle->rx.rxEnable = uartConfig->enableRx;
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
|
||||
(void)HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
Serial_UartCallback, serialUartHandle);
|
||||
#else
|
||||
(void)HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), Serial_UartCallback,
|
||||
serialUartHandle);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return serialManagerStatus;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
(void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#else
|
||||
(void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#endif
|
||||
#endif
|
||||
(void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
serialUartHandle->rx.busy = 0U;
|
||||
#endif
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
|
||||
serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
hal_uart_status_t uartstatus;
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
hal_uart_transfer_t transfer;
|
||||
#endif
|
||||
|
||||
assert(serialHandle);
|
||||
assert(buffer);
|
||||
assert(length);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
if (0U != serialUartHandle->tx.busy)
|
||||
{
|
||||
return kStatus_SerialManager_Busy;
|
||||
}
|
||||
serialUartHandle->tx.busy = 1U;
|
||||
|
||||
serialUartHandle->tx.buffer = buffer;
|
||||
serialUartHandle->tx.length = length;
|
||||
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
transfer.data = buffer;
|
||||
transfer.dataSize = length;
|
||||
uartstatus =
|
||||
HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer);
|
||||
#else
|
||||
|
||||
uartstatus = HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
|
||||
#endif
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
assert(serialHandle);
|
||||
(void)buffer;
|
||||
(void)length;
|
||||
return (serial_manager_status_t)Serial_UartEnableReceiving(serialHandle);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
assert(buffer);
|
||||
assert(length);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
buffer, length);
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
assert(buffer);
|
||||
assert(length);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
return (serial_manager_status_t)HAL_UartReceiveBlocking(
|
||||
((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
serial_manager_callback_message_t serialMsg;
|
||||
uint32_t primask;
|
||||
uint8_t isBusy = 0U;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
primask = DisableGlobalIRQ();
|
||||
isBusy = serialUartHandle->tx.busy;
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
EnableGlobalIRQ(primask);
|
||||
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
(void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#else
|
||||
(void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
#endif
|
||||
if (0U != isBusy)
|
||||
{
|
||||
if ((NULL != serialUartHandle->tx.callback))
|
||||
{
|
||||
serialMsg.buffer = serialUartHandle->tx.buffer;
|
||||
serialMsg.length = serialUartHandle->tx.length;
|
||||
serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg,
|
||||
kStatus_SerialManager_Canceled);
|
||||
}
|
||||
}
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
serialUartHandle->tx.callback = callback;
|
||||
serialUartHandle->tx.callbackParam = callbackParam;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
serialUartHandle->rx.callback = callback;
|
||||
serialUartHandle->rx.callbackParam = callbackParam;
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
(void)Serial_UartEnableReceiving(serialUartHandle);
|
||||
#endif
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
void Serial_UartIsrFunction(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
}
|
||||
#endif
|
||||
|
||||
serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
hal_uart_status_t uartstatus;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
uartstatus = HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_state_t *serialUartHandle;
|
||||
serial_manager_status_t status = kStatus_SerialManager_Success;
|
||||
hal_uart_status_t uartstatus;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_state_t *)serialHandle;
|
||||
|
||||
uartstatus = HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
status = Serial_UartEnableReceiving(serialUartHandle);
|
||||
#endif
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
static serial_manager_status_t Serial_UartDmaEnableReceiving(serial_uart_dma_state_t *serialUartHandle)
|
||||
{
|
||||
if (1U == serialUartHandle->rx.rxEnable)
|
||||
{
|
||||
serialUartHandle->rx.busy = 1U;
|
||||
if (kStatus_HAL_UartDmaSuccess !=
|
||||
HAL_UartDMATransferReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
&serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer),
|
||||
false))
|
||||
|
||||
{
|
||||
serialUartHandle->rx.busy = 0U;
|
||||
return kStatus_SerialManager_Error;
|
||||
}
|
||||
}
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
/* UART user callback */
|
||||
static void Serial_UartDmaCallback(hal_uart_dma_handle_t handle, hal_dma_callback_msg_t *dmaMsg, void *callbackParam)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
serial_manager_callback_message_t cb_msg;
|
||||
|
||||
assert(callbackParam);
|
||||
serialUartHandle = (serial_uart_dma_state_t *)callbackParam;
|
||||
|
||||
if (((hal_uart_dma_status_t)kStatus_HAL_UartDmaRxIdle == dmaMsg->status) ||
|
||||
(kStatus_HAL_UartDmaIdleline == dmaMsg->status))
|
||||
{
|
||||
if ((NULL != serialUartHandle->rx.callback))
|
||||
{
|
||||
cb_msg.buffer = dmaMsg->data;
|
||||
cb_msg.length = dmaMsg->dataSize;
|
||||
serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &cb_msg, kStatus_SerialManager_Success);
|
||||
}
|
||||
|
||||
if (kStatus_HAL_UartDmaSuccess ==
|
||||
HAL_UartDMATransferReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
&serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer),
|
||||
false))
|
||||
{
|
||||
serialUartHandle->rx.busy = 1U;
|
||||
}
|
||||
}
|
||||
else if (kStatus_HAL_UartDmaTxIdle == dmaMsg->status)
|
||||
{
|
||||
if (0U != serialUartHandle->tx.busy)
|
||||
{
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
if ((NULL != serialUartHandle->tx.callback))
|
||||
{
|
||||
cb_msg.buffer = dmaMsg->data;
|
||||
cb_msg.length = dmaMsg->dataSize;
|
||||
serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &cb_msg,
|
||||
kStatus_SerialManager_Success);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
serial_manager_status_t Serial_UartDmaInit(serial_handle_t serialHandle, void *serialConfig)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
serial_port_uart_dma_config_t *uartConfig = (serial_port_uart_dma_config_t *)serialConfig;
|
||||
#endif
|
||||
serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success;
|
||||
|
||||
assert(serialConfig);
|
||||
assert(serialHandle);
|
||||
|
||||
assert(SERIAL_PORT_UART_DMA_HANDLE_SIZE >= sizeof(serial_uart_dma_state_t));
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
serialManagerStatus = (serial_manager_status_t)HAL_UartInit(
|
||||
((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), (const hal_uart_config_t *)serialConfig);
|
||||
assert(kStatus_SerialManager_Success == serialManagerStatus);
|
||||
(void)serialManagerStatus;
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
|
||||
hal_uart_dma_config_t dmaConfig;
|
||||
|
||||
dmaConfig.uart_instance = uartConfig->instance;
|
||||
dmaConfig.dma_instance = uartConfig->dma_instance;
|
||||
dmaConfig.rx_channel = uartConfig->rx_channel;
|
||||
dmaConfig.tx_channel = uartConfig->tx_channel;
|
||||
dmaConfig.dma_mux_configure = uartConfig->dma_mux_configure;
|
||||
dmaConfig.dma_channel_mux_configure = uartConfig->dma_channel_mux_configure;
|
||||
|
||||
// Init uart dma
|
||||
(void)HAL_UartDMAInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
(hal_uart_dma_handle_t *)serialUartHandle->uartDmaHandle, &dmaConfig);
|
||||
|
||||
#endif
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
|
||||
serialUartHandle->rx.rxEnable = uartConfig->enableRx;
|
||||
(void)HAL_UartDMATransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
|
||||
Serial_UartDmaCallback, serialUartHandle);
|
||||
|
||||
#endif
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serialManagerStatus = Serial_UartDmaEnableReceiving(serialUartHandle);
|
||||
#endif
|
||||
|
||||
return serialManagerStatus;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartDmaDeinit(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
(void)HAL_UartDMAAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
|
||||
(void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
(void)HAL_UartDMADeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
serialUartHandle->rx.busy = 0U;
|
||||
#endif
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
|
||||
serial_manager_status_t Serial_UartDmaWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
hal_uart_status_t uartstatus;
|
||||
|
||||
assert(serialHandle);
|
||||
assert(buffer);
|
||||
assert(length);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
if (0U != serialUartHandle->tx.busy)
|
||||
{
|
||||
return kStatus_SerialManager_Busy;
|
||||
}
|
||||
serialUartHandle->tx.busy = 1U;
|
||||
|
||||
serialUartHandle->tx.buffer = buffer;
|
||||
serialUartHandle->tx.length = length;
|
||||
|
||||
uartstatus = (hal_uart_status_t)HAL_UartDMATransferSend(
|
||||
((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
|
||||
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
serial_manager_status_t Serial_UartDmaCancelWrite(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
serial_manager_callback_message_t serialMsg;
|
||||
uint32_t primask;
|
||||
uint8_t isBusy = 0U;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
primask = DisableGlobalIRQ();
|
||||
isBusy = serialUartHandle->tx.busy;
|
||||
serialUartHandle->tx.busy = 0U;
|
||||
EnableGlobalIRQ(primask);
|
||||
|
||||
(void)HAL_UartDMAAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
|
||||
if (0U != isBusy)
|
||||
{
|
||||
if ((NULL != serialUartHandle->tx.callback))
|
||||
{
|
||||
serialMsg.buffer = serialUartHandle->tx.buffer;
|
||||
serialMsg.length = serialUartHandle->tx.length;
|
||||
serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg,
|
||||
kStatus_SerialManager_Canceled);
|
||||
}
|
||||
}
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartDmaInstallTxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
serialUartHandle->tx.callback = callback;
|
||||
serialUartHandle->tx.callbackParam = callbackParam;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartDmaInstallRxCallback(serial_handle_t serialHandle,
|
||||
serial_manager_callback_t callback,
|
||||
void *callbackParam)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
serialUartHandle->rx.callback = callback;
|
||||
serialUartHandle->rx.callbackParam = callbackParam;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
void Serial_UartDmaIsrFunction(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
}
|
||||
#endif
|
||||
|
||||
serial_manager_status_t Serial_UartDmaEnterLowpower(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
hal_uart_status_t uartstatus;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
uartstatus = HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
return kStatus_SerialManager_Success;
|
||||
}
|
||||
|
||||
serial_manager_status_t Serial_UartDmaExitLowpower(serial_handle_t serialHandle)
|
||||
{
|
||||
serial_uart_dma_state_t *serialUartHandle;
|
||||
serial_manager_status_t status = kStatus_SerialManager_Success;
|
||||
hal_uart_status_t uartstatus;
|
||||
|
||||
assert(serialHandle);
|
||||
|
||||
serialUartHandle = (serial_uart_dma_state_t *)serialHandle;
|
||||
|
||||
uartstatus = HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
|
||||
assert(kStatus_HAL_UartSuccess == uartstatus);
|
||||
(void)uartstatus;
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@ -1,106 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_PORT_UART_H__
|
||||
#define __SERIAL_PORT_UART_H__
|
||||
|
||||
#include "fsl_adapter_uart.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup serial_port_uart
|
||||
* @ingroup serialmanager
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief serial port uart handle size*/
|
||||
|
||||
#ifndef SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH
|
||||
#define SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH (64U)
|
||||
#endif
|
||||
|
||||
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
|
||||
|
||||
#define SERIAL_PORT_UART_HANDLE_SIZE (76U + HAL_UART_HANDLE_SIZE)
|
||||
#define SERIAL_PORT_UART_BLOCK_HANDLE_SIZE (HAL_UART_BLOCK_HANDLE_SIZE)
|
||||
#else
|
||||
#define SERIAL_PORT_UART_HANDLE_SIZE (HAL_UART_HANDLE_SIZE)
|
||||
#endif
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
#define SERIAL_PORT_UART_DMA_HANDLE_SIZE (76U + HAL_UART_DMA_HANDLE_SIZE + 132U)
|
||||
#endif
|
||||
|
||||
#ifndef SERIAL_USE_CONFIGURE_STRUCTURE
|
||||
#define SERIAL_USE_CONFIGURE_STRUCTURE (0U) /*!< Enable or disable the confgure structure pointer */
|
||||
#endif
|
||||
|
||||
/*! @brief serial port uart parity mode*/
|
||||
typedef enum _serial_port_uart_parity_mode
|
||||
{
|
||||
kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */
|
||||
kSerialManager_UartParityEven = 0x2U, /*!< Parity even enabled */
|
||||
kSerialManager_UartParityOdd = 0x3U, /*!< Parity odd enabled */
|
||||
} serial_port_uart_parity_mode_t;
|
||||
|
||||
/*! @brief serial port uart stop bit count*/
|
||||
typedef enum _serial_port_uart_stop_bit_count
|
||||
{
|
||||
kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */
|
||||
kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */
|
||||
} serial_port_uart_stop_bit_count_t;
|
||||
|
||||
typedef struct _serial_port_uart_config
|
||||
{
|
||||
uint32_t clockRate; /*!< clock rate */
|
||||
uint32_t baudRate; /*!< baud rate */
|
||||
serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
|
||||
serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
|
||||
|
||||
uint8_t enableRx; /*!< Enable RX */
|
||||
uint8_t enableTx; /*!< Enable TX */
|
||||
uint8_t enableRxRTS; /*!< Enable RX RTS */
|
||||
uint8_t enableTxCTS; /*!< Enable TX CTS */
|
||||
uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
|
||||
please refer to the SOC corresponding RM. */
|
||||
|
||||
#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
|
||||
uint8_t txFifoWatermark;
|
||||
uint8_t rxFifoWatermark;
|
||||
#endif
|
||||
} serial_port_uart_config_t;
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
typedef struct _serial_port_uart_dma_config
|
||||
{
|
||||
uint32_t clockRate; /*!< clock rate */
|
||||
uint32_t baudRate; /*!< baud rate */
|
||||
serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
|
||||
serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
|
||||
|
||||
uint8_t enableRx; /*!< Enable RX */
|
||||
uint8_t enableTx; /*!< Enable TX */
|
||||
uint8_t enableRxRTS; /*!< Enable RX RTS */
|
||||
uint8_t enableTxCTS; /*!< Enable TX CTS */
|
||||
uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
|
||||
please refer to the SOC corresponding RM. */
|
||||
#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
|
||||
uint8_t txFifoWatermark;
|
||||
uint8_t rxFifoWatermark;
|
||||
#endif
|
||||
uint8_t dma_instance;
|
||||
uint8_t rx_channel;
|
||||
uint8_t tx_channel;
|
||||
void *dma_mux_configure;
|
||||
void *dma_channel_mux_configure;
|
||||
|
||||
} serial_port_uart_dma_config_t;
|
||||
#endif
|
||||
/*! @} */
|
||||
#endif /* __SERIAL_PORT_UART_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,829 +0,0 @@
|
||||
/*
|
||||
* Copyright 2018-2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __HAL_UART_ADAPTER_H__
|
||||
#define __HAL_UART_ADAPTER_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
#if defined(SDK_OS_FREE_RTOS)
|
||||
#include "FreeRTOS.h"
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @addtogroup UART_Adapter
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
#define UART_ADAPTER_NON_BLOCKING_MODE (1U)
|
||||
#else
|
||||
#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
|
||||
#define UART_ADAPTER_NON_BLOCKING_MODE (0U)
|
||||
#else
|
||||
#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
#ifndef HAL_UART_ISR_PRIORITY
|
||||
#define HAL_UART_ISR_PRIORITY (25U)
|
||||
#endif
|
||||
#else
|
||||
#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
|
||||
#ifndef HAL_UART_ISR_PRIORITY
|
||||
#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
|
||||
#endif
|
||||
#else
|
||||
/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
|
||||
* The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
|
||||
* priority is 3 (2^2 - 1). So, the default value is 3.
|
||||
*/
|
||||
#ifndef HAL_UART_ISR_PRIORITY
|
||||
#define HAL_UART_ISR_PRIORITY (3U)
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef HAL_UART_ADAPTER_LOWPOWER
|
||||
#define HAL_UART_ADAPTER_LOWPOWER (0U)
|
||||
#endif /* HAL_UART_ADAPTER_LOWPOWER */
|
||||
|
||||
/*! @brief Enable or disable uart hardware FIFO mode (1 - enable, 0 - disable) */
|
||||
#ifndef HAL_UART_ADAPTER_FIFO
|
||||
#define HAL_UART_ADAPTER_FIFO (1U)
|
||||
#endif /* HAL_UART_ADAPTER_FIFO */
|
||||
|
||||
#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U))
|
||||
#ifndef HAL_UART_DMA_ENABLE
|
||||
#define HAL_UART_DMA_ENABLE (1U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef HAL_UART_DMA_ENABLE
|
||||
#define HAL_UART_DMA_ENABLE (0U)
|
||||
#endif /* HAL_UART_DMA_ENABLE */
|
||||
|
||||
/*! @brief Enable or disable uart DMA adapter int mode (1 - enable, 0 - disable) */
|
||||
#ifndef HAL_UART_DMA_INIT_ENABLE
|
||||
#define HAL_UART_DMA_INIT_ENABLE (1U)
|
||||
#endif /* HAL_SPI_MASTER_DMA_INIT_ENABLE */
|
||||
|
||||
/*! @brief Definition of uart dma adapter software idleline detection timeout value in ms. */
|
||||
#ifndef HAL_UART_DMA_IDLELINE_TIMEOUT
|
||||
#define HAL_UART_DMA_IDLELINE_TIMEOUT (1U)
|
||||
#endif /* HAL_UART_DMA_IDLELINE_TIMEOUT */
|
||||
|
||||
/*! @brief Definition of uart adapter handle size. */
|
||||
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
|
||||
#define HAL_UART_HANDLE_SIZE (92U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
|
||||
#define HAL_UART_BLOCK_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
|
||||
#else
|
||||
#define HAL_UART_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U)
|
||||
#endif
|
||||
|
||||
/*! @brief Definition of uart dma adapter handle size. */
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
|
||||
#define HAL_UART_DMA_HANDLE_SIZE (124U + HAL_UART_ADAPTER_LOWPOWER * 36U)
|
||||
#elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
|
||||
#define HAL_UART_DMA_HANDLE_SIZE (140U + HAL_UART_ADAPTER_LOWPOWER * 36U)
|
||||
#else
|
||||
#error This SOC does not have DMA or EDMA available!
|
||||
#endif
|
||||
#endif /* HAL_UART_DMA_ENABLE */
|
||||
|
||||
/*!
|
||||
* @brief Defines the uart handle
|
||||
*
|
||||
* This macro is used to define a 4 byte aligned uart handle.
|
||||
* Then use "(hal_uart_handle_t)name" to get the uart handle.
|
||||
*
|
||||
* The macro should be global and could be optional. You could also define uart handle by yourself.
|
||||
*
|
||||
* This is an example,
|
||||
* @code
|
||||
* UART_HANDLE_DEFINE(uartHandle);
|
||||
* @endcode
|
||||
*
|
||||
* @param name The name string of the uart handle.
|
||||
*/
|
||||
#define UART_HANDLE_DEFINE(name) uint32_t name[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
#define UART_DMA_HANDLE_DEFINE(name) \
|
||||
uint32_t name[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
|
||||
#endif
|
||||
|
||||
/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */
|
||||
#ifndef HAL_UART_TRANSFER_MODE
|
||||
#define HAL_UART_TRANSFER_MODE (0U)
|
||||
#endif
|
||||
|
||||
/*! @brief The handle of uart adapter. */
|
||||
typedef void *hal_uart_handle_t;
|
||||
|
||||
/*! @brief The handle of uart dma adapter. */
|
||||
typedef void *hal_uart_dma_handle_t;
|
||||
|
||||
/*! @brief UART status */
|
||||
typedef enum _hal_uart_status
|
||||
{
|
||||
kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */
|
||||
kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */
|
||||
kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */
|
||||
kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */
|
||||
kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */
|
||||
kStatus_HAL_UartBaudrateNotSupport =
|
||||
MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */
|
||||
kStatus_HAL_UartProtocolError = MAKE_STATUS(
|
||||
kStatusGroup_HAL_UART,
|
||||
6), /*!< Error occurs for Noise, Framing, Parity, etc.
|
||||
For transactional transfer, The up layer needs to abort the transfer and then starts again */
|
||||
kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */
|
||||
} hal_uart_status_t;
|
||||
|
||||
/*! @brief UART parity mode. */
|
||||
typedef enum _hal_uart_parity_mode
|
||||
{
|
||||
kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */
|
||||
kHAL_UartParityEven = 0x2U, /*!< Parity even enabled */
|
||||
kHAL_UartParityOdd = 0x3U, /*!< Parity odd enabled */
|
||||
} hal_uart_parity_mode_t;
|
||||
|
||||
/*! @brief UART stop bit count. */
|
||||
typedef enum _hal_uart_stop_bit_count
|
||||
{
|
||||
kHAL_UartOneStopBit = 0U, /*!< One stop bit */
|
||||
kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */
|
||||
} hal_uart_stop_bit_count_t;
|
||||
|
||||
/*! @brief UART configuration structure. */
|
||||
typedef struct _hal_uart_config
|
||||
{
|
||||
uint32_t srcClock_Hz; /*!< Source clock */
|
||||
uint32_t baudRate_Bps; /*!< Baud rate */
|
||||
hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
|
||||
hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
|
||||
uint8_t enableRx; /*!< Enable RX */
|
||||
uint8_t enableTx; /*!< Enable TX */
|
||||
uint8_t enableRxRTS; /*!< Enable RX RTS */
|
||||
uint8_t enableTxCTS; /*!< Enable TX CTS */
|
||||
uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
|
||||
SOC corresponding RM.
|
||||
Invalid instance value will cause initialization failure. */
|
||||
#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
|
||||
uint8_t txFifoWatermark;
|
||||
uint8_t rxFifoWatermark;
|
||||
#endif
|
||||
} hal_uart_config_t;
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
/*! @brief UART DMA status */
|
||||
typedef enum _hal_uart_dma_status
|
||||
{
|
||||
kStatus_HAL_UartDmaSuccess = 0U,
|
||||
kStatus_HAL_UartDmaRxIdle = (1U << 1U),
|
||||
kStatus_HAL_UartDmaRxBusy = (1U << 2U),
|
||||
kStatus_HAL_UartDmaTxIdle = (1U << 3U),
|
||||
kStatus_HAL_UartDmaTxBusy = (1U << 4U),
|
||||
kStatus_HAL_UartDmaIdleline = (1U << 5U),
|
||||
kStatus_HAL_UartDmaError = (1U << 6U),
|
||||
} hal_uart_dma_status_t;
|
||||
|
||||
typedef struct _dma_mux_configure_t
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint8_t dma_mux_instance;
|
||||
uint32_t rx_request;
|
||||
uint32_t tx_request;
|
||||
} dma_dmamux_configure;
|
||||
};
|
||||
} dma_mux_configure_t;
|
||||
typedef struct _dma_channel_mux_configure_t
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t dma_rx_channel_mux;
|
||||
uint32_t dma_tx_channel_mux;
|
||||
} dma_dmamux_configure;
|
||||
};
|
||||
} dma_channel_mux_configure_t;
|
||||
|
||||
typedef struct _hal_uart_dma_config_t
|
||||
{
|
||||
uint8_t uart_instance;
|
||||
uint8_t dma_instance;
|
||||
uint8_t rx_channel;
|
||||
uint8_t tx_channel;
|
||||
void *dma_mux_configure;
|
||||
void *dma_channel_mux_configure;
|
||||
} hal_uart_dma_config_t;
|
||||
#endif /* HAL_UART_DMA_ENABLE */
|
||||
|
||||
/*! @brief UART transfer callback function. */
|
||||
typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
typedef struct _dma_callback_msg
|
||||
{
|
||||
hal_uart_dma_status_t status;
|
||||
uint8_t *data;
|
||||
uint32_t dataSize;
|
||||
} hal_dma_callback_msg_t;
|
||||
|
||||
/*! @brief UART transfer callback function. */
|
||||
typedef void (*hal_uart_dma_transfer_callback_t)(hal_uart_dma_handle_t handle,
|
||||
hal_dma_callback_msg_t *msg,
|
||||
void *callbackParam);
|
||||
#endif /* HAL_UART_DMA_ENABLE */
|
||||
|
||||
/*! @brief UART transfer structure. */
|
||||
typedef struct _hal_uart_transfer
|
||||
{
|
||||
uint8_t *data; /*!< The buffer of data to be transfer.*/
|
||||
size_t dataSize; /*!< The byte count to be transfer. */
|
||||
} hal_uart_transfer_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes a UART instance with the UART handle and the user configuration structure.
|
||||
*
|
||||
* This function configures the UART module with user-defined settings. The user can configure the configuration
|
||||
* structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by
|
||||
* the caller. Example below shows how to use this API to configure the UART.
|
||||
* @code
|
||||
* UART_HANDLE_DEFINE(g_UartHandle);
|
||||
* hal_uart_config_t config;
|
||||
* config.srcClock_Hz = 48000000;
|
||||
* config.baudRate_Bps = 115200U;
|
||||
* config.parityMode = kHAL_UartParityDisabled;
|
||||
* config.stopBitCount = kHAL_UartOneStopBit;
|
||||
* config.enableRx = 1;
|
||||
* config.enableTx = 1;
|
||||
* config.enableRxRTS = 0;
|
||||
* config.enableTxCTS = 0;
|
||||
* config.instance = 0;
|
||||
* HAL_UartInit((hal_uart_handle_t)g_UartHandle, &config);
|
||||
* @endcode
|
||||
*
|
||||
* @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* You can define the handle in the following two ways:
|
||||
* #UART_HANDLE_DEFINE(handle);
|
||||
* or
|
||||
* uint32_t handle[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
|
||||
* @param uart_config Pointer to user-defined configuration structure.
|
||||
* @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.
|
||||
* @retval kStatus_HAL_UartSuccess UART initialization succeed
|
||||
*/
|
||||
hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *uart_config);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes a UART instance.
|
||||
*
|
||||
* This function waits for TX complete, disables TX and RX, and disables the UART clock.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_HAL_UartSuccess UART de-initialization succeed
|
||||
*/
|
||||
hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Blocking bus Operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Reads RX data register using a blocking method.
|
||||
*
|
||||
* This function polls the RX register, waits for the RX register to be full or for RX FIFO to
|
||||
* have data, and reads data from the RX register.
|
||||
*
|
||||
* @note The function #HAL_UartReceiveBlocking and the function HAL_UartTransferReceiveNonBlocking
|
||||
* cannot be used at the same time.
|
||||
* And, the function HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data Start address of the buffer to store the received data.
|
||||
* @param length Size of the buffer.
|
||||
* @retval kStatus_HAL_UartError An error occurred while receiving data.
|
||||
* @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully received all data.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
|
||||
|
||||
/*!
|
||||
* @brief Writes to the TX register using a blocking method.
|
||||
*
|
||||
* This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
|
||||
* to have room and writes data to the TX buffer.
|
||||
*
|
||||
* @note The function #HAL_UartSendBlocking and the function HAL_UartTransferSendNonBlocking
|
||||
* cannot be used at the same time.
|
||||
* And, the function HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data Start address of the data to write.
|
||||
* @param length Size of the data to write.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully sent all data.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
|
||||
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
|
||||
|
||||
/*!
|
||||
* @name Transactional
|
||||
* @note The transactional API and the functional API cannot be used at the same time. The macro
|
||||
* #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
|
||||
* functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Installs a callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the callback and callback parameter for UART module.
|
||||
* When any status of the UART changed, the driver will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully install the callback.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
|
||||
hal_uart_transfer_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Receives a buffer of data using an interrupt method.
|
||||
*
|
||||
* This function receives data using an interrupt method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be received.
|
||||
* The receive request is saved by the UART driver.
|
||||
* When the new data arrives, the receive request is serviced first.
|
||||
* When all data is received, the UART driver notifies the upper layer
|
||||
* through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle.
|
||||
*
|
||||
* @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
|
||||
* cannot be used at the same time.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param transfer UART transfer structure, see #hal_uart_transfer_t.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
|
||||
* @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
|
||||
|
||||
/*!
|
||||
* @brief Transmits a buffer of data using the interrupt method.
|
||||
*
|
||||
* This function sends data using an interrupt method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be written to the TX register. When
|
||||
* all data is written to the TX register in the ISR, the UART driver calls the callback
|
||||
* function and passes the @ref kStatus_HAL_UartTxIdle as status parameter.
|
||||
*
|
||||
* @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
|
||||
* cannot be used at the same time.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param transfer UART transfer structure. See #hal_uart_transfer_t.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
|
||||
* @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes that have been received.
|
||||
*
|
||||
* This function gets the number of bytes that have been received.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param count Receive bytes count.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes written to the UART TX register.
|
||||
*
|
||||
* This function gets the number of bytes written to the UART TX
|
||||
* register by using the interrupt method.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param count Send bytes count.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data receiving.
|
||||
*
|
||||
* This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
|
||||
* how many bytes are not received yet.
|
||||
*
|
||||
* @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of
|
||||
* the function #HAL_UartReceiveBlocking.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_Success Get successfully abort the receiving.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data sending.
|
||||
*
|
||||
* This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
|
||||
* how many bytes are not sent out.
|
||||
*
|
||||
* @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of
|
||||
* the function #HAL_UartSendBlocking.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_Success Get successfully abort the sending.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#else
|
||||
|
||||
/*!
|
||||
* @name Functional API with non-blocking mode.
|
||||
* @note The functional API and the transactional API cannot be used at the same time. The macro
|
||||
* #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
|
||||
* functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Installs a callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the callback and callback parameter for UART module.
|
||||
* When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully install the callback.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
|
||||
hal_uart_transfer_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Receives a buffer of data using an interrupt method.
|
||||
*
|
||||
* This function receives data using an interrupt method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be received.
|
||||
* The receive request is saved by the UART adapter.
|
||||
* When the new data arrives, the receive request is serviced first.
|
||||
* When all data is received, the UART adapter notifies the upper layer
|
||||
* through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle.
|
||||
*
|
||||
* @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking
|
||||
* cannot be used at the same time.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data Start address of the data to write.
|
||||
* @param length Size of the data to write.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
|
||||
* @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
|
||||
|
||||
/*!
|
||||
* @brief Transmits a buffer of data using the interrupt method.
|
||||
*
|
||||
* This function sends data using an interrupt method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be written to the TX register. When
|
||||
* all data is written to the TX register in the ISR, the UART driver calls the callback
|
||||
* function and passes the @ref kStatus_HAL_UartTxIdle as status parameter.
|
||||
*
|
||||
* @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking
|
||||
* cannot be used at the same time.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data Start address of the data to write.
|
||||
* @param length Size of the data to write.
|
||||
* @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
|
||||
* @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes that have been received.
|
||||
*
|
||||
* This function gets the number of bytes that have been received.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param reCount Receive bytes count.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes written to the UART TX register.
|
||||
*
|
||||
* This function gets the number of bytes written to the UART TX
|
||||
* register by using the interrupt method.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param seCount Send bytes count.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data receiving.
|
||||
*
|
||||
* This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
|
||||
* how many bytes are not received yet.
|
||||
*
|
||||
* @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of
|
||||
* the function #HAL_UartReceiveBlocking.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_Success Get successfully abort the receiving.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data sending.
|
||||
*
|
||||
* This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
|
||||
* how many bytes are not sent out.
|
||||
*
|
||||
* @note The function #HAL_UartAbortSend cannot be used to abort the transmission of
|
||||
* the function #HAL_UartSendBlocking.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_Success Get successfully abort the sending.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
|
||||
|
||||
/*!
|
||||
* @brief Initializes a UART dma instance with the UART dma handle and the user configuration structure.
|
||||
*
|
||||
* This function configures the UART dma module with user-defined settings. The user can configure the configuration
|
||||
* structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated
|
||||
* by the caller. Example below shows how to use this API to configure the UART.
|
||||
* @code
|
||||
*
|
||||
* Init TimerManager, only used in UART without Idleline interrupt
|
||||
* timer_config_t timerConfig;
|
||||
* timerConfig.srcClock_Hz = 16000000;
|
||||
* timerConfig.instance = 0;
|
||||
* TM_Init(&timerConfig);
|
||||
*
|
||||
* Init the DMA module
|
||||
* DMA_Init(DMA0);
|
||||
*
|
||||
* Define a uart dma handle
|
||||
* UART_HANDLE_DEFINE(g_uartHandle);
|
||||
* UART_DMA_HANDLE_DEFINE(g_UartDmaHandle);
|
||||
*
|
||||
* Configure uart settings
|
||||
* hal_uart_config_t uartConfig;
|
||||
* uartConfig.srcClock_Hz = 48000000;
|
||||
* uartConfig.baudRate_Bps = 115200;
|
||||
* uartConfig.parityMode = kHAL_UartParityDisabled;
|
||||
* uartConfig.stopBitCount = kHAL_UartOneStopBit;
|
||||
* uartConfig.enableRx = 1;
|
||||
* uartConfig.enableTx = 1;
|
||||
* uartConfig.enableRxRTS = 0;
|
||||
* uartConfig.enableTxCTS = 0;
|
||||
* uartConfig.instance = 0;
|
||||
*
|
||||
* Init uart
|
||||
* HAL_UartInit((hal_uart_handle_t *)g_uartHandle, &uartConfig);
|
||||
*
|
||||
* Configure uart dma settings
|
||||
* hal_uart_dma_config_t dmaConfig;
|
||||
* dmaConfig.uart_instance = 0;
|
||||
* dmaConfig.dma_instance = 0;
|
||||
* dmaConfig.rx_channel = 0;
|
||||
* dmaConfig.tx_channel = 1;
|
||||
*
|
||||
* Init uart dma
|
||||
* HAL_UartDMAInit((hal_uart_handle_t *)g_uartHandle, (hal_uart_dma_handle_t *)g_uartDmaHandle, &dmaConfig);
|
||||
* @endcode
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param dmaHandle Pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated by the caller.
|
||||
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
|
||||
* You can define the handle in the following two ways:
|
||||
* #UART_DMA_HANDLE_DEFINE(handle);
|
||||
* or
|
||||
* uint32_t handle[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
|
||||
* @param dmaConfig Pointer to user-defined configuration structure.
|
||||
* @retval kStatus_HAL_UartDmaError UART dma initialization failed.
|
||||
* @retval kStatus_HAL_UartDmaSuccess UART dma initialization succeed.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle,
|
||||
hal_uart_dma_handle_t dmaHandle,
|
||||
hal_uart_dma_config_t *dmaConfig);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes a UART DMA instance.
|
||||
*
|
||||
* This function will abort uart dma receive/send transfer and deinitialize UART.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_HAL_UartDmaSuccess UART DMA de-initialization succeed
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle);
|
||||
|
||||
/*!
|
||||
* @brief Installs a callback and callback parameter.
|
||||
*
|
||||
* This function is used to install the callback and callback parameter for UART DMA module.
|
||||
* When any status of the UART DMA changed, the driver will notify the upper layer by the installed callback
|
||||
* function. And the status is also passed as status parameter when the callback is called.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param callbackParam The parameter of the callback function.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Successfully install the callback.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle,
|
||||
hal_uart_dma_transfer_callback_t callback,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Receives a buffer of data using an dma method.
|
||||
*
|
||||
* This function receives data using an dma method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be received.
|
||||
* The receive request is saved by the UART DMA driver.
|
||||
* When all data is received, the UART DMA adapter notifies the upper layer
|
||||
* through a callback function and passes the status parameter @ref kStatus_HAL_UartDmaRxIdle.
|
||||
*
|
||||
* When an idleline is detected, the UART DMA adapter notifies the upper layer through a callback function,
|
||||
* and passes the status parameter @ref kStatus_HAL_UartDmaIdleline. For the UARTs without hardware idleline
|
||||
* interrupt(like usart), it will use a software idleline detection method with the help of TimerManager.
|
||||
*
|
||||
* When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data data Start address of the buffer to store the received data.
|
||||
* @param length Size of the buffer.
|
||||
* @param receiveAll Idleline interrupt will not end transfer process if set true.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Successfully start the data receive.
|
||||
* @retval kStatus_HAL_UartDmaRxBusy Previous receive request is not finished.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle,
|
||||
uint8_t *data,
|
||||
size_t length,
|
||||
bool receiveAll);
|
||||
|
||||
/*!
|
||||
* @brief Transmits a buffer of data using an dma method.
|
||||
*
|
||||
* This function sends data using an dma method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be written to the TX register. When
|
||||
* all data is written to the TX register by DMA, the UART DMA driver calls the callback
|
||||
* function and passes the @ref kStatus_HAL_UartDmaTxIdle as status parameter.
|
||||
*
|
||||
* When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param data data Start address of the data to write.
|
||||
* @param length Size of the data to write.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Successfully start the data transmission.
|
||||
* @retval kStatus_HAL_UartDmaTxBusy Previous send request is not finished.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes that have been received.
|
||||
*
|
||||
* This function gets the number of bytes that have been received.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param reCount Receive bytes count.
|
||||
* @retval kStatus_HAL_UartDmaError An error occurred.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p reCount.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes written to the UART TX register.
|
||||
*
|
||||
* This function gets the number of bytes written to the UART TX
|
||||
* register by using the DMA method.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @param seCount Send bytes count.
|
||||
* @retval kStatus_HAL_UartDmaError An error occurred.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p seCount.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the DMA-driven data receiving.
|
||||
*
|
||||
* This function aborts the DMA-driven data receiving.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_HAL_UartDmaSuccess Get successfully abort the receiving.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the DMA-driven data sending.
|
||||
*
|
||||
* This function aborts the DMA-driven data sending.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_Success Get successfully abort the sending.
|
||||
*/
|
||||
hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle);
|
||||
#endif /* HAL_UART_DMA_ENABLE */
|
||||
|
||||
/*!
|
||||
* @brief Prepares to enter low power consumption.
|
||||
*
|
||||
* This function is used to prepare to enter low power consumption.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_HAL_UartSuccess Successful operation.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle);
|
||||
|
||||
/*!
|
||||
* @brief Restores from low power consumption.
|
||||
*
|
||||
* This function is used to restore from low power consumption.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
* @retval kStatus_HAL_UartSuccess Successful operation.
|
||||
* @retval kStatus_HAL_UartError An error occurred.
|
||||
*/
|
||||
hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle);
|
||||
|
||||
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
|
||||
/*!
|
||||
* @brief UART IRQ handle function.
|
||||
*
|
||||
* This function handles the UART transmit and receive IRQ request.
|
||||
*
|
||||
* @param handle UART handle pointer.
|
||||
*/
|
||||
void HAL_UartIsrFunction(hal_uart_handle_t handle);
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/*! @}*/
|
||||
#endif /* __HAL_UART_ADAPTER_H__ */
|
||||
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Reference in New Issue
Block a user