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Fix boot loader UART baud rate on soft reboot
Also remove `-O3` optimization flasg, it negates `-Os`. Saves ~400 bytes. CL: none PUBLISHED_FROM=f40f42e4f54a8e0e003ab65ec8f5838c2d932876
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@ -160,7 +160,8 @@ static uint8 calc_chksum(uint8 *start, uint8 *end) {
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}
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#endif
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#define UART_CLKDIV_26MHZ(B) (52000000 + B / 2) / B
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#define UART_CLKDIV_80MHZ(B) (80000000 + B / 2) / B
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#define UART_CLKDIV_52MHZ(B) (52000000 + B / 2) / B
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// prevent this function being placed inline with main
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// to keep main's stack size as small as possible
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@ -182,10 +183,23 @@ uint32 NOINLINE find_image(void) {
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// delay to slow boot (help see messages when debugging)
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//ets_delay_us(2000000);
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uart_div_modify(0, UART_CLKDIV_26MHZ(115200));
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/*
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* UART divider depends on the APB frequency. Cold boot starts with 52MHz APB,
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* SDK configures PLL, sets it to 80 and it persists across soft reset
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* so on soft reset a different divider should be used. What we really want to
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* know is if the PLL is running but since that is completely undocumented
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* we use CPU frequency bit as a workaround: mos sets CPU to 160 MHz on startup
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* so we assume that if frequency is preserved, then it's soft reset, PLL is
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* running and APB is at 80 MHz.
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*/
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if (READ_PERI_REG(0x3ff00014) & 1) {
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uart_div_modify(0, UART_CLKDIV_80MHZ(115200));
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} else {
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uart_div_modify(0, UART_CLKDIV_52MHZ(115200));
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}
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ets_delay_us(1000);
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ets_printf("\r\nrBoot v1.2.1 - richardaburton@gmail.com\r\n");
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ets_printf("\r\nrBoot v1.2.1-cesanta1 - richardaburton@gmail.com\r\n");
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// read rom header
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SPIRead(0, header, sizeof(rom_header));
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@ -23,7 +23,7 @@ LD := $(addprefix $(XTENSA_BINDIR)/,xtensa-lx106-elf-gcc)
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endif
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CC_WRAPPER ?=
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CFLAGS = -Os -O3 -Wpointer-arith -Wundef -Werror -Wl,-EL \
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CFLAGS = -Os -Wpointer-arith -Wundef -Werror -Wl,-EL \
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-fno-inline-functions -nostdlib -mlongcalls -mtext-section-literals \
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-D__ets__ -DIRAM='__attribute__((section(".fast.text")))' \
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-DNOINSTR='__attribute__((no_instrument_function))' \
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