From 81f0f8a7c2468a9fe19830f962f8915440ef55e2 Mon Sep 17 00:00:00 2001 From: "Sergio R. Caprile" Date: Mon, 13 May 2024 12:15:44 -0300 Subject: [PATCH] fix LAN87x --- mongoose.c | 23 ++++++----------------- src/drivers/phy.c | 23 ++++++----------------- 2 files changed, 12 insertions(+), 34 deletions(-) diff --git a/mongoose.c b/mongoose.c index ba2dc8e9..99946628 100644 --- a/mongoose.c +++ b/mongoose.c @@ -15624,31 +15624,21 @@ static const char *mg_phy_id_to_str(uint16_t id1, uint16_t id2) { (void) id2; } -static void mg_phy_set_clk_out(struct mg_phy *phy, uint8_t phy_addr) { - uint16_t id1, id2; - id1 = phy->read_reg(phy_addr, MG_PHY_REG_ID1); - id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2); - - if (id1 == MG_PHY_DP83x && id2 == MG_PHY_DP83867) { - // write 0x10d to IO_MUX_CFG (0x0170) - phy->write_reg(phy_addr, 0x0d, 0x1f); - phy->write_reg(phy_addr, 0x0e, 0x170); - phy->write_reg(phy_addr, 0x0d, 0x401f); - phy->write_reg(phy_addr, 0x0e, 0x10d); - } -} - void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) { uint16_t id1, id2; phy->write_reg(phy_addr, MG_PHY_REG_BCR, MG_BIT(15)); // Reset PHY - phy->write_reg(phy_addr, MG_PHY_REG_BCR, MG_BIT(12)); // Autonegotiation + while (phy->read_reg(phy_addr, MG_PHY_REG_BCR) & MG_BIT(15)) (void) 0; + // MG_PHY_REG_BCR[12]: Autonegotiation is default unless hw says otherwise id1 = phy->read_reg(phy_addr, MG_PHY_REG_ID1); id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2); MG_INFO(("PHY ID: %#04x %#04x (%s)", id1, id2, mg_phy_id_to_str(id1, id2))); if (id1 == MG_PHY_DP83x && id2 == MG_PHY_DP83867) { - mg_phy_set_clk_out(phy, phy_addr); + phy->write_reg(phy_addr, 0x0d, 0x1f); // write 0x10d to IO_MUX_CFG (0x0170) + phy->write_reg(phy_addr, 0x0e, 0x170); + phy->write_reg(phy_addr, 0x0d, 0x401f); + phy->write_reg(phy_addr, 0x0e, 0x10d); } if (config & MG_PHY_CLOCKS_MAC) { @@ -15711,7 +15701,6 @@ bool mg_phy_up(struct mg_phy *phy, uint8_t phy_addr, bool *full_duplex, *speed = (scsr & MG_BIT(3)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M; } else if (id1 == MG_PHY_RTL8201) { uint16_t bcr = phy->read_reg(phy_addr, MG_PHY_REG_BCR); - if (bcr & MG_BIT(15)) return 0; // still resetting *full_duplex = bcr & MG_BIT(8); *speed = (bcr & MG_BIT(13)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M; } diff --git a/src/drivers/phy.c b/src/drivers/phy.c index 3a11cb9a..9acb28d9 100644 --- a/src/drivers/phy.c +++ b/src/drivers/phy.c @@ -45,31 +45,21 @@ static const char *mg_phy_id_to_str(uint16_t id1, uint16_t id2) { (void) id2; } -static void mg_phy_set_clk_out(struct mg_phy *phy, uint8_t phy_addr) { - uint16_t id1, id2; - id1 = phy->read_reg(phy_addr, MG_PHY_REG_ID1); - id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2); - - if (id1 == MG_PHY_DP83x && id2 == MG_PHY_DP83867) { - // write 0x10d to IO_MUX_CFG (0x0170) - phy->write_reg(phy_addr, 0x0d, 0x1f); - phy->write_reg(phy_addr, 0x0e, 0x170); - phy->write_reg(phy_addr, 0x0d, 0x401f); - phy->write_reg(phy_addr, 0x0e, 0x10d); - } -} - void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) { uint16_t id1, id2; phy->write_reg(phy_addr, MG_PHY_REG_BCR, MG_BIT(15)); // Reset PHY - phy->write_reg(phy_addr, MG_PHY_REG_BCR, MG_BIT(12)); // Autonegotiation + while (phy->read_reg(phy_addr, MG_PHY_REG_BCR) & MG_BIT(15)) (void) 0; + // MG_PHY_REG_BCR[12]: Autonegotiation is default unless hw says otherwise id1 = phy->read_reg(phy_addr, MG_PHY_REG_ID1); id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2); MG_INFO(("PHY ID: %#04x %#04x (%s)", id1, id2, mg_phy_id_to_str(id1, id2))); if (id1 == MG_PHY_DP83x && id2 == MG_PHY_DP83867) { - mg_phy_set_clk_out(phy, phy_addr); + phy->write_reg(phy_addr, 0x0d, 0x1f); // write 0x10d to IO_MUX_CFG (0x0170) + phy->write_reg(phy_addr, 0x0e, 0x170); + phy->write_reg(phy_addr, 0x0d, 0x401f); + phy->write_reg(phy_addr, 0x0e, 0x10d); } if (config & MG_PHY_CLOCKS_MAC) { @@ -132,7 +122,6 @@ bool mg_phy_up(struct mg_phy *phy, uint8_t phy_addr, bool *full_duplex, *speed = (scsr & MG_BIT(3)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M; } else if (id1 == MG_PHY_RTL8201) { uint16_t bcr = phy->read_reg(phy_addr, MG_PHY_REG_BCR); - if (bcr & MG_BIT(15)) return 0; // still resetting *full_duplex = bcr & MG_BIT(8); *speed = (bcr & MG_BIT(13)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M; }