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FreeRTOS w/blink works
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parent
c44549bfa5
commit
151e375091
@ -13,8 +13,8 @@ INCS = -I$(ARCH) -I. -I../.. -Ifreertos-kernel/include -Ifreertos-tcp/include -I
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CFLAGS = -W -Wall -Os -g $(MCU) -fdata-sections -ffunction-sections $(INCS) $(MONGOOSE_OPTS) $(EXTRA)
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CFLAGS = -W -Wall -Os -g $(MCU) -fdata-sections -ffunction-sections $(INCS) $(MONGOOSE_OPTS) $(EXTRA)
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LDFLAGS = $(MCU) -specs=nano.specs -Tobj/link.ld -nostartfiles -nostdlib -lc -lm -lnosys -lgcc #-Wl,-Map=obj/$(PROG).map,--cref -Wl,--gc-sections
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LDFLAGS = $(MCU) -specs=nano.specs -Tobj/link.ld -nostartfiles -nostdlib -lc -lm -lnosys -lgcc #-Wl,-Map=obj/$(PROG).map,--cref -Wl,--gc-sections
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SRCS = main.c # $(wildcard freertos-tcp/*.c)
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SRCS = main.c # $(wildcard freertos-tcp/*.c)
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# SRCS += freertos-kernel/portable/MemMang/heap_4.c $(ARCH)/port.c
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SRCS += freertos-kernel/portable/MemMang/heap_4.c $(ARCH)/port.c
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# SRCS += freertos-kernel/list.c freertos-kernel/tasks.c freertos-kernel/queue.c
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SRCS += freertos-kernel/list.c freertos-kernel/tasks.c freertos-kernel/queue.c
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OBJS = obj/boot.o $(SRCS:%.c=obj/%.o) #obj/mongoose.o # ORDER MATTERS - boot (vector table) first!
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OBJS = obj/boot.o $(SRCS:%.c=obj/%.o) #obj/mongoose.o # ORDER MATTERS - boot (vector table) first!
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all: $(PROG).hex
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all: $(PROG).hex
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@ -43,7 +43,7 @@ obj/mongoose.o:
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$(DOCKER) arm-none-eabi-gcc $(CFLAGS) -c ../../mongoose.c -o $@
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$(DOCKER) arm-none-eabi-gcc $(CFLAGS) -c ../../mongoose.c -o $@
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flash: $(PROG).bin
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flash: $(PROG).bin
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st-flash write $< 0x8000000
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st-flash --reset write $< 0x8000000
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gdb: $(PROG).elf
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gdb: $(PROG).elf
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arm-none-eabi-gdb \
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arm-none-eabi-gdb \
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@ -51,8 +51,6 @@ gdb: $(PROG).elf
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-ex 'target extended-remote :4242' \
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-ex 'target extended-remote :4242' \
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-ex 'monitor reset halt' \
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-ex 'monitor reset halt' \
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-ex 'monitor reset init' \
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-ex 'monitor reset init' \
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-ex 'b main' \
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-ex 'r' \
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$<
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$<
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clean:
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clean:
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@ -33,8 +33,7 @@ static void fn(void *args) {
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// int delay_ms = *(int *) args;
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// int delay_ms = *(int *) args;
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for (;;) {
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for (;;) {
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led_toggle();
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led_toggle();
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spin(500000);
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vTaskDelay(pdMS_TO_TICKS(300));
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// vTaskDelay(pdMS_TO_TICKS(0));
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};
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};
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(void) args;
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(void) args;
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}
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}
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@ -42,8 +41,7 @@ static void fn(void *args) {
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int main(void) {
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int main(void) {
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init_ram();
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init_ram();
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init_hardware();
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init_hardware();
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fn(NULL);
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xTaskCreate(fn, "server", 512, NULL, configMAX_PRIORITIES - 1, NULL);
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// xTaskCreate(fn, "server", 512, NULL, configMAX_PRIORITIES - 1, NULL);
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vTaskStartScheduler(); // This blocks
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// vTaskStartScheduler();
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return 0; // Unreachable
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return 0;
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}
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}
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@ -1,29 +1,33 @@
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.cpu cortex-m3
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.cpu cortex-m3
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.thumb
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.thumb
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.word _estack /* stack top address */
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.word _estack // 0 Stack top address
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.word _reset /* 1 Reset */
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.word _reset // 1 Reset
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.word spin /* 2 NMI */
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.word pass // 2 NMI
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.word spin /* 3 Hard Fault */
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.word halt // 3 Hard Fault
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.word spin /* 4 MM Fault */
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.word halt // 4 MM Fault
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.word spin /* 5 Bus Fault */
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.word halt // 5 Bus Fault
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.word spin /* 6 Usage Fault */
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.word halt // 6 Usage Fault
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.word spin /* 7 RESERVED */
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.word halt // 7 RESERVED
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.word spin /* 8 RESERVED */
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.word halt // 8 RESERVED
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.word spin /* 9 RESERVED*/
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.word halt // 9 RESERVED
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.word spin /* 10 RESERVED */
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.word halt // 10 RESERVED
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.word spin /* 11 SV call */
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.word SVC_handler // 11 SV call
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.word spin /* 12 Debug reserved */
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.word halt // 12 Debug reserved
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.word spin /* 13 RESERVED */
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.word halt // 13 RESERVED
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.word spin /* 14 PendSV */
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.word pending_SV_handler // 14 PendSV
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.word spin /* 15 SysTick */
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.word SysTick_handler // 15 SysTick
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.word spin /* 16 IRQ0 */
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.word pass // 16 IRQ0
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.word spin /* 17 IRQ1 */
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.word halt // 17 IRQ1
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.word spin /* 18 IRQ2 */
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// On to IRQ67
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.word spin /* 19 ... */
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.word halt,halt,halt,halt,halt,halt,halt,halt,halt,halt
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/* On to IRQ67 */
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.word halt,halt,halt,halt,halt,halt,halt,halt,halt,halt
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.word halt,halt,halt,halt,halt,halt,halt,halt,halt,halt
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.word halt,halt,halt,halt,halt,halt,halt,halt,halt,halt
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.word halt,halt,halt,halt,halt,halt,halt,halt,halt,halt
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spin: b spin
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halt: b halt
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pass: BX lr
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.thumb_func
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.thumb_func
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.global _reset
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.global _reset
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@ -13,6 +13,17 @@ static inline void led_toggle(void) {
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}
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}
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static inline void init_hardware(void) {
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static inline void init_hardware(void) {
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RCC->CR |= (RCC_CR_HSEON);
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while (!(RCC->CR & RCC_CR_HSERDY)) (void) 0;
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RCC->CFGR &= ~(RCC_CFGR_SW);
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RCC->CFGR |= (RCC_CFGR_SW_HSE);
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RCC->CFGR &= ~(RCC_CFGR_PLLMULL);
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RCC->CFGR |= (RCC_CFGR_PLLMULL9);
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RCC->CR |= (RCC_CR_PLLON);
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while (!(RCC->CR & RCC_CR_PLLRDY)) (void) 0;
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RCC->CFGR &= ~(RCC_CFGR_SW);
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RCC->CFGR |= (RCC_CFGR_SW_PLL);
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RCC->APB2ENR |= BIT(2) | BIT(3) | BIT(4); // Init GPIO banks A,B,C
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RCC->APB2ENR |= BIT(2) | BIT(3) | BIT(4); // Init GPIO banks A,B,C
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gpio_init(LED1, OUTPUT); // Set LED
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gpio_init(LED1, OUTPUT); // Set LED
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}
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}
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@ -15,6 +15,8 @@ static inline void setreg(volatile uint32_t *r, uint32_t clear_mask, uint32_t se
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// RCC registers, TRM section 7.3, memory map section 3.3
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// RCC registers, TRM section 7.3, memory map section 3.3
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struct rcc { volatile uint32_t CR, CFGR, CIR, APB2RSTR, APB1RSTR, AHBENR, APB2ENR, APB1ENR, BDCR, CSR; };
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struct rcc { volatile uint32_t CR, CFGR, CIR, APB2RSTR, APB1RSTR, AHBENR, APB2ENR, APB1ENR, BDCR, CSR; };
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#define RCC ((struct rcc *) 0x40021000)
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#define RCC ((struct rcc *) 0x40021000)
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enum {RCC_CR_HSEON = BIT(16), RCC_CR_HSERDY = BIT(17), RCC_CR_PLLON = BIT(24), RCC_CR_PLLRDY = BIT(25)};
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enum {RCC_CFGR_SW = 3, RCC_CFGR_SW_HSI = 0, RCC_CFGR_SW_HSE = 1, RCC_CFGR_SW_PLL = 2, RCC_CFGR_PLLMULL = (15U << 18), RCC_CFGR_PLLMULL9 = (7U << 18)};
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static inline void init_ram(void) {
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static inline void init_ram(void) {
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extern uint32_t _bss_start, _bss_end;
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extern uint32_t _bss_start, _bss_end;
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