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When no SSE (fxsave) context is available but x87 (fsave) context is, use the x87 context. This also embeds the x87 FPU opcode from the fxsave fop field in bits 16-26 of the fsave error_selector field, true to the layout of the fsave structure. See Intel SDM volume 1 (253665-061) 8.1.10 and figure 8-9. BUG=crashpad:161 TEST=crashpad_snapshot_test CPUContextX86.*:CPUContextWin.* Change-Id: I0bf7ed995c152f124166eaa20104d228d3468f76 Reviewed-on: https://chromium-review.googlesource.com/442144 Reviewed-by: Scott Graham <scottmg@chromium.org>
116 lines
3.7 KiB
C++
116 lines
3.7 KiB
C++
// Copyright 2014 The Crashpad Authors. All rights reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "snapshot/cpu_context.h"
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#include "base/logging.h"
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#include "util/misc/implicit_cast.h"
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namespace crashpad {
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namespace {
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enum {
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kX87TagValid = 0,
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kX87TagZero,
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kX87TagSpecial,
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kX87TagEmpty,
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};
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} // namespace
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// static
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uint16_t CPUContextX86::FxsaveToFsaveTagWord(
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uint16_t fsw,
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uint8_t fxsave_tag,
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const CPUContextX86::X87OrMMXRegister st_mm[8]) {
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// The x87 tag word (in both abridged and full form) identifies physical
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// registers, but |st_mm| is arranged in logical stack order. In order to map
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// physical tag word bits to the logical stack registers they correspond to,
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// the “stack top” value from the x87 status word is necessary.
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int stack_top = (fsw >> 11) & 0x7;
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uint16_t fsave_tag = 0;
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for (int physical_index = 0; physical_index < 8; ++physical_index) {
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bool fxsave_bit = (fxsave_tag & (1 << physical_index)) != 0;
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uint8_t fsave_bits;
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if (fxsave_bit) {
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int st_index = (physical_index + 8 - stack_top) % 8;
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const CPUContextX86::X87Register& st = st_mm[st_index].st;
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uint32_t exponent = ((st[9] & 0x7f) << 8) | st[8];
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if (exponent == 0x7fff) {
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// Infinity, NaN, pseudo-infinity, or pseudo-NaN. If it was important to
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// distinguish between these, the J bit and the M bit (the most
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// significant bit of |fraction|) could be consulted.
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fsave_bits = kX87TagSpecial;
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} else {
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// The integer bit the “J bit”.
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bool integer_bit = (st[7] & 0x80) != 0;
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if (exponent == 0) {
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uint64_t fraction = ((implicit_cast<uint64_t>(st[7]) & 0x7f) << 56) |
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(implicit_cast<uint64_t>(st[6]) << 48) |
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(implicit_cast<uint64_t>(st[5]) << 40) |
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(implicit_cast<uint64_t>(st[4]) << 32) |
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(implicit_cast<uint32_t>(st[3]) << 24) |
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(st[2] << 16) | (st[1] << 8) | st[0];
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if (!integer_bit && fraction == 0) {
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fsave_bits = kX87TagZero;
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} else {
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// Denormal (if the J bit is clear) or pseudo-denormal.
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fsave_bits = kX87TagSpecial;
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}
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} else if (integer_bit) {
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fsave_bits = kX87TagValid;
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} else {
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// Unnormal.
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fsave_bits = kX87TagSpecial;
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}
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}
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} else {
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fsave_bits = kX87TagEmpty;
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}
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fsave_tag |= (fsave_bits << (physical_index * 2));
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}
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return fsave_tag;
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}
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// static
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uint8_t CPUContextX86::FsaveToFxsaveTagWord(uint16_t fsave_tag) {
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uint8_t fxsave_tag = 0;
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for (int physical_index = 0; physical_index < 8; ++physical_index) {
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const uint8_t fsave_bits = (fsave_tag >> (physical_index * 2)) & 0x3;
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const bool fxsave_bit = fsave_bits != kX87TagEmpty;
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fxsave_tag |= fxsave_bit << physical_index;
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}
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return fxsave_tag;
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}
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uint64_t CPUContext::InstructionPointer() const {
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switch (architecture) {
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case kCPUArchitectureX86:
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return x86->eip;
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case kCPUArchitectureX86_64:
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return x86_64->rip;
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default:
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NOTREACHED();
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return ~0ull;
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}
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}
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} // namespace crashpad
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