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4b450c8137
gtest used to require (expected, actual) ordering for arguments to
EXPECT_EQ and ASSERT_EQ, and in failed test assertions would identify
each side as “expected” or “actual.” Tests in Crashpad adhered to this
traditional ordering. After a gtest change in February 2016, it is now
agnostic with respect to the order of these arguments.
This change mechanically updates all uses of these macros to (actual,
expected) by reversing them. This provides consistency with our use of
the logging CHECK_EQ and DCHECK_EQ macros, and makes for better
readability by ordinary native speakers. The rough (but working!)
conversion tool is
https://chromium-review.googlesource.com/c/466727/1/rewrite_expectassert_eq.py,
and “git cl format” cleaned up its output.
EXPECT_NE and ASSERT_NE never had a preferred ordering. gtest never made
a judgment that one side or the other needed to provide an “unexpected”
value. Consequently, some code used (unexpected, actual) while other
code used (actual, unexpected). For consistency with the new EXPECT_EQ
and ASSERT_EQ usage, as well as consistency with CHECK_NE and DCHECK_NE,
this change also updates these use sites to (actual, unexpected) where
one side can be called “unexpected” as, for example, std::string::npos
can be. Unfortunately, this portion was a manual conversion.
References:
https://github.com/google/googletest/blob/master/googletest/docs/Primer.md#binary-comparison
77d6b17338
https://github.com/google/googletest/pull/713
Change-Id: I978fef7c94183b8b1ef63f12f5ab4d6693626be3
Reviewed-on: https://chromium-review.googlesource.com/466727
Reviewed-by: Scott Graham <scottmg@chromium.org>
348 lines
14 KiB
C++
348 lines
14 KiB
C++
// Copyright 2014 The Crashpad Authors. All rights reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "snapshot/cpu_context.h"
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#include <stddef.h>
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#include <string.h>
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#include <sys/types.h>
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#include "base/macros.h"
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#include "gtest/gtest.h"
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#include "test/hex_string.h"
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namespace crashpad {
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namespace test {
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namespace {
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enum ExponentValue {
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kExponentAllZero = 0,
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kExponentAllOne,
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kExponentNormal,
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};
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enum FractionValue {
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kFractionAllZero = 0,
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kFractionNormal,
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};
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//! \brief Initializes an x87 register to a known bit pattern.
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//!
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//! \param[out] st_mm The x87 register to initialize. The reserved portion of
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//! the register is always zeroed out.
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//! \param[in] exponent_value The bit pattern to use for the exponent. If this
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//! is kExponentAllZero, the sign bit will be set to `1`, and if this is
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//! kExponentAllOne, the sign bit will be set to `0`. This tests that the
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//! implementation doesn’t erroneously consider the sign bit to be part of
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//! the exponent. This may also be kExponentNormal, indicating that the
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//! exponent shall neither be all zeroes nor all ones.
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//! \param[in] j_bit The value to use for the “J bit” (“integer bit”).
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//! \param[in] fraction_value If kFractionAllZero, the fraction will be zeroed
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//! out. If kFractionNormal, the fraction will not be all zeroes.
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void SetX87Register(CPUContextX86::X87Register* st,
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ExponentValue exponent_value,
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bool j_bit,
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FractionValue fraction_value) {
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switch (exponent_value) {
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case kExponentAllZero:
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(*st)[9] = 0x80;
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(*st)[8] = 0;
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break;
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case kExponentAllOne:
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(*st)[9] = 0x7f;
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(*st)[8] = 0xff;
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break;
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case kExponentNormal:
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(*st)[9] = 0x55;
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(*st)[8] = 0x55;
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break;
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}
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uint8_t fraction_pattern = fraction_value == kFractionAllZero ? 0 : 0x55;
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memset(st, fraction_pattern, 8);
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if (j_bit) {
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(*st)[7] |= 0x80;
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} else {
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(*st)[7] &= ~0x80;
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}
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}
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//! \brief Initializes an x87 register to a known bit pattern.
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//!
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//! This behaves as SetX87Register() but also clears the reserved portion of the
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//! field as used in the `fxsave` format.
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void SetX87OrMMXRegister(CPUContextX86::X87OrMMXRegister* st_mm,
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ExponentValue exponent_value,
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bool j_bit,
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FractionValue fraction_value) {
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SetX87Register(&st_mm->st, exponent_value, j_bit, fraction_value);
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memset(st_mm->st_reserved, 0, sizeof(st_mm->st_reserved));
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}
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TEST(CPUContextX86, FxsaveToFsave) {
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// Establish a somewhat plausible fxsave state. Use nonzero values for
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// reserved fields and things that aren’t present in fsave.
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CPUContextX86::Fxsave fxsave;
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fxsave.fcw = 0x027f; // mask exceptions, 53-bit precision, round to nearest
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fxsave.fsw = 1 << 11; // top = 1: logical 0-7 maps to physical 1-7, 0
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fxsave.ftw = 0x1f; // physical 5-7 (logical 4-6) empty
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fxsave.reserved_1 = 0x5a;
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fxsave.fop = 0x1fe; // fsin
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fxsave.fpu_ip = 0x76543210;
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fxsave.fpu_cs = 0x0007;
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fxsave.reserved_2 = 0x5a5a;
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fxsave.fpu_dp = 0xfedcba98;
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fxsave.fpu_ds = 0x000f;
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fxsave.reserved_3 = 0x5a5a;
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fxsave.mxcsr = 0x1f80;
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fxsave.mxcsr_mask = 0xffff;
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SetX87Register(
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&fxsave.st_mm[0].st, kExponentNormal, true, kFractionAllZero); // valid
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SetX87Register(
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&fxsave.st_mm[1].st, kExponentAllZero, false, kFractionAllZero); // zero
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SetX87Register(
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&fxsave.st_mm[2].st, kExponentAllOne, true, kFractionAllZero); // spec.
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SetX87Register(
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&fxsave.st_mm[3].st, kExponentAllOne, true, kFractionNormal); // spec.
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SetX87Register(
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&fxsave.st_mm[4].st, kExponentAllZero, false, kFractionAllZero);
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SetX87Register(
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&fxsave.st_mm[5].st, kExponentAllZero, false, kFractionAllZero);
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SetX87Register(
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&fxsave.st_mm[6].st, kExponentAllZero, false, kFractionAllZero);
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SetX87Register(
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&fxsave.st_mm[7].st, kExponentNormal, true, kFractionNormal); // valid
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for (size_t index = 0; index < arraysize(fxsave.st_mm); ++index) {
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memset(&fxsave.st_mm[index].st_reserved,
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0x5a,
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sizeof(fxsave.st_mm[index].st_reserved));
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}
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memset(&fxsave.xmm, 0x5a, sizeof(fxsave) - offsetof(decltype(fxsave), xmm));
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CPUContextX86::Fsave fsave;
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CPUContextX86::FxsaveToFsave(fxsave, &fsave);
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// Everything should have come over from fxsave. Reserved fields should be
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// zero.
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EXPECT_EQ(fsave.fcw, fxsave.fcw);
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EXPECT_EQ(fsave.reserved_1, 0);
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EXPECT_EQ(fsave.fsw, fxsave.fsw);
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EXPECT_EQ(fsave.reserved_2, 0);
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EXPECT_EQ(fsave.ftw, 0xfe90); // FxsaveToFsaveTagWord
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EXPECT_EQ(fsave.reserved_3, 0);
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EXPECT_EQ(fsave.fpu_ip, fxsave.fpu_ip);
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EXPECT_EQ(fsave.fpu_cs, fxsave.fpu_cs);
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EXPECT_EQ(fsave.fop, fxsave.fop);
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EXPECT_EQ(fsave.fpu_dp, fxsave.fpu_dp);
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EXPECT_EQ(fsave.fpu_ds, fxsave.fpu_ds);
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EXPECT_EQ(fsave.reserved_4, 0);
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for (size_t index = 0; index < arraysize(fsave.st); ++index) {
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EXPECT_EQ(BytesToHexString(fsave.st[index], arraysize(fsave.st[index])),
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BytesToHexString(fxsave.st_mm[index].st,
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arraysize(fxsave.st_mm[index].st)))
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<< "index " << index;
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}
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}
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TEST(CPUContextX86, FsaveToFxsave) {
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// Establish a somewhat plausible fsave state. Use nonzero values for
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// reserved fields.
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CPUContextX86::Fsave fsave;
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fsave.fcw = 0x0300; // unmask exceptions, 64-bit precision, round to nearest
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fsave.reserved_1 = 0xa5a5;
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fsave.fsw = 2 << 11; // top = 2: logical 0-7 maps to physical 2-7, 0-1
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fsave.reserved_2 = 0xa5a5;
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fsave.ftw = 0xa9ff; // physical 0-3 (logical 6-7, 0-1) empty; physical 4
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// (logical 2) zero; physical 5-7 (logical 3-5) special
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fsave.reserved_3 = 0xa5a5;
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fsave.fpu_ip = 0x456789ab;
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fsave.fpu_cs = 0x1013;
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fsave.fop = 0x01ee; // fldz
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fsave.fpu_dp = 0x0123cdef;
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fsave.fpu_ds = 0x2017;
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fsave.reserved_4 = 0xa5a5;
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SetX87Register(&fsave.st[0], kExponentAllZero, false, kFractionNormal);
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SetX87Register(&fsave.st[1], kExponentAllZero, true, kFractionNormal);
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SetX87Register(
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&fsave.st[2], kExponentAllZero, false, kFractionAllZero); // zero
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SetX87Register(
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&fsave.st[3], kExponentAllZero, true, kFractionAllZero); // spec.
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SetX87Register(
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&fsave.st[4], kExponentAllZero, false, kFractionNormal); // spec.
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SetX87Register(
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&fsave.st[5], kExponentAllZero, true, kFractionNormal); // spec.
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SetX87Register(&fsave.st[6], kExponentAllZero, false, kFractionAllZero);
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SetX87Register(&fsave.st[7], kExponentAllZero, true, kFractionAllZero);
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CPUContextX86::Fxsave fxsave;
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CPUContextX86::FsaveToFxsave(fsave, &fxsave);
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// Everything in fsave should have come over from there. Fields not present in
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// fsave and reserved fields should be zero.
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EXPECT_EQ(fxsave.fcw, fsave.fcw);
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EXPECT_EQ(fxsave.fsw, fsave.fsw);
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EXPECT_EQ(fxsave.ftw, 0xf0); // FsaveToFxsaveTagWord
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EXPECT_EQ(fxsave.reserved_1, 0);
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EXPECT_EQ(fxsave.fop, fsave.fop);
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EXPECT_EQ(fxsave.fpu_ip, fsave.fpu_ip);
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EXPECT_EQ(fxsave.fpu_cs, fsave.fpu_cs);
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EXPECT_EQ(fxsave.reserved_2, 0);
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EXPECT_EQ(fxsave.fpu_dp, fsave.fpu_dp);
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EXPECT_EQ(fxsave.fpu_ds, fsave.fpu_ds);
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EXPECT_EQ(fxsave.reserved_3, 0);
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EXPECT_EQ(fxsave.mxcsr, 0u);
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EXPECT_EQ(fxsave.mxcsr_mask, 0u);
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for (size_t index = 0; index < arraysize(fxsave.st_mm); ++index) {
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EXPECT_EQ(BytesToHexString(fxsave.st_mm[index].st,
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arraysize(fxsave.st_mm[index].st)),
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BytesToHexString(fsave.st[index], arraysize(fsave.st[index])))
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<< "index " << index;
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EXPECT_EQ(BytesToHexString(fxsave.st_mm[index].st_reserved,
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arraysize(fxsave.st_mm[index].st_reserved)),
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std::string(arraysize(fxsave.st_mm[index].st_reserved) * 2, '0'))
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<< "index " << index;
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}
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size_t unused_len = sizeof(fxsave) - offsetof(decltype(fxsave), xmm);
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EXPECT_EQ(BytesToHexString(fxsave.xmm, unused_len),
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std::string(unused_len * 2, '0'));
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// Since the fsave format is a subset of the fxsave format, fsave-fxsave-fsave
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// should round-trip cleanly.
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CPUContextX86::Fsave fsave_2;
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CPUContextX86::FxsaveToFsave(fxsave, &fsave_2);
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// Clear the reserved fields in the original fsave structure, since they’re
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// expected to be clear in the copy.
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fsave.reserved_1 = 0;
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fsave.reserved_2 = 0;
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fsave.reserved_3 = 0;
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fsave.reserved_4 = 0;
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EXPECT_EQ(memcmp(&fsave, &fsave_2, sizeof(fsave)), 0);
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}
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TEST(CPUContextX86, FxsaveToFsaveTagWord) {
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// The fsave tag word uses bit pattern 00 for valid, 01 for zero, 10 for
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// “special”, and 11 for empty. Like the fxsave tag word, it is arranged by
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// physical register. The fxsave tag word determines whether a register is
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// empty, and analysis of the x87 register content distinguishes between
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// valid, zero, and special. In the initializations below, comments show
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// whether a register is expected to be considered valid, zero, or special,
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// except where the tag word is expected to indicate that it is empty. Each
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// combination appears twice: once where the fxsave tag word indicates a
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// nonempty register, and once again where it indicates an empty register.
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uint16_t fsw = 0 << 11; // top = 0: logical 0-7 maps to physical 0-7
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uint8_t fxsave_tag = 0x0f; // physical 4-7 (logical 4-7) empty
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CPUContextX86::X87OrMMXRegister st_mm[8];
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SetX87OrMMXRegister(
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&st_mm[0], kExponentNormal, false, kFractionNormal); // spec.
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SetX87OrMMXRegister(
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&st_mm[1], kExponentNormal, true, kFractionNormal); // valid
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SetX87OrMMXRegister(
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&st_mm[2], kExponentNormal, false, kFractionAllZero); // spec.
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SetX87OrMMXRegister(
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&st_mm[3], kExponentNormal, true, kFractionAllZero); // valid
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SetX87OrMMXRegister(&st_mm[4], kExponentNormal, false, kFractionNormal);
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SetX87OrMMXRegister(&st_mm[5], kExponentNormal, true, kFractionNormal);
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SetX87OrMMXRegister(&st_mm[6], kExponentNormal, false, kFractionAllZero);
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SetX87OrMMXRegister(&st_mm[7], kExponentNormal, true, kFractionAllZero);
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EXPECT_EQ(CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm),
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0xff22);
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fsw = 2 << 11; // top = 2: logical 0-7 maps to physical 2-7, 0-1
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fxsave_tag = 0xf0; // physical 0-3 (logical 6-7, 0-1) empty
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SetX87OrMMXRegister(&st_mm[0], kExponentAllZero, false, kFractionNormal);
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SetX87OrMMXRegister(&st_mm[1], kExponentAllZero, true, kFractionNormal);
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SetX87OrMMXRegister(
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&st_mm[2], kExponentAllZero, false, kFractionAllZero); // zero
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SetX87OrMMXRegister(
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&st_mm[3], kExponentAllZero, true, kFractionAllZero); // spec.
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SetX87OrMMXRegister(
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&st_mm[4], kExponentAllZero, false, kFractionNormal); // spec.
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SetX87OrMMXRegister(
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&st_mm[5], kExponentAllZero, true, kFractionNormal); // spec.
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SetX87OrMMXRegister(&st_mm[6], kExponentAllZero, false, kFractionAllZero);
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SetX87OrMMXRegister(&st_mm[7], kExponentAllZero, true, kFractionAllZero);
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EXPECT_EQ(CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm),
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0xa9ff);
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fsw = 5 << 11; // top = 5: logical 0-7 maps to physical 5-7, 0-4
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fxsave_tag = 0x5a; // physical 0, 2, 5, and 7 (logical 5, 0, 2, and 3) empty
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SetX87OrMMXRegister(&st_mm[0], kExponentAllOne, false, kFractionNormal);
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SetX87OrMMXRegister(
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&st_mm[1], kExponentAllOne, true, kFractionNormal); // spec.
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SetX87OrMMXRegister(&st_mm[2], kExponentAllOne, false, kFractionAllZero);
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SetX87OrMMXRegister(&st_mm[3], kExponentAllOne, true, kFractionAllZero);
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SetX87OrMMXRegister(
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&st_mm[4], kExponentAllOne, false, kFractionNormal); // spec.
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SetX87OrMMXRegister(&st_mm[5], kExponentAllOne, true, kFractionNormal);
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SetX87OrMMXRegister(
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&st_mm[6], kExponentAllOne, false, kFractionAllZero); // spec.
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SetX87OrMMXRegister(
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&st_mm[7], kExponentAllOne, true, kFractionAllZero); // spec.
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EXPECT_EQ(CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm),
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0xeebb);
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// This set set is just a mix of all of the possible tag types in a single
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// register file.
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fsw = 1 << 11; // top = 1: logical 0-7 maps to physical 1-7, 0
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fxsave_tag = 0x1f; // physical 5-7 (logical 4-6) empty
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SetX87OrMMXRegister(
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&st_mm[0], kExponentNormal, true, kFractionAllZero); // valid
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SetX87OrMMXRegister(
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&st_mm[1], kExponentAllZero, false, kFractionAllZero); // zero
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SetX87OrMMXRegister(
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&st_mm[2], kExponentAllOne, true, kFractionAllZero); // spec.
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SetX87OrMMXRegister(
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&st_mm[3], kExponentAllOne, true, kFractionNormal); // spec.
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SetX87OrMMXRegister(&st_mm[4], kExponentAllZero, false, kFractionAllZero);
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SetX87OrMMXRegister(&st_mm[5], kExponentAllZero, false, kFractionAllZero);
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SetX87OrMMXRegister(&st_mm[6], kExponentAllZero, false, kFractionAllZero);
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SetX87OrMMXRegister(
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&st_mm[7], kExponentNormal, true, kFractionNormal); // valid
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EXPECT_EQ(CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm),
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0xfe90);
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// In this set, everything is valid.
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fsw = 0 << 11; // top = 0: logical 0-7 maps to physical 0-7
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fxsave_tag = 0xff; // nothing empty
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for (size_t index = 0; index < arraysize(st_mm); ++index) {
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SetX87OrMMXRegister(&st_mm[index], kExponentNormal, true, kFractionAllZero);
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}
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EXPECT_EQ(CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm), 0);
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// In this set, everything is empty. The registers shouldn’t be consulted at
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// all, so they’re left alone from the previous set.
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fsw = 0 << 11; // top = 0: logical 0-7 maps to physical 0-7
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fxsave_tag = 0; // everything empty
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EXPECT_EQ(CPUContextX86::FxsaveToFsaveTagWord(fsw, fxsave_tag, st_mm),
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0xffff);
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}
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TEST(CPUContextX86, FsaveToFxsaveTagWord) {
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// The register sets that these x87 tag words might apply to are given in the
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// FxsaveToFsaveTagWord test above.
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EXPECT_EQ(CPUContextX86::FsaveToFxsaveTagWord(0xff22), 0x0f);
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EXPECT_EQ(CPUContextX86::FsaveToFxsaveTagWord(0xa9ff), 0xf0);
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EXPECT_EQ(CPUContextX86::FsaveToFxsaveTagWord(0xeebb), 0x5a);
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EXPECT_EQ(CPUContextX86::FsaveToFxsaveTagWord(0xfe90), 0x1f);
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EXPECT_EQ(CPUContextX86::FsaveToFxsaveTagWord(0x0000), 0xff);
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EXPECT_EQ(CPUContextX86::FsaveToFxsaveTagWord(0xffff), 0x00);
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}
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} // namespace
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} // namespace test
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||
} // namespace crashpad
|