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<title>Crashpad: crashpad::CPUContextX86::Fsave Struct Reference</title>
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<li class="navelem"><a class="el" href="namespacecrashpad.html">crashpad</a></li><li class="navelem"><a class="el" href="structcrashpad_1_1CPUContextX86.html">CPUContextX86</a></li><li class="navelem"><a class="el" href="structcrashpad_1_1CPUContextX86_1_1Fsave.html">Fsave</a></li> </ul>
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<a href="#pub-attribs">Public Attributes</a> |
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<div class="title">crashpad::CPUContextX86::Fsave Struct Reference</div> </div>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:acd21406ba078a16fcbff95e9469726cd"><td class="memItemLeft" align="right" valign="top"><a id="acd21406ba078a16fcbff95e9469726cd"></a>
uint16_t </td><td class="memItemRight" valign="bottom"><b>fcw</b></td></tr>
<tr class="separator:acd21406ba078a16fcbff95e9469726cd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afcd7ac97b17c802be50c624fc31e0aec"><td class="memItemLeft" align="right" valign="top"><a id="afcd7ac97b17c802be50c624fc31e0aec"></a>
uint16_t </td><td class="memItemRight" valign="bottom"><b>reserved_1</b></td></tr>
<tr class="separator:afcd7ac97b17c802be50c624fc31e0aec"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1ac83f7d2daba2af68b2d8e247b1159c"><td class="memItemLeft" align="right" valign="top"><a id="a1ac83f7d2daba2af68b2d8e247b1159c"></a>
uint16_t </td><td class="memItemRight" valign="bottom"><b>fsw</b></td></tr>
<tr class="separator:a1ac83f7d2daba2af68b2d8e247b1159c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4c1bfcec002c023c4a52baf389966441"><td class="memItemLeft" align="right" valign="top"><a id="a4c1bfcec002c023c4a52baf389966441"></a>
uint16_t </td><td class="memItemRight" valign="bottom"><b>reserved_2</b></td></tr>
<tr class="separator:a4c1bfcec002c023c4a52baf389966441"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afb442c5faf3a85db2f819cb00bc9952a"><td class="memItemLeft" align="right" valign="top"><a id="afb442c5faf3a85db2f819cb00bc9952a"></a>
uint16_t </td><td class="memItemRight" valign="bottom"><b>ftw</b></td></tr>
<tr class="separator:afb442c5faf3a85db2f819cb00bc9952a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a45f31cd186d06325e1b97c8d1ccac10f"><td class="memItemLeft" align="right" valign="top"><a id="a45f31cd186d06325e1b97c8d1ccac10f"></a>
uint16_t </td><td class="memItemRight" valign="bottom"><b>reserved_3</b></td></tr>
<tr class="separator:a45f31cd186d06325e1b97c8d1ccac10f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:adede648a3fffdb3f92c9bae3cff7dbf6"><td class="memItemLeft" align="right" valign="top"><a id="adede648a3fffdb3f92c9bae3cff7dbf6"></a>
uint32_t </td><td class="memItemRight" valign="bottom"><b>fpu_ip</b></td></tr>
<tr class="separator:adede648a3fffdb3f92c9bae3cff7dbf6"><td class="memSeparator" colspan="2"> </td></tr>
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uint16_t </td><td class="memItemRight" valign="bottom"><b>fpu_cs</b></td></tr>
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uint16_t </td><td class="memItemRight" valign="bottom"><b>fop</b></td></tr>
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uint32_t </td><td class="memItemRight" valign="bottom"><b>fpu_dp</b></td></tr>
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uint16_t </td><td class="memItemRight" valign="bottom"><b>fpu_ds</b></td></tr>
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uint16_t </td><td class="memItemRight" valign="bottom"><b>reserved_4</b></td></tr>
<tr class="separator:a5ac672e4ad7dad428c2d9545ac601c22"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abefb4f055f1c77959a93160529ff4c99"><td class="memItemLeft" align="right" valign="top"><a id="abefb4f055f1c77959a93160529ff4c99"></a>
X87Register </td><td class="memItemRight" valign="bottom"><b>st</b> [8]</td></tr>
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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>snapshot/cpu_context.h</li>
</ul>
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