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85 lines
3.4 KiB
C++
85 lines
3.4 KiB
C++
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// Copyright 2018 The Crashpad Authors. All rights reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "util/misc/capture_context_test_util.h"
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#include "gtest/gtest.h"
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#include "util/misc/implicit_cast.h"
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namespace crashpad {
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namespace test {
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void SanityCheckContext(const NativeCPUContext& context) {
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#if defined(ARCH_CPU_X86)
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ASSERT_EQ(implicit_cast<thread_state_flavor_t>(context.tsh.flavor),
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implicit_cast<thread_state_flavor_t>(x86_THREAD_STATE32));
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ASSERT_EQ(implicit_cast<uint32_t>(context.tsh.count),
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implicit_cast<uint32_t>(x86_THREAD_STATE32_COUNT));
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#elif defined(ARCH_CPU_X86_64)
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ASSERT_EQ(implicit_cast<thread_state_flavor_t>(context.tsh.flavor),
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implicit_cast<thread_state_flavor_t>(x86_THREAD_STATE64));
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ASSERT_EQ(implicit_cast<uint32_t>(context.tsh.count),
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implicit_cast<uint32_t>(x86_THREAD_STATE64_COUNT));
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#endif
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#if defined(ARCH_CPU_X86_FAMILY)
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// The segment registers are only capable of storing 16-bit quantities, but
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// the context structure provides native integer-width fields for them. Ensure
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// that the high bits are all clear.
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//
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// Many bit positions in the flags register are reserved and will always read
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// a known value. Most reserved bits are always 0, but bit 1 is always 1.
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// Check that the reserved bits are all set to their expected values. Note
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// that the set of reserved bits may be relaxed over time with newer CPUs, and
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// that this test may need to be changed to reflect these developments. The
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// current set of reserved bits are 1, 3, 5, 15, and 22 and higher. See Intel
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// Software Developer’s Manual, Volume 1: Basic Architecture (253665-051),
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// 3.4.3 “EFLAGS Register”, and AMD Architecture Programmer’s Manual, Volume
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// 2: System Programming (24593-3.24), 3.1.6 “RFLAGS Register”.
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#if defined(ARCH_CPU_X86)
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EXPECT_EQ(context.uts.ts32.__cs & ~0xffff, 0u);
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EXPECT_EQ(context.uts.ts32.__ds & ~0xffff, 0u);
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EXPECT_EQ(context.uts.ts32.__es & ~0xffff, 0u);
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EXPECT_EQ(context.uts.ts32.__fs & ~0xffff, 0u);
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EXPECT_EQ(context.uts.ts32.__gs & ~0xffff, 0u);
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EXPECT_EQ(context.uts.ts32.__ss & ~0xffff, 0u);
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EXPECT_EQ(context.uts.ts32.__eflags & 0xffc0802a, 2u);
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#elif defined(ARCH_CPU_X86_64)
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EXPECT_EQ(context.uts.ts64.__cs & ~UINT64_C(0xffff), 0u);
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EXPECT_EQ(context.uts.ts64.__fs & ~UINT64_C(0xffff), 0u);
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EXPECT_EQ(context.uts.ts64.__gs & ~UINT64_C(0xffff), 0u);
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EXPECT_EQ(context.uts.ts64.__rflags & UINT64_C(0xffffffffffc0802a), 2u);
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#endif
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#endif
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}
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uintptr_t ProgramCounterFromContext(const NativeCPUContext& context) {
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#if defined(ARCH_CPU_X86)
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return context.uts.ts32.__eip;
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#elif defined(ARCH_CPU_X86_64)
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return context.uts.ts64.__rip;
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#endif
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}
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uintptr_t StackPointerFromContext(const NativeCPUContext& context) {
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#if defined(ARCH_CPU_X86)
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return context.uts.ts32.__esp;
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#elif defined(ARCH_CPU_X86_64)
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return context.uts.ts64.__rsp;
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#endif
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}
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} // namespace test
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} // namespace crashpad
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