2022-09-06 19:14:07 -04:00
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// Copyright 2014 The Crashpad Authors
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2014-10-02 17:09:37 -04:00
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "snapshot/cpu_context.h"
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2017-03-22 21:44:05 -04:00
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#include <stddef.h>
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2017-02-16 13:25:29 -05:00
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#include <string.h>
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2022-02-28 20:57:19 -08:00
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#include <iterator>
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2020-06-22 11:14:31 +02:00
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#include "base/notreached.h"
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2023-06-08 21:08:54 +00:00
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#include "cpu_architecture.h"
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2019-01-03 13:36:02 -05:00
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#include "util/misc/arraysize.h"
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2015-09-14 11:09:46 -07:00
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#include "util/misc/implicit_cast.h"
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2014-10-02 17:09:37 -04:00
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namespace crashpad {
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2017-02-14 16:27:22 -05:00
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namespace {
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2017-02-16 13:25:29 -05:00
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// Sanity-check complex structures to ensure interoperability.
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static_assert(sizeof(CPUContextX86::Fsave) == 108, "CPUContextX86::Fsave size");
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static_assert(sizeof(CPUContextX86::Fxsave) == 512,
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"CPUContextX86::Fxsave size");
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static_assert(sizeof(CPUContextX86_64::Fxsave) == 512,
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"CPUContextX86_64::Fxsave size");
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2017-02-14 16:27:22 -05:00
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enum {
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kX87TagValid = 0,
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kX87TagZero,
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kX87TagSpecial,
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kX87TagEmpty,
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};
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} // namespace
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2017-02-16 13:25:29 -05:00
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// static
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void CPUContextX86::FxsaveToFsave(const Fxsave& fxsave, Fsave* fsave) {
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fsave->fcw = fxsave.fcw;
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fsave->reserved_1 = 0;
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fsave->fsw = fxsave.fsw;
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fsave->reserved_2 = 0;
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fsave->ftw = FxsaveToFsaveTagWord(fxsave.fsw, fxsave.ftw, fxsave.st_mm);
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fsave->reserved_3 = 0;
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fsave->fpu_ip = fxsave.fpu_ip;
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fsave->fpu_cs = fxsave.fpu_cs;
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fsave->fop = fxsave.fop;
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fsave->fpu_dp = fxsave.fpu_dp;
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fsave->fpu_ds = fxsave.fpu_ds;
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fsave->reserved_4 = 0;
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static_assert(ArraySize(fsave->st) == ArraySize(fxsave.st_mm),
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"FPU stack registers must be equivalent");
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for (size_t index = 0; index < std::size(fsave->st); ++index) {
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memcpy(fsave->st[index], fxsave.st_mm[index].st, sizeof(fsave->st[index]));
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}
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}
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// static
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void CPUContextX86::FsaveToFxsave(const Fsave& fsave, Fxsave* fxsave) {
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fxsave->fcw = fsave.fcw;
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fxsave->fsw = fsave.fsw;
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fxsave->ftw = FsaveToFxsaveTagWord(fsave.ftw);
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fxsave->reserved_1 = 0;
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fxsave->fop = fsave.fop;
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fxsave->fpu_ip = fsave.fpu_ip;
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fxsave->fpu_cs = fsave.fpu_cs;
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fxsave->reserved_2 = 0;
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fxsave->fpu_dp = fsave.fpu_dp;
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fxsave->fpu_ds = fsave.fpu_ds;
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fxsave->reserved_3 = 0;
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fxsave->mxcsr = 0;
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fxsave->mxcsr_mask = 0;
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static_assert(ArraySize(fxsave->st_mm) == ArraySize(fsave.st),
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"FPU stack registers must be equivalent");
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for (size_t index = 0; index < std::size(fsave.st); ++index) {
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memcpy(fxsave->st_mm[index].st, fsave.st[index], sizeof(fsave.st[index]));
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memset(fxsave->st_mm[index].st_reserved,
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0,
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sizeof(fxsave->st_mm[index].st_reserved));
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}
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memset(fxsave->xmm, 0, sizeof(*fxsave) - offsetof(Fxsave, xmm));
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}
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2014-11-03 17:43:39 -05:00
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// static
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uint16_t CPUContextX86::FxsaveToFsaveTagWord(
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uint16_t fsw,
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uint8_t fxsave_tag,
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const CPUContextX86::X87OrMMXRegister st_mm[8]) {
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// The x87 tag word (in both abridged and full form) identifies physical
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// registers, but |st_mm| is arranged in logical stack order. In order to map
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// physical tag word bits to the logical stack registers they correspond to,
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// the “stack top” value from the x87 status word is necessary.
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int stack_top = (fsw >> 11) & 0x7;
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uint16_t fsave_tag = 0;
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for (int physical_index = 0; physical_index < 8; ++physical_index) {
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bool fxsave_bit = (fxsave_tag & (1 << physical_index)) != 0;
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uint8_t fsave_bits;
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if (fxsave_bit) {
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int st_index = (physical_index + 8 - stack_top) % 8;
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const CPUContextX86::X87Register& st = st_mm[st_index].st;
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uint32_t exponent = ((st[9] & 0x7f) << 8) | st[8];
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if (exponent == 0x7fff) {
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// Infinity, NaN, pseudo-infinity, or pseudo-NaN. If it was important to
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// distinguish between these, the J bit and the M bit (the most
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// significant bit of |fraction|) could be consulted.
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fsave_bits = kX87TagSpecial;
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} else {
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// The integer bit the “J bit”.
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bool integer_bit = (st[7] & 0x80) != 0;
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if (exponent == 0) {
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uint64_t fraction = ((implicit_cast<uint64_t>(st[7]) & 0x7f) << 56) |
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(implicit_cast<uint64_t>(st[6]) << 48) |
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(implicit_cast<uint64_t>(st[5]) << 40) |
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(implicit_cast<uint64_t>(st[4]) << 32) |
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(implicit_cast<uint32_t>(st[3]) << 24) |
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(st[2] << 16) | (st[1] << 8) | st[0];
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if (!integer_bit && fraction == 0) {
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fsave_bits = kX87TagZero;
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} else {
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// Denormal (if the J bit is clear) or pseudo-denormal.
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fsave_bits = kX87TagSpecial;
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}
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} else if (integer_bit) {
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fsave_bits = kX87TagValid;
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} else {
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// Unnormal.
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fsave_bits = kX87TagSpecial;
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}
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}
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} else {
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fsave_bits = kX87TagEmpty;
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}
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fsave_tag |= (fsave_bits << (physical_index * 2));
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}
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return fsave_tag;
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}
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2017-02-14 16:27:22 -05:00
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// static
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uint8_t CPUContextX86::FsaveToFxsaveTagWord(uint16_t fsave_tag) {
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uint8_t fxsave_tag = 0;
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for (int physical_index = 0; physical_index < 8; ++physical_index) {
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const uint8_t fsave_bits = (fsave_tag >> (physical_index * 2)) & 0x3;
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const bool fxsave_bit = fsave_bits != kX87TagEmpty;
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fxsave_tag |= fxsave_bit << physical_index;
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}
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return fxsave_tag;
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}
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2014-10-02 17:09:37 -04:00
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uint64_t CPUContext::InstructionPointer() const {
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switch (architecture) {
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case kCPUArchitectureX86:
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return x86->eip;
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case kCPUArchitectureX86_64:
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return x86_64->rip;
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case kCPUArchitectureARM:
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return arm->pc;
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case kCPUArchitectureARM64:
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return arm64->pc;
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case kCPUArchitectureRISCV64:
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return riscv64->pc;
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default:
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NOTREACHED_IN_MIGRATION();
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2014-12-19 14:53:23 -08:00
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return ~0ull;
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}
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}
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2018-05-15 11:04:20 -07:00
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uint64_t CPUContext::StackPointer() const {
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switch (architecture) {
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case kCPUArchitectureX86:
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return x86->esp;
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case kCPUArchitectureX86_64:
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return x86_64->rsp;
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case kCPUArchitectureARM:
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return arm->sp;
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case kCPUArchitectureARM64:
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return arm64->sp;
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case kCPUArchitectureRISCV64:
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return riscv64->regs[1];
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2018-05-15 11:04:20 -07:00
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default:
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NOTREACHED_IN_MIGRATION();
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2018-05-15 11:04:20 -07:00
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return ~0ull;
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}
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}
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2022-05-14 22:40:17 -07:00
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uint64_t CPUContext::ShadowStackPointer() const {
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switch (architecture) {
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case kCPUArchitectureX86:
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case kCPUArchitectureARM:
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case kCPUArchitectureARM64:
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NOTREACHED_IN_MIGRATION();
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return 0;
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case kCPUArchitectureX86_64:
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return x86_64->xstate.cet_u.ssp;
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default:
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NOTREACHED_IN_MIGRATION();
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return ~0ull;
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}
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}
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bool CPUContext::HasShadowStack() const {
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switch (architecture) {
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case kCPUArchitectureX86:
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case kCPUArchitectureARM:
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case kCPUArchitectureARM64:
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return false;
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case kCPUArchitectureX86_64:
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return x86_64->xstate.cet_u.cetmsr != 0;
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default:
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NOTREACHED_IN_MIGRATION();
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return false;
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}
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}
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2018-06-11 09:38:24 -07:00
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bool CPUContext::Is64Bit() const {
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switch (architecture) {
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case kCPUArchitectureX86_64:
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case kCPUArchitectureARM64:
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2018-07-10 11:17:22 +02:00
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case kCPUArchitectureMIPS64EL:
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case kCPUArchitectureRISCV64:
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return true;
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case kCPUArchitectureX86:
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case kCPUArchitectureARM:
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2018-07-10 11:17:22 +02:00
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case kCPUArchitectureMIPSEL:
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return false;
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default:
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NOTREACHED_IN_MIGRATION();
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return false;
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}
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}
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2014-10-02 17:09:37 -04:00
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} // namespace crashpad
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